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From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Michał Mirosław" <mirq-linux@rere.qmqm.pl>,
	"Nikola Milosavljević" <mnidza@outlook.com>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Nicolas Chauvet" <kwizart@gmail.com>,
	"Viresh Kumar" <vireshk@kernel.org>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Matt Merhar" <mattmerhar@protonmail.com>,
	"Paul Fertser" <fercerpav@gmail.com>,
	"Mark Brown" <broonie@kernel.org>,
	"Liam Girdwood" <lgirdwood@gmail.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com>,
	"Mikko Perttunen" <mperttunen@nvidia.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
	devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
	Nathan Chancellor <nathan@kernel.org>,
	linux-clk@vger.kernel.org
Subject: [PATCH v3 06/14] clk: tegra: Add stubs needed for compile-testing
Date: Thu, 27 May 2021 23:47:34 +0300	[thread overview]
Message-ID: <20210527204742.10379-7-digetx@gmail.com> (raw)
In-Reply-To: <20210527204742.10379-1-digetx@gmail.com>

Add stubs needed for compile-testing of Tegra memory drivers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 include/linux/clk/tegra.h | 96 ++++++++++++++++++++++++++++++---------
 1 file changed, 75 insertions(+), 21 deletions(-)

diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index f7ff722a03dd..5667fe7a979c 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -123,20 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
-extern int tegra210_plle_hw_sequence_start(void);
-extern bool tegra210_plle_hw_sequence_is_enabled(void);
-extern void tegra210_xusb_pll_hw_control_enable(void);
-extern void tegra210_xusb_pll_hw_sequence_start(void);
-extern void tegra210_sata_pll_hw_control_enable(void);
-extern void tegra210_sata_pll_hw_sequence_start(void);
-extern void tegra210_set_sata_pll_seq_sw(bool state);
-extern void tegra210_put_utmipll_in_iddq(void);
-extern void tegra210_put_utmipll_out_iddq(void);
-extern int tegra210_clk_handle_mbist_war(unsigned int id);
-extern void tegra210_clk_emc_dll_enable(bool flag);
-extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
-extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
-
 struct clk;
 struct tegra_emc;
 
@@ -144,17 +130,10 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
 					unsigned long min_rate,
 					unsigned long max_rate,
 					void *arg);
-
-void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
-					void *cb_arg);
-int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
-
 typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,
 						    unsigned long rate);
 typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,
 						      unsigned long rate);
-void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
-				    tegra124_emc_complete_timing_change_cb *complete_cb);
 
 struct tegra210_clk_emc_config {
 	unsigned long rate;
@@ -176,8 +155,83 @@ struct tegra210_clk_emc_provider {
 			const struct tegra210_clk_emc_config *config);
 };
 
+#ifdef CONFIG_ARCH_TEGRA
+void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
+					void *cb_arg);
+int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
+
+void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
+				    tegra124_emc_complete_timing_change_cb *complete_cb);
+
+int tegra210_plle_hw_sequence_start(void);
+bool tegra210_plle_hw_sequence_is_enabled(void);
+void tegra210_xusb_pll_hw_control_enable(void);
+void tegra210_xusb_pll_hw_sequence_start(void);
+void tegra210_sata_pll_hw_control_enable(void);
+void tegra210_sata_pll_hw_sequence_start(void);
+void tegra210_set_sata_pll_seq_sw(bool state);
+void tegra210_put_utmipll_in_iddq(void);
+void tegra210_put_utmipll_out_iddq(void);
+int tegra210_clk_handle_mbist_war(unsigned int id);
+void tegra210_clk_emc_dll_enable(bool flag);
+void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
+void tegra210_clk_emc_update_setting(u32 emc_src_value);
+
 int tegra210_clk_emc_attach(struct clk *clk,
 			    struct tegra210_clk_emc_provider *provider);
 void tegra210_clk_emc_detach(struct clk *clk);
+#else
+static inline void
+tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
+				   void *cb_arg)
+{
+}
+
+static inline int
+tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
+{
+	return 0;
+}
+
+static inline void
+tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
+			       tegra124_emc_complete_timing_change_cb *complete_cb)
+{
+}
+
+static inline int tegra210_plle_hw_sequence_start(void)
+{
+	return 0;
+}
+
+static inline bool tegra210_plle_hw_sequence_is_enabled(void)
+{
+	return false;
+}
+
+static inline int tegra210_clk_handle_mbist_war(unsigned int id)
+{
+	return 0;
+}
+
+static inline int
+tegra210_clk_emc_attach(struct clk *clk,
+			struct tegra210_clk_emc_provider *provider);
+{
+	return 0;
+}
+
+static inline void tegra210_xusb_pll_hw_control_enable(void) {}
+static inline void tegra210_xusb_pll_hw_sequence_start(void) {}
+static inline void tegra210_sata_pll_hw_control_enable(void) {}
+static inline void tegra210_sata_pll_hw_sequence_start(void) {}
+static inline void tegra210_set_sata_pll_seq_sw(bool state) {}
+static inline void tegra210_put_utmipll_in_iddq(void) {}
+static inline void tegra210_put_utmipll_out_iddq(void) {}
+static inline void tegra210_clk_emc_dll_enable(bool flag) {}
+static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {}
+static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {}
+static inline void tegra210_clk_emc_detach(struct clk *clk) {}
+#endif
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
-- 
2.30.2


  parent reply	other threads:[~2021-05-27 20:48 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-27 20:47 [PATCH v3 00/14] NVIDIA Tegra memory and power management changes for 5.14 Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 01/14] regulator: core: Add regulator_sync_voltage_rdev() Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 02/14] soc/tegra: regulators: Bump voltages on system reboot Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 03/14] soc/tegra: Add stub for soc_is_tegra() Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 04/14] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 05/14] soc/tegra: fuse: Add stubs needed for compile-testing Dmitry Osipenko
2021-05-27 20:47 ` Dmitry Osipenko [this message]
2021-05-27 20:47 ` [PATCH v3 07/14] memory: tegra: Fix compilation warnings on 64bit platforms Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 08/14] memory: tegra: Enable compile testing for all drivers Dmitry Osipenko
2021-05-27 22:30   ` kernel test robot
2021-05-27 22:36     ` Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 09/14] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 10/14] memory: tegra30-emc: " Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 11/14] dt-bindings: soc: tegra-pmc: Document core power domain Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 12/14] soc/tegra: pmc: Add " Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 13/14] soc/tegra: pmc: Add driver state syncing Dmitry Osipenko
2021-05-27 20:47 ` [PATCH v3 14/14] soc/tegra: regulators: Support core domain " Dmitry Osipenko

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