* [PATCH v7 01/27] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 02/27] tcg: Add tcg_call_flags Richard Henderson
` (27 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
We will shortly be interested in distinguishing pointers
from integers in the helper's declaration, as well as a
true void return. We currently have two parallel 1 bit
fields; merge them and expand to a 3 bit field.
Our current maximum is 7 helper arguments, plus the return
makes 8 * 3 = 24 bits used within the uint32_t typemask.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/helper-head.h | 37 +++++--------------
include/exec/helper-tcg.h | 34 ++++++++---------
target/hppa/helper.h | 3 --
| 3 --
target/m68k/helper.h | 1 -
target/ppc/helper.h | 3 --
tcg/tcg.c | 71 +++++++++++++++++++++---------------
7 files changed, 67 insertions(+), 85 deletions(-)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 3094c7946d..b974eb394a 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -85,32 +85,14 @@
#define dh_retvar_ptr tcgv_ptr_temp(retval)
#define dh_retvar(t) glue(dh_retvar_, dh_alias(t))
-#define dh_is_64bit_void 0
-#define dh_is_64bit_noreturn 0
-#define dh_is_64bit_i32 0
-#define dh_is_64bit_i64 1
-#define dh_is_64bit_ptr (sizeof(void *) == 8)
-#define dh_is_64bit_cptr dh_is_64bit_ptr
-#define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t))
-
-#define dh_is_signed_void 0
-#define dh_is_signed_noreturn 0
-#define dh_is_signed_i32 0
-#define dh_is_signed_s32 1
-#define dh_is_signed_i64 0
-#define dh_is_signed_s64 1
-#define dh_is_signed_f16 0
-#define dh_is_signed_f32 0
-#define dh_is_signed_f64 0
-#define dh_is_signed_tl 0
-#define dh_is_signed_int 1
-/* ??? This is highly specific to the host cpu. There are even special
- extension instructions that may be required, e.g. ia64's addp4. But
- for now we don't support any 64-bit targets with 32-bit pointers. */
-#define dh_is_signed_ptr 0
-#define dh_is_signed_cptr dh_is_signed_ptr
-#define dh_is_signed_env dh_is_signed_ptr
-#define dh_is_signed(t) dh_is_signed_##t
+#define dh_typecode_void 0
+#define dh_typecode_noreturn 0
+#define dh_typecode_i32 2
+#define dh_typecode_s32 3
+#define dh_typecode_i64 4
+#define dh_typecode_s64 5
+#define dh_typecode_ptr 6
+#define dh_typecode(t) glue(dh_typecode_, dh_alias(t))
#define dh_callflag_i32 0
#define dh_callflag_s32 0
@@ -126,8 +108,7 @@
#define dh_callflag_noreturn TCG_CALL_NO_RETURN
#define dh_callflag(t) glue(dh_callflag_, dh_alias(t))
-#define dh_sizemask(t, n) \
- ((dh_is_64bit(t) << (n*2)) | (dh_is_signed(t) << (n*2+1)))
+#define dh_typemask(t, n) (dh_typecode(t) << (n * 3))
#define dh_arg(t, n) \
glue(glue(tcgv_, dh_alias(t)), _temp)(glue(arg, n))
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
index 6888514635..16cd318b83 100644
--- a/include/exec/helper-tcg.h
+++ b/include/exec/helper-tcg.h
@@ -13,50 +13,50 @@
#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) },
+ .typemask = dh_typemask(ret, 0) },
#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) },
#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
- | dh_sizemask(t2, 2) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
+ | dh_typemask(t2, 2) },
#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
- | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
+ | dh_typemask(t2, 2) | dh_typemask(t3, 3) },
#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
- | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
+ | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) },
#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
- | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
- | dh_sizemask(t5, 5) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
+ | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \
+ | dh_typemask(t5, 5) },
#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \
{ .func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(ret), \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
- | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
- | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
+ | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \
+ | dh_typemask(t5, 5) | dh_typemask(t6, 6) },
#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
{ .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
- .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
- | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
- | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
+ .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \
+ | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \
+ | dh_typemask(t5, 5) | dh_typemask(t6, 6) | dh_typemask(t7, 7) },
#include "helper.h"
#include "trace/generated-helpers.h"
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 2d483aab58..0a629ffa7c 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -1,12 +1,9 @@
#if TARGET_REGISTER_BITS == 64
# define dh_alias_tr i64
-# define dh_is_64bit_tr 1
#else
# define dh_alias_tr i32
-# define dh_is_64bit_tr 0
#endif
#define dh_ctype_tr target_ureg
-#define dh_is_signed_tr 0
DEF_HELPER_2(excp, noreturn, env, int)
DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr)
--git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 6c0c849347..e68af5c403 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -30,9 +30,6 @@
#define dh_ctype_Reg Reg *
#define dh_ctype_ZMMReg ZMMReg *
#define dh_ctype_MMXReg MMXReg *
-#define dh_is_signed_Reg dh_is_signed_ptr
-#define dh_is_signed_ZMMReg dh_is_signed_ptr
-#define dh_is_signed_MMXReg dh_is_signed_ptr
DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index 77808497a9..9842eeaa95 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -17,7 +17,6 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
#define dh_alias_fp ptr
#define dh_ctype_fp FPReg *
-#define dh_is_signed_fp dh_is_signed_ptr
DEF_HELPER_3(exts32, void, env, fp, s32)
DEF_HELPER_3(extf32, void, env, fp, f32)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea9f2a236c..c3cb9f1c3f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -108,11 +108,9 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
-#define dh_is_signed_avr dh_is_signed_ptr
#define dh_alias_vsr ptr
#define dh_ctype_vsr ppc_vsr_t *
-#define dh_is_signed_vsr dh_is_signed_ptr
DEF_HELPER_3(vavgub, void, avr, avr, avr)
DEF_HELPER_3(vavguh, void, avr, avr, avr)
@@ -696,7 +694,6 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl)
#define dh_alias_fprp ptr
#define dh_ctype_fprp ppc_fprp_t *
-#define dh_is_signed_fprp dh_is_signed_ptr
DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp)
DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index db806a6658..5c9a89d22d 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1087,7 +1087,7 @@ typedef struct TCGHelperInfo {
void *func;
const char *name;
unsigned flags;
- unsigned sizemask;
+ unsigned typemask;
} TCGHelperInfo;
#include "exec/helper-proto.h"
@@ -1962,13 +1962,13 @@ bool tcg_op_supported(TCGOpcode op)
void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
{
int i, real_args, nb_rets, pi;
- unsigned sizemask, flags;
+ unsigned typemask, flags;
TCGHelperInfo *info;
TCGOp *op;
info = g_hash_table_lookup(helper_table, (gpointer)func);
flags = info->flags;
- sizemask = info->sizemask;
+ typemask = info->typemask;
#ifdef CONFIG_PLUGIN
/* detect non-plugin helpers */
@@ -1981,36 +1981,41 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
&& !defined(CONFIG_TCG_INTERPRETER)
/* We have 64-bit values in one register, but need to pass as two
separate parameters. Split them. */
- int orig_sizemask = sizemask;
+ int orig_typemask = typemask;
int orig_nargs = nargs;
TCGv_i64 retl, reth;
TCGTemp *split_args[MAX_OPC_PARAM];
retl = NULL;
reth = NULL;
- if (sizemask != 0) {
- for (i = real_args = 0; i < nargs; ++i) {
- int is_64bit = sizemask & (1 << (i+1)*2);
- if (is_64bit) {
- TCGv_i64 orig = temp_tcgv_i64(args[i]);
- TCGv_i32 h = tcg_temp_new_i32();
- TCGv_i32 l = tcg_temp_new_i32();
- tcg_gen_extr_i64_i32(l, h, orig);
- split_args[real_args++] = tcgv_i32_temp(h);
- split_args[real_args++] = tcgv_i32_temp(l);
- } else {
- split_args[real_args++] = args[i];
- }
+ typemask = 0;
+ for (i = real_args = 0; i < nargs; ++i) {
+ int argtype = extract32(orig_typemask, (i + 1) * 3, 3);
+ bool is_64bit = (argtype & ~1) == dh_typecode_i64;
+
+ if (is_64bit) {
+ TCGv_i64 orig = temp_tcgv_i64(args[i]);
+ TCGv_i32 h = tcg_temp_new_i32();
+ TCGv_i32 l = tcg_temp_new_i32();
+ tcg_gen_extr_i64_i32(l, h, orig);
+ split_args[real_args++] = tcgv_i32_temp(h);
+ typemask |= dh_typecode_i32 << (real_args * 3);
+ split_args[real_args++] = tcgv_i32_temp(l);
+ typemask |= dh_typecode_i32 << (real_args * 3);
+ } else {
+ split_args[real_args++] = args[i];
+ typemask |= argtype << (real_args * 3);
}
- nargs = real_args;
- args = split_args;
- sizemask = 0;
}
+ nargs = real_args;
+ args = split_args;
#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
for (i = 0; i < nargs; ++i) {
- int is_64bit = sizemask & (1 << (i+1)*2);
- int is_signed = sizemask & (2 << (i+1)*2);
- if (!is_64bit) {
+ int argtype = extract32(typemask, (i + 1) * 3, 3);
+ bool is_32bit = (argtype & ~1) == dh_typecode_i32;
+ bool is_signed = argtype & 1;
+
+ if (is_32bit) {
TCGv_i64 temp = tcg_temp_new_i64();
TCGv_i64 orig = temp_tcgv_i64(args[i]);
if (is_signed) {
@@ -2029,7 +2034,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
if (ret != NULL) {
#if defined(__sparc__) && !defined(__arch64__) \
&& !defined(CONFIG_TCG_INTERPRETER)
- if (orig_sizemask & 1) {
+ if ((typemask & 6) == dh_typecode_i64) {
/* The 32-bit ABI is going to return the 64-bit value in
the %o0/%o1 register pair. Prepare for this by using
two return temporaries, and reassemble below. */
@@ -2043,7 +2048,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
nb_rets = 1;
}
#else
- if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
+ if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) == dh_typecode_i64) {
#ifdef HOST_WORDS_BIGENDIAN
op->args[pi++] = temp_arg(ret + 1);
op->args[pi++] = temp_arg(ret);
@@ -2064,7 +2069,9 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
real_args = 0;
for (i = 0; i < nargs; i++) {
- int is_64bit = sizemask & (1 << (i+1)*2);
+ int argtype = extract32(typemask, (i + 1) * 3, 3);
+ bool is_64bit = (argtype & ~1) == dh_typecode_i64;
+
if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
/* some targets want aligned 64 bit args */
@@ -2109,7 +2116,9 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
&& !defined(CONFIG_TCG_INTERPRETER)
/* Free all of the parts we allocated above. */
for (i = real_args = 0; i < orig_nargs; ++i) {
- int is_64bit = orig_sizemask & (1 << (i+1)*2);
+ int argtype = extract32(orig_typemask, (i + 1) * 3, 3);
+ bool is_64bit = (argtype & ~1) == dh_typecode_i64;
+
if (is_64bit) {
tcg_temp_free_internal(args[real_args++]);
tcg_temp_free_internal(args[real_args++]);
@@ -2117,7 +2126,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
real_args++;
}
}
- if (orig_sizemask & 1) {
+ if ((orig_typemask & 6) == dh_typecode_i64) {
/* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
Note that describing these as TCGv_i64 eliminates an unnecessary
zero-extension that tcg_gen_concat_i32_i64 would create. */
@@ -2127,8 +2136,10 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
}
#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
for (i = 0; i < nargs; ++i) {
- int is_64bit = sizemask & (1 << (i+1)*2);
- if (!is_64bit) {
+ int argtype = extract32(typemask, (i + 1) * 3, 3);
+ bool is_32bit = (argtype & ~1) == dh_typecode_i32;
+
+ if (is_32bit) {
tcg_temp_free_internal(args[i]);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 02/27] tcg: Add tcg_call_flags
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
2021-06-01 15:00 ` [PATCH v7 01/27] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 03/27] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
` (26 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
We're going to change how to look up the call flags from a TCGop,
so extract it as a helper.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/internal.h | 33 +++++++++++++++++++++++++++++++++
tcg/optimize.c | 3 ++-
tcg/tcg.c | 15 +++++++--------
3 files changed, 42 insertions(+), 9 deletions(-)
create mode 100644 tcg/internal.h
diff --git a/tcg/internal.h b/tcg/internal.h
new file mode 100644
index 0000000000..35a8a0d9fa
--- /dev/null
+++ b/tcg/internal.h
@@ -0,0 +1,33 @@
+/*
+ * Internal declarations for Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TCG_INTERNAL_H
+#define TCG_INTERNAL_H 1
+
+static inline unsigned tcg_call_flags(TCGOp *op)
+{
+ return op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
+}
+
+#endif /* TCG_INTERNAL_H */
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 37c902283e..081b62798e 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "tcg/tcg-op.h"
+#include "internal.h"
#define CASE_OP_32_64(x) \
glue(glue(case INDEX_op_, x), _i32): \
@@ -1481,7 +1482,7 @@ void tcg_optimize(TCGContext *s)
break;
case INDEX_op_call:
- if (!(op->args[nb_oargs + nb_iargs + 1]
+ if (!(tcg_call_flags(op)
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
for (i = 0; i < nb_globals; i++) {
if (test_bit(i, temps_used.l)) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5c9a89d22d..1fb4604e45 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -63,6 +63,7 @@
#include "elf.h"
#include "exec/log.h"
+#include "internal.h"
/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
@@ -2333,9 +2334,9 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
nb_cargs = def->nb_cargs;
/* function name, flags, out args */
- col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
+ col += qemu_log(" %s %s,$0x%x,$%d", def->name,
tcg_find_helper(s, op->args[nb_oargs + nb_iargs]),
- op->args[nb_oargs + nb_iargs + 1], nb_oargs);
+ tcg_call_flags(op), nb_oargs);
for (i = 0; i < nb_oargs; i++) {
col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf),
op->args[i]));
@@ -2709,7 +2710,6 @@ static void reachable_code_pass(TCGContext *s)
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
bool remove = dead;
TCGLabel *label;
- int call_flags;
switch (op->opc) {
case INDEX_op_set_label:
@@ -2754,8 +2754,7 @@ static void reachable_code_pass(TCGContext *s)
case INDEX_op_call:
/* Notice noreturn helper calls, raising exceptions. */
- call_flags = op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
- if (call_flags & TCG_CALL_NO_RETURN) {
+ if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) {
dead = true;
}
break;
@@ -2956,7 +2955,7 @@ static void liveness_pass_1(TCGContext *s)
nb_oargs = TCGOP_CALLO(op);
nb_iargs = TCGOP_CALLI(op);
- call_flags = op->args[nb_oargs + nb_iargs + 1];
+ call_flags = tcg_call_flags(op);
/* pure functions can be removed if their result is unused */
if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
@@ -3271,7 +3270,7 @@ static bool liveness_pass_2(TCGContext *s)
if (opc == INDEX_op_call) {
nb_oargs = TCGOP_CALLO(op);
nb_iargs = TCGOP_CALLI(op);
- call_flags = op->args[nb_oargs + nb_iargs + 1];
+ call_flags = tcg_call_flags(op);
} else {
nb_iargs = def->nb_iargs;
nb_oargs = def->nb_oargs;
@@ -4353,7 +4352,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
TCGRegSet allocated_regs;
func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs];
- flags = op->args[nb_oargs + nb_iargs + 1];
+ flags = tcg_call_flags(op);
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
if (nb_regs > nb_iargs) {
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 03/27] accel/tcg/plugin-gen: Drop inline markers
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
2021-06-01 15:00 ` [PATCH v7 01/27] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
2021-06-01 15:00 ` [PATCH v7 02/27] tcg: Add tcg_call_flags Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
` (25 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Let the compiler decide on inlining.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/plugin-gen.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 7627225aef..48bd2f36f0 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -160,9 +160,8 @@ static void gen_empty_mem_helper(void)
tcg_temp_free_ptr(ptr);
}
-static inline
-void gen_plugin_cb_start(enum plugin_gen_from from,
- enum plugin_gen_cb type, unsigned wr)
+static void gen_plugin_cb_start(enum plugin_gen_from from,
+ enum plugin_gen_cb type, unsigned wr)
{
TCGOp *op;
@@ -179,7 +178,7 @@ static void gen_wrapped(enum plugin_gen_from from,
tcg_gen_plugin_cb_end();
}
-static inline void plugin_gen_empty_callback(enum plugin_gen_from from)
+static void plugin_gen_empty_callback(enum plugin_gen_from from)
{
switch (from) {
case PLUGIN_GEN_AFTER_INSN:
@@ -513,9 +512,8 @@ static bool op_rw(const TCGOp *op, const struct qemu_plugin_dyn_cb *cb)
return !!(cb->rw & (w + 1));
}
-static inline
-void inject_cb_type(const GArray *cbs, TCGOp *begin_op, inject_fn inject,
- op_ok_fn ok)
+static void inject_cb_type(const GArray *cbs, TCGOp *begin_op,
+ inject_fn inject, op_ok_fn ok)
{
TCGOp *end_op;
TCGOp *op;
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (2 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 03/27] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-02 9:22 ` Alex Bennée
2021-06-01 15:00 ` [PATCH v7 05/27] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
` (24 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée, Philippe Mathieu-Daudé
As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is
currently unused -- plugins can neither read nor write
guest registers.
Cc: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/plugin-helpers.h | 1 -
include/qemu/plugin.h | 1 -
accel/tcg/plugin-gen.c | 8 ++++----
plugins/core.c | 30 ++++++------------------------
4 files changed, 10 insertions(+), 30 deletions(-)
diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h
index 1916ee7920..853bd21677 100644
--- a/accel/tcg/plugin-helpers.h
+++ b/accel/tcg/plugin-helpers.h
@@ -1,5 +1,4 @@
#ifdef CONFIG_PLUGIN
-/* Note: no TCG flags because those are overwritten later */
DEF_HELPER_2(plugin_vcpu_udata_cb, void, i32, ptr)
DEF_HELPER_4(plugin_vcpu_mem_cb, void, i32, i32, i64, ptr)
#endif
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
index c5a79a89f0..0fefbc6084 100644
--- a/include/qemu/plugin.h
+++ b/include/qemu/plugin.h
@@ -79,7 +79,6 @@ enum plugin_dyn_cb_subtype {
struct qemu_plugin_dyn_cb {
union qemu_plugin_cb_sig f;
void *userp;
- unsigned tcg_flags;
enum plugin_dyn_cb_subtype type;
/* @rw applies to mem callbacks only (both regular and inline) */
enum qemu_plugin_mem_rw rw;
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 48bd2f36f0..88e25c6df9 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -384,7 +384,7 @@ static TCGOp *copy_st_ptr(TCGOp **begin_op, TCGOp *op)
}
static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func,
- void *func, unsigned tcg_flags, int *cb_idx)
+ void *func, int *cb_idx)
{
/* copy all ops until the call */
do {
@@ -411,7 +411,7 @@ static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func,
tcg_debug_assert(i < MAX_OPC_PARAM_ARGS);
}
op->args[*cb_idx] = (uintptr_t)func;
- op->args[*cb_idx + 1] = tcg_flags;
+ op->args[*cb_idx + 1] = (*begin_op)->args[*cb_idx + 1];
return op;
}
@@ -438,7 +438,7 @@ static TCGOp *append_udata_cb(const struct qemu_plugin_dyn_cb *cb,
/* call */
op = copy_call(&begin_op, op, HELPER(plugin_vcpu_udata_cb),
- cb->f.vcpu_udata, cb->tcg_flags, cb_idx);
+ cb->f.vcpu_udata, cb_idx);
return op;
}
@@ -489,7 +489,7 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb,
if (type == PLUGIN_GEN_CB_MEM) {
/* call */
op = copy_call(&begin_op, op, HELPER(plugin_vcpu_mem_cb),
- cb->f.vcpu_udata, cb->tcg_flags, cb_idx);
+ cb->f.vcpu_udata, cb_idx);
}
return op;
diff --git a/plugins/core.c b/plugins/core.c
index 55d188af51..e1bcdb570d 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -295,33 +295,15 @@ void plugin_register_inline_op(GArray **arr,
dyn_cb->inline_insn.imm = imm;
}
-static inline uint32_t cb_to_tcg_flags(enum qemu_plugin_cb_flags flags)
-{
- uint32_t ret;
-
- switch (flags) {
- case QEMU_PLUGIN_CB_RW_REGS:
- ret = 0;
- break;
- case QEMU_PLUGIN_CB_R_REGS:
- ret = TCG_CALL_NO_WG;
- break;
- case QEMU_PLUGIN_CB_NO_REGS:
- default:
- ret = TCG_CALL_NO_RWG;
- }
- return ret;
-}
-
-inline void
-plugin_register_dyn_cb__udata(GArray **arr,
- qemu_plugin_vcpu_udata_cb_t cb,
- enum qemu_plugin_cb_flags flags, void *udata)
+void plugin_register_dyn_cb__udata(GArray **arr,
+ qemu_plugin_vcpu_udata_cb_t cb,
+ enum qemu_plugin_cb_flags flags,
+ void *udata)
{
struct qemu_plugin_dyn_cb *dyn_cb = plugin_get_dyn_cb(arr);
dyn_cb->userp = udata;
- dyn_cb->tcg_flags = cb_to_tcg_flags(flags);
+ /* Note flags are discarded as unused. */
dyn_cb->f.vcpu_udata = cb;
dyn_cb->type = PLUGIN_CB_REGULAR;
}
@@ -336,7 +318,7 @@ void plugin_register_vcpu_mem_cb(GArray **arr,
dyn_cb = plugin_get_dyn_cb(arr);
dyn_cb->userp = udata;
- dyn_cb->tcg_flags = cb_to_tcg_flags(flags);
+ /* Note flags are discarded as unused. */
dyn_cb->type = PLUGIN_CB_REGULAR;
dyn_cb->rw = rw;
dyn_cb->f.generic = cb;
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb
2021-06-01 15:00 ` [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
@ 2021-06-02 9:22 ` Alex Bennée
2021-06-02 16:02 ` Richard Henderson
0 siblings, 1 reply; 47+ messages in thread
From: Alex Bennée @ 2021-06-02 9:22 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Philippe Mathieu-Daudé
Richard Henderson <richard.henderson@linaro.org> writes:
> As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is
> currently unused -- plugins can neither read nor write
> guest registers.
No objection to this - although we hopefully will introduce the ability
to read registers at some point. I saw no indication that the ability to
mark helpers for that is going away, just the mechanism is changing?
>
> Cc: Alex Bennée <alex.bennee@linaro.org>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/plugin-helpers.h | 1 -
> include/qemu/plugin.h | 1 -
> accel/tcg/plugin-gen.c | 8 ++++----
> plugins/core.c | 30 ++++++------------------------
> 4 files changed, 10 insertions(+), 30 deletions(-)
>
> diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h
> index 1916ee7920..853bd21677 100644
> --- a/accel/tcg/plugin-helpers.h
> +++ b/accel/tcg/plugin-helpers.h
> @@ -1,5 +1,4 @@
> #ifdef CONFIG_PLUGIN
> -/* Note: no TCG flags because those are overwritten later */
> DEF_HELPER_2(plugin_vcpu_udata_cb, void, i32, ptr)
> DEF_HELPER_4(plugin_vcpu_mem_cb, void, i32, i32, i64, ptr)
> #endif
> diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
> index c5a79a89f0..0fefbc6084 100644
> --- a/include/qemu/plugin.h
> +++ b/include/qemu/plugin.h
> @@ -79,7 +79,6 @@ enum plugin_dyn_cb_subtype {
> struct qemu_plugin_dyn_cb {
> union qemu_plugin_cb_sig f;
> void *userp;
> - unsigned tcg_flags;
> enum plugin_dyn_cb_subtype type;
> /* @rw applies to mem callbacks only (both regular and inline) */
> enum qemu_plugin_mem_rw rw;
> diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
> index 48bd2f36f0..88e25c6df9 100644
> --- a/accel/tcg/plugin-gen.c
> +++ b/accel/tcg/plugin-gen.c
> @@ -384,7 +384,7 @@ static TCGOp *copy_st_ptr(TCGOp **begin_op, TCGOp *op)
> }
>
> static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func,
> - void *func, unsigned tcg_flags, int *cb_idx)
> + void *func, int *cb_idx)
> {
> /* copy all ops until the call */
> do {
> @@ -411,7 +411,7 @@ static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func,
> tcg_debug_assert(i < MAX_OPC_PARAM_ARGS);
> }
> op->args[*cb_idx] = (uintptr_t)func;
> - op->args[*cb_idx + 1] = tcg_flags;
> + op->args[*cb_idx + 1] = (*begin_op)->args[*cb_idx + 1];
This confuses me. We are dropping tcg_flags because we aren't using them
but why are we copying the next args from begin_op? Should we have been
doing that before?
>
> return op;
> }
> @@ -438,7 +438,7 @@ static TCGOp *append_udata_cb(const struct qemu_plugin_dyn_cb *cb,
>
> /* call */
> op = copy_call(&begin_op, op, HELPER(plugin_vcpu_udata_cb),
> - cb->f.vcpu_udata, cb->tcg_flags, cb_idx);
> + cb->f.vcpu_udata, cb_idx);
>
> return op;
> }
> @@ -489,7 +489,7 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb,
> if (type == PLUGIN_GEN_CB_MEM) {
> /* call */
> op = copy_call(&begin_op, op, HELPER(plugin_vcpu_mem_cb),
> - cb->f.vcpu_udata, cb->tcg_flags, cb_idx);
> + cb->f.vcpu_udata, cb_idx);
> }
>
> return op;
> diff --git a/plugins/core.c b/plugins/core.c
> index 55d188af51..e1bcdb570d 100644
> --- a/plugins/core.c
> +++ b/plugins/core.c
> @@ -295,33 +295,15 @@ void plugin_register_inline_op(GArray **arr,
> dyn_cb->inline_insn.imm = imm;
> }
>
> -static inline uint32_t cb_to_tcg_flags(enum qemu_plugin_cb_flags flags)
> -{
> - uint32_t ret;
> -
> - switch (flags) {
> - case QEMU_PLUGIN_CB_RW_REGS:
> - ret = 0;
> - break;
> - case QEMU_PLUGIN_CB_R_REGS:
> - ret = TCG_CALL_NO_WG;
> - break;
> - case QEMU_PLUGIN_CB_NO_REGS:
> - default:
> - ret = TCG_CALL_NO_RWG;
> - }
> - return ret;
> -}
> -
> -inline void
> -plugin_register_dyn_cb__udata(GArray **arr,
> - qemu_plugin_vcpu_udata_cb_t cb,
> - enum qemu_plugin_cb_flags flags, void *udata)
> +void plugin_register_dyn_cb__udata(GArray **arr,
> + qemu_plugin_vcpu_udata_cb_t cb,
> + enum qemu_plugin_cb_flags flags,
> + void *udata)
> {
> struct qemu_plugin_dyn_cb *dyn_cb = plugin_get_dyn_cb(arr);
>
> dyn_cb->userp = udata;
> - dyn_cb->tcg_flags = cb_to_tcg_flags(flags);
> + /* Note flags are discarded as unused. */
"currently unused" would be a slightly more hopeful statement ;-)
> dyn_cb->f.vcpu_udata = cb;
> dyn_cb->type = PLUGIN_CB_REGULAR;
> }
> @@ -336,7 +318,7 @@ void plugin_register_vcpu_mem_cb(GArray **arr,
>
> dyn_cb = plugin_get_dyn_cb(arr);
> dyn_cb->userp = udata;
> - dyn_cb->tcg_flags = cb_to_tcg_flags(flags);
> + /* Note flags are discarded as unused. */
> dyn_cb->type = PLUGIN_CB_REGULAR;
> dyn_cb->rw = rw;
> dyn_cb->f.generic = cb;
--
Alex Bennée
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb
2021-06-02 9:22 ` Alex Bennée
@ 2021-06-02 16:02 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-02 16:02 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, Philippe Mathieu-Daudé
On 6/2/21 2:22 AM, Alex Bennée wrote:
>
> Richard Henderson <richard.henderson@linaro.org> writes:
>
>> As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is
>> currently unused -- plugins can neither read nor write
>> guest registers.
>
> No objection to this - although we hopefully will introduce the ability
> to read registers at some point. I saw no indication that the ability to
> mark helpers for that is going away, just the mechanism is changing?
The mechanism is going away. I'll figure out how to replace it when there's
some call to do so.
>> @@ -411,7 +411,7 @@ static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func,
>> tcg_debug_assert(i < MAX_OPC_PARAM_ARGS);
>> }
>> op->args[*cb_idx] = (uintptr_t)func;
>> - op->args[*cb_idx + 1] = tcg_flags;
>> + op->args[*cb_idx + 1] = (*begin_op)->args[*cb_idx + 1];
>
> This confuses me. We are dropping tcg_flags because we aren't using them
> but why are we copying the next args from begin_op? Should we have been
> doing that before?
You were overwriting the field before, now we're copying it.
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 05/27] accel/tcg: Add tcg call flags to plugins helpers
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (3 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 04/27] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 06/27] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
` (23 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
As noted by qemu-plugins.h, plugins can neither read nor write
guest registers.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/plugin-helpers.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h
index 853bd21677..9829abe4a9 100644
--- a/accel/tcg/plugin-helpers.h
+++ b/accel/tcg/plugin-helpers.h
@@ -1,4 +1,4 @@
#ifdef CONFIG_PLUGIN
-DEF_HELPER_2(plugin_vcpu_udata_cb, void, i32, ptr)
-DEF_HELPER_4(plugin_vcpu_mem_cb, void, i32, i32, i64, ptr)
+DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb, TCG_CALL_NO_RWG, void, i32, ptr)
+DEF_HELPER_FLAGS_4(plugin_vcpu_mem_cb, TCG_CALL_NO_RWG, void, i32, i32, i64, ptr)
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 06/27] tcg: Store the TCGHelperInfo in the TCGOp for call
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (4 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 05/27] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 07/27] tcg: Add tcg_call_func Richard Henderson
` (22 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This will give us both flags and typemask for use later.
We also fix a dumping bug, wherein calls generated for plugins
fail tcg_find_helper and print (null) instead of either a name
or the raw function pointer.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/internal.h | 14 +++++++++++++-
tcg/tcg.c | 49 +++++++++++++++++++++----------------------------
2 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/tcg/internal.h b/tcg/internal.h
index 35a8a0d9fa..c2d5e9c42f 100644
--- a/tcg/internal.h
+++ b/tcg/internal.h
@@ -25,9 +25,21 @@
#ifndef TCG_INTERNAL_H
#define TCG_INTERNAL_H 1
+typedef struct TCGHelperInfo {
+ void *func;
+ const char *name;
+ unsigned flags;
+ unsigned typemask;
+} TCGHelperInfo;
+
+static inline const TCGHelperInfo *tcg_call_info(TCGOp *op)
+{
+ return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
+}
+
static inline unsigned tcg_call_flags(TCGOp *op)
{
- return op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
+ return tcg_call_info(op)->flags;
}
#endif /* TCG_INTERNAL_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1fb4604e45..6e5b70215a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1084,13 +1084,6 @@ void tcg_pool_reset(TCGContext *s)
s->pool_current = NULL;
}
-typedef struct TCGHelperInfo {
- void *func;
- const char *name;
- unsigned flags;
- unsigned typemask;
-} TCGHelperInfo;
-
#include "exec/helper-proto.h"
static const TCGHelperInfo all_helpers[] = {
@@ -1963,12 +1956,11 @@ bool tcg_op_supported(TCGOpcode op)
void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
{
int i, real_args, nb_rets, pi;
- unsigned typemask, flags;
- TCGHelperInfo *info;
+ unsigned typemask;
+ const TCGHelperInfo *info;
TCGOp *op;
info = g_hash_table_lookup(helper_table, (gpointer)func);
- flags = info->flags;
typemask = info->typemask;
#ifdef CONFIG_PLUGIN
@@ -2106,7 +2098,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
real_args++;
}
op->args[pi++] = (uintptr_t)func;
- op->args[pi++] = flags;
+ op->args[pi++] = (uintptr_t)info;
TCGOP_CALLI(op) = real_args;
/* Make sure the fields didn't overflow. */
@@ -2225,19 +2217,6 @@ static char *tcg_get_arg_str(TCGContext *s, char *buf,
return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg));
}
-/* Find helper name. */
-static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
-{
- const char *ret = NULL;
- if (helper_table) {
- TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val);
- if (info) {
- ret = info->name;
- }
- }
- return ret;
-}
-
static const char * const cond_name[] =
{
[TCG_COND_NEVER] = "never",
@@ -2328,15 +2307,29 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
col += qemu_log(" " TARGET_FMT_lx, a);
}
} else if (c == INDEX_op_call) {
+ const TCGHelperInfo *info = tcg_call_info(op);
+ void *func;
+
/* variable number of arguments */
nb_oargs = TCGOP_CALLO(op);
nb_iargs = TCGOP_CALLI(op);
nb_cargs = def->nb_cargs;
- /* function name, flags, out args */
- col += qemu_log(" %s %s,$0x%x,$%d", def->name,
- tcg_find_helper(s, op->args[nb_oargs + nb_iargs]),
- tcg_call_flags(op), nb_oargs);
+ col += qemu_log(" %s ", def->name);
+
+ /*
+ * Print the function name from TCGHelperInfo, if available.
+ * Note that plugins have a template function for the info,
+ * but the actual function pointer comes from the plugin.
+ */
+ func = (void *)(uintptr_t)op->args[nb_oargs + nb_iargs];
+ if (func == info->func) {
+ col += qemu_log("%s", info->name);
+ } else {
+ col += qemu_log("plugin(%p)", func);
+ }
+
+ col += qemu_log("$0x%x,$%d", info->flags, nb_oargs);
for (i = 0; i < nb_oargs; i++) {
col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf),
op->args[i]));
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 07/27] tcg: Add tcg_call_func
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (5 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 06/27] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 08/27] tcg: Build ffi data structures for helpers Richard Henderson
` (21 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/internal.h | 5 +++++
tcg/tcg.c | 5 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/internal.h b/tcg/internal.h
index c2d5e9c42f..cd128e2a83 100644
--- a/tcg/internal.h
+++ b/tcg/internal.h
@@ -32,6 +32,11 @@ typedef struct TCGHelperInfo {
unsigned typemask;
} TCGHelperInfo;
+static inline void *tcg_call_func(TCGOp *op)
+{
+ return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op)];
+}
+
static inline const TCGHelperInfo *tcg_call_info(TCGOp *op)
{
return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 6e5b70215a..205b2b7106 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2308,7 +2308,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
}
} else if (c == INDEX_op_call) {
const TCGHelperInfo *info = tcg_call_info(op);
- void *func;
+ void *func = tcg_call_func(op);
/* variable number of arguments */
nb_oargs = TCGOP_CALLO(op);
@@ -2322,7 +2322,6 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
* Note that plugins have a template function for the info,
* but the actual function pointer comes from the plugin.
*/
- func = (void *)(uintptr_t)op->args[nb_oargs + nb_iargs];
if (func == info->func) {
col += qemu_log("%s", info->name);
} else {
@@ -4344,7 +4343,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
int allocate_args;
TCGRegSet allocated_regs;
- func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs];
+ func_addr = tcg_call_func(op);
flags = tcg_call_flags(op);
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 08/27] tcg: Build ffi data structures for helpers
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (6 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 07/27] tcg: Add tcg_call_func Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
` (20 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Add libffi as a build requirement for TCI.
Add libffi to the dockerfiles to satisfy that requirement.
Construct an ffi_cif structure for each unique typemask.
Record the result in a separate hash table for later lookup;
this allows helper_table to stay const.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 9 ++-
tcg/tcg.c | 58 +++++++++++++++++++
tests/docker/dockerfiles/alpine.docker | 1 +
tests/docker/dockerfiles/centos7.docker | 1 +
tests/docker/dockerfiles/centos8.docker | 1 +
tests/docker/dockerfiles/debian10.docker | 1 +
.../dockerfiles/fedora-i386-cross.docker | 1 +
.../dockerfiles/fedora-win32-cross.docker | 1 +
.../dockerfiles/fedora-win64-cross.docker | 1 +
tests/docker/dockerfiles/fedora.docker | 1 +
tests/docker/dockerfiles/ubuntu.docker | 1 +
tests/docker/dockerfiles/ubuntu1804.docker | 1 +
tests/docker/dockerfiles/ubuntu2004.docker | 1 +
13 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index a45f1a844f..c2f36171ea 100644
--- a/meson.build
+++ b/meson.build
@@ -1958,7 +1958,14 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files(
'tcg/tcg-op.c',
'tcg/tcg.c',
))
-specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'))
+
+if get_option('tcg_interpreter')
+ libffi = dependency('libffi', version: '>=3.0',
+ static: enable_static, method: 'pkg-config',
+ required: true)
+ specific_ss.add(libffi)
+ specific_ss.add(files('tcg/tci.c'))
+endif
# Work around a gcc bug/misfeature wherein constant propagation looks
# through an alias:
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 205b2b7106..3df29417c3 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -65,6 +65,10 @@
#include "exec/log.h"
#include "internal.h"
+#ifdef CONFIG_TCG_INTERPRETER
+#include <ffi.h>
+#endif
+
/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
static void tcg_target_init(TCGContext *s);
@@ -1091,6 +1095,19 @@ static const TCGHelperInfo all_helpers[] = {
};
static GHashTable *helper_table;
+#ifdef CONFIG_TCG_INTERPRETER
+static GHashTable *ffi_table;
+
+static ffi_type * const typecode_to_ffi[8] = {
+ [dh_typecode_void] = &ffi_type_void,
+ [dh_typecode_i32] = &ffi_type_uint32,
+ [dh_typecode_s32] = &ffi_type_sint32,
+ [dh_typecode_i64] = &ffi_type_uint64,
+ [dh_typecode_s64] = &ffi_type_sint64,
+ [dh_typecode_ptr] = &ffi_type_pointer,
+};
+#endif
+
static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)];
static void process_op_defs(TCGContext *s);
static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
@@ -1133,6 +1150,47 @@ void tcg_context_init(TCGContext *s)
(gpointer)&all_helpers[i]);
}
+#ifdef CONFIG_TCG_INTERPRETER
+ /* g_direct_hash/equal for direct comparisons on uint32_t. */
+ ffi_table = g_hash_table_new(NULL, NULL);
+ for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
+ struct {
+ ffi_cif cif;
+ ffi_type *args[];
+ } *ca;
+ uint32_t typemask = all_helpers[i].typemask;
+ gpointer hash = (gpointer)(uintptr_t)typemask;
+ ffi_status status;
+ int nargs;
+
+ if (g_hash_table_lookup(ffi_table, hash)) {
+ continue;
+ }
+
+ /* Ignoring the return type, find the last non-zero field. */
+ nargs = 32 - clz32(typemask >> 3);
+ nargs = DIV_ROUND_UP(nargs, 3);
+
+ ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *));
+ ca->cif.rtype = typecode_to_ffi[typemask & 7];
+ ca->cif.nargs = nargs;
+
+ if (nargs != 0) {
+ ca->cif.arg_types = ca->args;
+ for (i = 0; i < nargs; ++i) {
+ int typecode = extract32(typemask, (i + 1) * 3, 3);
+ ca->args[i] = typecode_to_ffi[typecode];
+ }
+ }
+
+ status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs,
+ ca->cif.rtype, ca->cif.arg_types);
+ assert(status == FFI_OK);
+
+ g_hash_table_insert(ffi_table, hash, (gpointer)&ca->cif);
+ }
+#endif
+
tcg_target_init(s);
process_op_defs(s);
diff --git a/tests/docker/dockerfiles/alpine.docker b/tests/docker/dockerfiles/alpine.docker
index 7eeecacc46..7e6997e301 100644
--- a/tests/docker/dockerfiles/alpine.docker
+++ b/tests/docker/dockerfiles/alpine.docker
@@ -22,6 +22,7 @@ ENV PACKAGES \
libaio-dev \
libbpf-dev \
libcap-ng-dev \
+ libffi-dev \
libjpeg-turbo-dev \
libnfs-dev \
libpng-dev \
diff --git a/tests/docker/dockerfiles/centos7.docker b/tests/docker/dockerfiles/centos7.docker
index 75fdb53c7c..fff7c5a424 100644
--- a/tests/docker/dockerfiles/centos7.docker
+++ b/tests/docker/dockerfiles/centos7.docker
@@ -20,6 +20,7 @@ ENV PACKAGES \
libaio-devel \
libepoxy-devel \
libfdt-devel \
+ libffi-devel \
libgcrypt-devel \
librdmacm-devel \
libzstd-devel \
diff --git a/tests/docker/dockerfiles/centos8.docker b/tests/docker/dockerfiles/centos8.docker
index efc1349cc8..03e0440e03 100644
--- a/tests/docker/dockerfiles/centos8.docker
+++ b/tests/docker/dockerfiles/centos8.docker
@@ -17,6 +17,7 @@ ENV PACKAGES \
libbpf-devel \
libepoxy-devel \
libfdt-devel \
+ libffi-devel \
libgcrypt-devel \
lzo-devel \
make \
diff --git a/tests/docker/dockerfiles/debian10.docker b/tests/docker/dockerfiles/debian10.docker
index 63cf835ec5..4ffe47671e 100644
--- a/tests/docker/dockerfiles/debian10.docker
+++ b/tests/docker/dockerfiles/debian10.docker
@@ -26,6 +26,7 @@ RUN apt update && \
gdb-multiarch \
gettext \
git \
+ libffi-dev \
libncurses5-dev \
ninja-build \
pkg-config \
diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker
index 66cdb06c19..8004fd8ee5 100644
--- a/tests/docker/dockerfiles/fedora-i386-cross.docker
+++ b/tests/docker/dockerfiles/fedora-i386-cross.docker
@@ -6,6 +6,7 @@ ENV PACKAGES \
findutils \
gcc \
git \
+ libffi-devel.i686 \
libtasn1-devel.i686 \
libzstd-devel.i686 \
make \
diff --git a/tests/docker/dockerfiles/fedora-win32-cross.docker b/tests/docker/dockerfiles/fedora-win32-cross.docker
index 3733df63e9..a638afb525 100644
--- a/tests/docker/dockerfiles/fedora-win32-cross.docker
+++ b/tests/docker/dockerfiles/fedora-win32-cross.docker
@@ -19,6 +19,7 @@ ENV PACKAGES \
mingw32-gmp \
mingw32-gnutls \
mingw32-gtk3 \
+ mingw32-libffi \
mingw32-libjpeg-turbo \
mingw32-libpng \
mingw32-libtasn1 \
diff --git a/tests/docker/dockerfiles/fedora-win64-cross.docker b/tests/docker/dockerfiles/fedora-win64-cross.docker
index 2564ce4979..f53007ac86 100644
--- a/tests/docker/dockerfiles/fedora-win64-cross.docker
+++ b/tests/docker/dockerfiles/fedora-win64-cross.docker
@@ -18,6 +18,7 @@ ENV PACKAGES \
mingw64-glib2 \
mingw64-gmp \
mingw64-gtk3 \
+ mingw64-libffi \
mingw64-libjpeg-turbo \
mingw64-libpng \
mingw64-libtasn1 \
diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker
index 0979c0e1f4..00cac5d61c 100644
--- a/tests/docker/dockerfiles/fedora.docker
+++ b/tests/docker/dockerfiles/fedora.docker
@@ -33,6 +33,7 @@ ENV PACKAGES \
libepoxy-devel \
libfdt-devel \
libbpf-devel \
+ libffi-devel \
libiscsi-devel \
libjpeg-devel \
libpmem-devel \
diff --git a/tests/docker/dockerfiles/ubuntu.docker b/tests/docker/dockerfiles/ubuntu.docker
index 98a527361c..24d1647a65 100644
--- a/tests/docker/dockerfiles/ubuntu.docker
+++ b/tests/docker/dockerfiles/ubuntu.docker
@@ -28,6 +28,7 @@ ENV PACKAGES \
libdrm-dev \
libepoxy-dev \
libfdt-dev \
+ libffi-dev \
libgbm-dev \
libgnutls28-dev \
libgtk-3-dev \
diff --git a/tests/docker/dockerfiles/ubuntu1804.docker b/tests/docker/dockerfiles/ubuntu1804.docker
index c0d3642507..2f1ec7c42b 100644
--- a/tests/docker/dockerfiles/ubuntu1804.docker
+++ b/tests/docker/dockerfiles/ubuntu1804.docker
@@ -16,6 +16,7 @@ ENV PACKAGES \
libdrm-dev \
libepoxy-dev \
libfdt-dev \
+ libffi-dev \
libgbm-dev \
libgtk-3-dev \
libibverbs-dev \
diff --git a/tests/docker/dockerfiles/ubuntu2004.docker b/tests/docker/dockerfiles/ubuntu2004.docker
index f1e0ebad49..fe993fe2a3 100644
--- a/tests/docker/dockerfiles/ubuntu2004.docker
+++ b/tests/docker/dockerfiles/ubuntu2004.docker
@@ -19,6 +19,7 @@ ENV PACKAGES flex bison \
libdrm-dev \
libepoxy-dev \
libfdt-dev \
+ libffi-dev \
libgbm-dev \
libgtk-3-dev \
libibverbs-dev \
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (7 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 08/27] tcg: Build ffi data structures for helpers Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-02 17:59 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 10/27] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
` (19 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
The current setting is much too pessimistic. Indicating only
the one or two registers that are actually assigned after a
call should avoid unnecessary movement between the register
array and the stack array.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index ee6cdfec71..fb7c927fdf 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -812,8 +812,14 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
/* Registers available for 64 bit operations. */
tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
- /* TODO: Which registers should be set here? */
- tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;
+ /*
+ * The interpreter "registers" are in the local stack frame and
+ * cannot be clobbered by the called helper functions. However,
+ * the interpreter assumes a 64-bit return value and assigns to
+ * the return value registers.
+ */
+ tcg_target_call_clobber_regs =
+ MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS);
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs
2021-06-01 15:00 ` [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
@ 2021-06-02 17:59 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-02 17:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> The current setting is much too pessimistic. Indicating only
> the one or two registers that are actually assigned after a
> call should avoid unnecessary movement between the register
> array and the stack array.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci/tcg-target.c.inc | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 10/27] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (8 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 09/27] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 11/27] tcg/tci: Use ffi for calls Richard Henderson
` (18 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
As the only call-clobbered regs for TCI, these should
receive the least priority.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index fb7c927fdf..288e945465 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
}
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R0,
- TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
TCG_REG_R4,
@@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+ TCG_REG_R1,
+ TCG_REG_R0,
};
#if MAX_OPC_PARAM_IARGS != 6
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 11/27] tcg/tci: Use ffi for calls
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (9 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 10/27] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-02 10:31 ` Alex Bennée
2021-06-01 15:00 ` [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary Richard Henderson
` (17 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This requires adjusting where arguments are stored.
Place them on the stack at left-aligned positions.
Adjust the stack frame to be at entirely positive offsets.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 1 +
tcg/tci/tcg-target.h | 2 +-
tcg/tcg.c | 64 ++++++++++++------
tcg/tci.c | 136 ++++++++++++++++++++++-----------------
tcg/tci/tcg-target.c.inc | 50 +++++++-------
5 files changed, 149 insertions(+), 104 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 74cb345308..029890712c 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -52,6 +52,7 @@
#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
#define CPU_TEMP_BUF_NLONGS 128
+#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long))
/* Default target word size to pointer size. */
#ifndef TCG_TARGET_REG_BITS
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 52af6d8bc5..4df10e2e83 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -161,7 +161,7 @@ typedef enum {
/* Used for function call generation. */
#define TCG_TARGET_CALL_STACK_OFFSET 0
-#define TCG_TARGET_STACK_ALIGN 16
+#define TCG_TARGET_STACK_ALIGN 8
#define HAVE_TCG_QEMU_TB_EXEC
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3df29417c3..c8e6dfb845 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -152,7 +152,12 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
intptr_t arg2);
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
TCGReg base, intptr_t ofs);
+#ifdef CONFIG_TCG_INTERPRETER
+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target,
+ ffi_cif *cif);
+#else
static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
+#endif
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct);
#ifdef TCG_TARGET_NEED_LDST_LABELS
@@ -2122,25 +2127,37 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = 0; i < nargs; i++) {
int argtype = extract32(typemask, (i + 1) * 3, 3);
bool is_64bit = (argtype & ~1) == dh_typecode_i64;
+ bool want_align = false;
+
+#if defined(CONFIG_TCG_INTERPRETER)
+ /*
+ * Align all arguments, so that they land in predictable places
+ * for passing off to ffi_call.
+ */
+ want_align = true;
+#elif defined(TCG_TARGET_CALL_ALIGN_ARGS)
+ /* Some targets want aligned 64 bit args */
+ want_align = is_64bit;
+#endif
+
+ if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) {
+ op->args[pi++] = TCG_CALL_DUMMY_ARG;
+ real_args++;
+ }
if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
-#ifdef TCG_TARGET_CALL_ALIGN_ARGS
- /* some targets want aligned 64 bit args */
- if (real_args & 1) {
- op->args[pi++] = TCG_CALL_DUMMY_ARG;
- real_args++;
- }
-#endif
- /* If stack grows up, then we will be placing successive
- arguments at lower addresses, which means we need to
- reverse the order compared to how we would normally
- treat either big or little-endian. For those arguments
- that will wind up in registers, this still works for
- HPPA (the only current STACK_GROWSUP target) since the
- argument registers are *also* allocated in decreasing
- order. If another such target is added, this logic may
- have to get more complicated to differentiate between
- stack arguments and register arguments. */
+ /*
+ * If stack grows up, then we will be placing successive
+ * arguments at lower addresses, which means we need to
+ * reverse the order compared to how we would normally
+ * treat either big or little-endian. For those arguments
+ * that will wind up in registers, this still works for
+ * HPPA (the only current STACK_GROWSUP target) since the
+ * argument registers are *also* allocated in decreasing
+ * order. If another such target is added, this logic may
+ * have to get more complicated to differentiate between
+ * stack arguments and register arguments.
+ */
#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
op->args[pi++] = temp_arg(args[i] + 1);
op->args[pi++] = temp_arg(args[i]);
@@ -4391,6 +4408,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
const int nb_oargs = TCGOP_CALLO(op);
const int nb_iargs = TCGOP_CALLI(op);
const TCGLifeData arg_life = op->life;
+ const TCGHelperInfo *info;
int flags, nb_regs, i;
TCGReg reg;
TCGArg arg;
@@ -4402,7 +4420,8 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
TCGRegSet allocated_regs;
func_addr = tcg_call_func(op);
- flags = tcg_call_flags(op);
+ info = tcg_call_info(op);
+ flags = info->flags;
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
if (nb_regs > nb_iargs) {
@@ -4494,7 +4513,16 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
save_globals(s, allocated_regs);
}
+#ifdef CONFIG_TCG_INTERPRETER
+ {
+ gpointer hash = (gpointer)(uintptr_t)info->typemask;
+ ffi_cif *cif = g_hash_table_lookup(ffi_table, hash);
+ assert(cif != NULL);
+ tcg_out_call(s, func_addr, cif);
+ }
+#else
tcg_out_call(s, func_addr);
+#endif
/* assign output registers and emit moves if needed */
for(i = 0; i < nb_oargs; i++) {
diff --git a/tcg/tci.c b/tcg/tci.c
index d68c5a4e55..3a6aeb1139 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -18,6 +18,13 @@
*/
#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
+#include "exec/cpu_ldst.h"
+#include "tcg/tcg-op.h"
+#include "qemu/compiler.h"
+#include <ffi.h>
+
/* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
* Without assertions, the interpreter runs much faster. */
@@ -27,36 +34,8 @@
# define tci_assert(cond) ((void)(cond))
#endif
-#include "qemu-common.h"
-#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
-#include "exec/cpu_ldst.h"
-#include "tcg/tcg-op.h"
-#include "qemu/compiler.h"
-
-#if MAX_OPC_PARAM_IARGS != 6
-# error Fix needed, number of supported input arguments changed!
-#endif
-#if TCG_TARGET_REG_BITS == 32
-typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong);
-#else
-typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong,
- tcg_target_ulong, tcg_target_ulong);
-#endif
-
__thread uintptr_t tci_tb_ptr;
-static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
-{
- tci_assert(index < TCG_TARGET_NB_REGS);
- return regs[index];
-}
-
static void
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
{
@@ -133,6 +112,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* I = immediate (tcg_target_ulong)
* l = label or pointer
* m = immediate (TCGMemOpIdx)
+ * n = immediate (call return length)
* r = register
* s = signed ldst offset
*/
@@ -153,6 +133,18 @@ static void tci_args_l(const uint8_t **tb_ptr, void **l0)
check_size(start, tb_ptr);
}
+static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0,
+ void **l1, void **l2)
+{
+ const uint8_t *start = *tb_ptr;
+
+ *n0 = tci_read_b(tb_ptr);
+ *l1 = (void *)tci_read_label(tb_ptr);
+ *l2 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
+}
+
static void tci_args_rr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1)
{
@@ -487,11 +479,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
{
const uint8_t *tb_ptr = v_tb_ptr;
tcg_target_ulong regs[TCG_TARGET_NB_REGS];
- long tcg_temps[CPU_TEMP_BUF_NLONGS];
- uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
+ uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE)
+ / sizeof(uint64_t)];
+ void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)];
regs[TCG_AREG0] = (tcg_target_ulong)env;
- regs[TCG_REG_CALL_STACK] = sp_value;
+ regs[TCG_REG_CALL_STACK] = (uintptr_t)stack;
+ /* Other call_slots entries initialized at first use (see below). */
+ call_slots[0] = NULL;
tci_assert(tb_ptr);
for (;;) {
@@ -509,40 +504,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
TCGMemOpIdx oi;
int32_t ofs;
- void *ptr;
+ void *ptr, *cif;
/* Skip opcode and size entry. */
tb_ptr += 2;
switch (opc) {
case INDEX_op_call:
- tci_args_l(&tb_ptr, &ptr);
+ /*
+ * Set up the ffi_avalue array once, delayed until now
+ * because many TB's do not make any calls. In tcg_gen_callN,
+ * we arranged for every real argument to be "left-aligned"
+ * in each 64-bit slot.
+ */
+ if (unlikely(call_slots[0] == NULL)) {
+ for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) {
+ call_slots[i] = &stack[i];
+ }
+ }
+
+ tci_args_nll(&tb_ptr, &len, &ptr, &cif);
+
+ /* Helper functions may need to access the "return address" */
tci_tb_ptr = (uintptr_t)tb_ptr;
-#if TCG_TARGET_REG_BITS == 32
- tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0),
- tci_read_reg(regs, TCG_REG_R1),
- tci_read_reg(regs, TCG_REG_R2),
- tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R4),
- tci_read_reg(regs, TCG_REG_R5),
- tci_read_reg(regs, TCG_REG_R6),
- tci_read_reg(regs, TCG_REG_R7),
- tci_read_reg(regs, TCG_REG_R8),
- tci_read_reg(regs, TCG_REG_R9),
- tci_read_reg(regs, TCG_REG_R10),
- tci_read_reg(regs, TCG_REG_R11));
- tci_write_reg(regs, TCG_REG_R0, tmp64);
- tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32);
-#else
- tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0),
- tci_read_reg(regs, TCG_REG_R1),
- tci_read_reg(regs, TCG_REG_R2),
- tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R4),
- tci_read_reg(regs, TCG_REG_R5));
- tci_write_reg(regs, TCG_REG_R0, tmp64);
-#endif
+
+ ffi_call(cif, ptr, stack, call_slots);
+
+ /* Any result winds up "left-aligned" in the stack[0] slot. */
+ switch (len) {
+ case 0: /* void */
+ break;
+ case 1: /* uint32_t */
+ /*
+ * Note that libffi has an odd special case in that it will
+ * always widen an integral result to ffi_arg.
+ */
+ if (sizeof(ffi_arg) == 4) {
+ regs[TCG_REG_R0] = *(uint32_t *)stack;
+ break;
+ }
+ /* fall through */
+ case 2: /* uint64_t */
+ if (TCG_TARGET_REG_BITS == 32) {
+ tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]);
+ } else {
+ regs[TCG_REG_R0] = stack[0];
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
break;
+
case INDEX_op_br:
tci_args_l(&tb_ptr, &ptr);
tb_ptr = ptr;
@@ -1119,7 +1132,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
TCGCond c;
TCGMemOpIdx oi;
uint8_t pos, len;
- void *ptr;
+ void *ptr, *cif;
const uint8_t *tb_ptr;
status = info->read_memory_func(addr, buf, 2, info);
@@ -1147,13 +1160,18 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
switch (op) {
case INDEX_op_br:
- case INDEX_op_call:
case INDEX_op_exit_tb:
case INDEX_op_goto_tb:
tci_args_l(&tb_ptr, &ptr);
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
+ case INDEX_op_call:
+ tci_args_nll(&tb_ptr, &len, &ptr, &cif);
+ info->fprintf_func(info->stream, "%-12s %d, %p, %p",
+ op_name, len, ptr, cif);
+ break;
+
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 288e945465..9ab7916300 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] = {
# error Fix needed, number of supported input arguments changed!
#endif
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
- TCG_REG_R4,
- TCG_REG_R5,
-#if TCG_TARGET_REG_BITS == 32
- /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
- TCG_REG_R6,
- TCG_REG_R7,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
-#endif
-};
+/* No call arguments via registers. All will be stored on the "stack". */
+static const int tcg_target_call_iarg_regs[] = { };
static const int tcg_target_call_oarg_regs[] = {
TCG_REG_R0,
@@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *label)
static void stack_bounds_check(TCGReg base, target_long offset)
{
if (base == TCG_REG_CALL_STACK) {
- tcg_debug_assert(offset < 0);
- tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long)));
+ tcg_debug_assert(offset >= 0);
+ tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE +
+ TCG_STATIC_FRAME_SIZE));
}
}
@@ -593,11 +579,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
}
}
-static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func,
+ ffi_cif *cif)
{
uint8_t *old_code_ptr = s->code_ptr;
+ uint8_t which;
+
+ if (cif->rtype == &ffi_type_void) {
+ which = 0;
+ } else if (cif->rtype->size == 4) {
+ which = 1;
+ } else {
+ tcg_debug_assert(cif->rtype->size == 8);
+ which = 2;
+ }
tcg_out_op_t(s, INDEX_op_call);
- tcg_out_i(s, (uintptr_t)arg);
+ tcg_out8(s, which);
+ tcg_out_i(s, (uintptr_t)func);
+ tcg_out_i(s, (uintptr_t)cif);
+
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
@@ -824,11 +824,9 @@ static void tcg_target_init(TCGContext *s)
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
- /* We use negative offsets from "sp" so that we can distinguish
- stores that might pretend to be call arguments. */
- tcg_set_frame(s, TCG_REG_CALL_STACK,
- -CPU_TEMP_BUF_NLONGS * sizeof(long),
- CPU_TEMP_BUF_NLONGS * sizeof(long));
+ /* The call arguments come first, followed by the temp storage. */
+ tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
+ TCG_STATIC_FRAME_SIZE);
}
/* Generate global QEMU prologue and epilogue code. */
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 11/27] tcg/tci: Use ffi for calls
2021-06-01 15:00 ` [PATCH v7 11/27] tcg/tci: Use ffi for calls Richard Henderson
@ 2021-06-02 10:31 ` Alex Bennée
0 siblings, 0 replies; 47+ messages in thread
From: Alex Bennée @ 2021-06-02 10:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: Philippe Mathieu-Daudé, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> This requires adjusting where arguments are stored.
> Place them on the stack at left-aligned positions.
> Adjust the stack frame to be at entirely positive offsets.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
FWIW checkpatch is being anal about comment formatting:
--8<---------------cut here---------------start------------->8---
fixup! tcg/tci: Use ffi for calls
2 files changed, 16 insertions(+), 14 deletions(-)
tcg/tcg.c | 24 ++++++++++++------------
tcg/tci.c | 6 ++++--
modified tcg/tcg.c
@@ -2148,18 +2148,18 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
}
if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
- /*
- * If stack grows up, then we will be placing successive
- * arguments at lower addresses, which means we need to
- * reverse the order compared to how we would normally
- * treat either big or little-endian. For those arguments
- * that will wind up in registers, this still works for
- * HPPA (the only current STACK_GROWSUP target) since the
- * argument registers are *also* allocated in decreasing
- * order. If another such target is added, this logic may
- * have to get more complicated to differentiate between
- * stack arguments and register arguments.
- */
+ /*
+ * If stack grows up, then we will be placing successive
+ * arguments at lower addresses, which means we need to
+ * reverse the order compared to how we would normally
+ * treat either big or little-endian. For those arguments
+ * that will wind up in registers, this still works for
+ * HPPA (the only current STACK_GROWSUP target) since the
+ * argument registers are *also* allocated in decreasing
+ * order. If another such target is added, this logic may
+ * have to get more complicated to differentiate between
+ * stack arguments and register arguments.
+ */
#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
op->args[pi++] = temp_arg(args[i] + 1);
op->args[pi++] = temp_arg(args[i]);
modified tcg/tci.c
@@ -26,8 +26,10 @@
#include <ffi.h>
-/* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
- * Without assertions, the interpreter runs much faster. */
+/*
+ * Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
+ * Without assertions, the interpreter runs much faster.
+ */
#if defined(CONFIG_DEBUG_TCG)
# define tci_assert(cond) assert(cond)
#else
--8<---------------cut here---------------end--------------->8---
--
Alex Bennée
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (10 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 11/27] tcg/tci: Use ffi for calls Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-19 15:50 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 13/27] tcg/tci: Emit setcond before brcond Richard Henderson
` (16 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
We're about to adjust the offset range on host memory ops,
and the format of branches. Both will require a temporary.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 1 +
tcg/tci/tcg-target.c.inc | 1 +
2 files changed, 2 insertions(+)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 4df10e2e83..1558a6e44e 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -155,6 +155,7 @@ typedef enum {
TCG_REG_R14,
TCG_REG_R15,
+ TCG_REG_TMP = TCG_REG_R13,
TCG_AREG0 = TCG_REG_R14,
TCG_REG_CALL_STACK = TCG_REG_R15,
} TCGReg;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 9ab7916300..d80fec3488 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -822,6 +822,7 @@ static void tcg_target_init(TCGContext *s)
MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS);
s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
/* The call arguments come first, followed by the temp storage. */
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary
2021-06-01 15:00 ` [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary Richard Henderson
@ 2021-06-19 15:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-19 15:50 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> We're about to adjust the offset range on host memory ops,
> and the format of branches. Both will require a temporary.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci/tcg-target.h | 1 +
> tcg/tci/tcg-target.c.inc | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 13/27] tcg/tci: Emit setcond before brcond
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (11 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-19 15:50 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 14/27] tcg/tci: Remove tci_write_reg Richard Henderson
` (15 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
The encoding planned for tci does not have enough room for
brcond2, with 4 registers and a condition as input as well
as the label. Resolve the condition into TCG_REG_TMP, and
relax brcond to one register plus a label, considering the
condition to always be reg != 0.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 68 ++++++++++------------------------------
tcg/tci/tcg-target.c.inc | 52 +++++++++++-------------------
2 files changed, 35 insertions(+), 85 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 3a6aeb1139..1e9e89458b 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -145,6 +145,16 @@ static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0,
check_size(start, tb_ptr);
}
+static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1)
+{
+ const uint8_t *start = *tb_ptr;
+
+ *r0 = tci_read_r(tb_ptr);
+ *l1 = (void *)tci_read_label(tb_ptr);
+
+ check_size(start, tb_ptr);
+}
+
static void tci_args_rr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1)
{
@@ -216,19 +226,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
check_size(start, tb_ptr);
}
-static void tci_args_rrcl(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *c2 = tci_read_b(tb_ptr);
- *l3 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-
static void tci_args_rrrc(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -297,21 +294,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr,
check_size(start, tb_ptr);
}
-static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
- TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *c4 = tci_read_b(tb_ptr);
- *l5 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
@@ -708,8 +690,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i32:
- tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
- if (tci_compare32(regs[r0], regs[r1], condition)) {
+ tci_args_rl(&tb_ptr, &r0, &ptr);
+ if ((uint32_t)regs[r0]) {
tb_ptr = ptr;
}
break;
@@ -726,15 +708,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
- case INDEX_op_brcond2_i32:
- tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
- T1 = tci_uint64(regs[r1], regs[r0]);
- T2 = tci_uint64(regs[r3], regs[r2]);
- if (tci_compare64(T1, T2, condition)) {
- tb_ptr = ptr;
- continue;
- }
- break;
case INDEX_op_mulu2_i32:
tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
@@ -862,8 +835,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
- if (tci_compare64(regs[r0], regs[r1], condition)) {
+ tci_args_rl(&tb_ptr, &r0, &ptr);
+ if (regs[r0]) {
tb_ptr = ptr;
}
break;
@@ -1174,9 +1147,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %p",
- op_name, str_r(r0), str_r(r1), str_c(c), ptr);
+ tci_args_rl(&tb_ptr, &r0, &ptr);
+ info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p",
+ op_name, str_r(r0), ptr);
break;
case INDEX_op_setcond_i32:
@@ -1301,13 +1274,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r3), str_r(r4), str_c(c));
break;
- case INDEX_op_brcond2_i32:
- tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %p",
- op_name, str_r(r0), str_r(r1),
- str_r(r2), str_r(r3), str_c(c), ptr);
- break;
-
case INDEX_op_mulu2_i32:
tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index d80fec3488..4841787e5f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -337,6 +337,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
}
#endif
+static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, op);
+ tcg_out_r(s, r0);
+ tci_out_label(s, l1);
+
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
uint8_t *old_code_ptr = s->code_ptr;
@@ -388,20 +399,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
-static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op,
- TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out8(s, c2);
- tci_out_label(s, l3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
@@ -475,23 +472,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
-static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op,
- TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3,
- TCGCond c4, TCGLabel *l5)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out8(s, c4);
- tci_out_label(s, l5);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGCond c5)
@@ -697,7 +677,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
CASE_32_64(brcond)
- tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3]));
+ tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
+ ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64),
+ TCG_REG_TMP, args[0], args[1], args[2]);
+ tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3]));
break;
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
@@ -723,8 +706,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
args[3], args[4], args[5]);
break;
case INDEX_op_brcond2_i32:
- tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2],
- args[3], args[4], arg_label(args[5]));
+ tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP,
+ args[0], args[1], args[2], args[3], args[4]);
+ tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5]));
break;
case INDEX_op_mulu2_i32:
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 13/27] tcg/tci: Emit setcond before brcond
2021-06-01 15:00 ` [PATCH v7 13/27] tcg/tci: Emit setcond before brcond Richard Henderson
@ 2021-06-19 15:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-19 15:50 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> The encoding planned for tci does not have enough room for
> brcond2, with 4 registers and a condition as input as well
> as the label. Resolve the condition into TCG_REG_TMP, and
> relax brcond to one register plus a label, considering the
> condition to always be reg != 0.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 68 ++++++++++------------------------------
> tcg/tci/tcg-target.c.inc | 52 +++++++++++-------------------
> 2 files changed, 35 insertions(+), 85 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 14/27] tcg/tci: Remove tci_write_reg
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (12 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 13/27] tcg/tci: Emit setcond before brcond Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units Richard Henderson
` (14 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Inline it into its one caller, tci_write_reg64.
Drop the asserts that are redundant with tcg_read_r.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 1e9e89458b..7dcf7f9529 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -36,20 +36,11 @@
__thread uintptr_t tci_tb_ptr;
-static void
-tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
-{
- tci_assert(index < TCG_TARGET_NB_REGS);
- tci_assert(index != TCG_AREG0);
- tci_assert(index != TCG_REG_CALL_STACK);
- regs[index] = value;
-}
-
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
{
- tci_write_reg(regs, low_index, value);
- tci_write_reg(regs, high_index, value >> 32);
+ regs[low_index] = value;
+ regs[high_index] = value >> 32;
}
/* Create a 64 bit value from two 32 bit values. */
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (13 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 14/27] tcg/tci: Remove tci_write_reg Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-12 10:21 ` Philippe Mathieu-Daudé
2021-06-19 17:48 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 16/27] tcg/tci: Implement goto_ptr Richard Henderson
` (13 subsequent siblings)
28 siblings, 2 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This removes all of the problems with unaligned accesses
to the bytecode stream.
With an 8-bit opcode at the bottom, we have 24 bits remaining,
which are generally split into 6 4-bit slots. This fits well
with the maximum length opcodes, e.g. INDEX_op_add2_i32, which
have 6 register operands.
We have, in previous patches, rearranged things such that there
are no operations with a label which have more than one other
operand. Which leaves us with a 20-bit field in which to encode
a label, giving us a maximum TB size of 512k -- easily large.
Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il].
The former puts the immediate in the upper 20 bits of the insn,
like we do for the label displacement. The later uses a label
to reference an entry in the constant pool. Thus, in the worst
case we still have a single memory reference for any constant,
but now the constants are out-of-line of the bytecode and can
be shared between different moves saving space.
Change INDEX_op_call to use a label to reference a pair of
pointers in the constant pool. This removes the only slightly
dodgy link with the layout of struct TCGHelperInfo.
The re-encode cannot be done in pieces.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 4 +-
tcg/tci/tcg-target.h | 3 +-
tcg/tci.c | 541 +++++++++++++++------------------------
tcg/tci/tcg-target.c.inc | 379 ++++++++++++---------------
tcg/tci/README | 20 +-
5 files changed, 384 insertions(+), 563 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index bbb0884af8..5bbec858aa 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#ifdef TCG_TARGET_INTERPRETER
/* These opcodes are only for use between the tci generator and interpreter. */
-DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
-DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
+DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT)
+DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT)
#endif
#undef TLADDR_ARGS
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 1558a6e44e..d953f2ead3 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -41,7 +41,7 @@
#define TCG_TARGET_H
#define TCG_TARGET_INTERPRETER 1
-#define TCG_TARGET_INSN_UNIT_SIZE 1
+#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
#if UINTPTR_MAX == UINT32_MAX
@@ -165,6 +165,7 @@ typedef enum {
#define TCG_TARGET_STACK_ALIGN 8
#define HAVE_TCG_QEMU_TB_EXEC
+#define TCG_TARGET_NEED_POOL_LABELS
/* We could notice __i386__ or __s390x__ and reduce the barriers depending
on the host. But if you want performance, you use the normal backend.
diff --git a/tcg/tci.c b/tcg/tci.c
index 7dcf7f9529..cb12de1cb5 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -49,49 +49,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low)
return ((uint64_t)high << 32) + low;
}
-/* Read constant byte from bytecode. */
-static uint8_t tci_read_b(const uint8_t **tb_ptr)
-{
- return *(tb_ptr[0]++);
-}
-
-/* Read register number from bytecode. */
-static TCGReg tci_read_r(const uint8_t **tb_ptr)
-{
- uint8_t regno = tci_read_b(tb_ptr);
- tci_assert(regno < TCG_TARGET_NB_REGS);
- return regno;
-}
-
-/* Read constant (native size) from bytecode. */
-static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr)
-{
- tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-
-/* Read unsigned constant (32 bit) from bytecode. */
-static uint32_t tci_read_i32(const uint8_t **tb_ptr)
-{
- uint32_t value = *(const uint32_t *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-
-/* Read signed constant (32 bit) from bytecode. */
-static int32_t tci_read_s32(const uint8_t **tb_ptr)
-{
- int32_t value = *(const int32_t *)(*tb_ptr);
- *tb_ptr += sizeof(value);
- return value;
-}
-
-static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
-{
- return tci_read_i(tb_ptr);
-}
-
/*
* Load sets of arguments all at once. The naming convention is:
* tci_args_<arguments>
@@ -108,211 +65,128 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* s = signed ldst offset
*/
-static void check_size(const uint8_t *start, const uint8_t **tb_ptr)
+static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0)
{
- const uint8_t *old_code_ptr = start - 2;
- uint8_t op_size = old_code_ptr[1];
- tci_assert(*tb_ptr == old_code_ptr + op_size);
+ int diff = sextract32(insn, 12, 20);
+ *l0 = diff ? (void *)tb_ptr + diff : NULL;
}
-static void tci_args_l(const uint8_t **tb_ptr, void **l0)
+static void tci_args_nl(uint32_t insn, const void *tb_ptr,
+ uint8_t *n0, void **l1)
{
- const uint8_t *start = *tb_ptr;
-
- *l0 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
+ *n0 = extract32(insn, 8, 4);
+ *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
}
-static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0,
- void **l1, void **l2)
+static void tci_args_rl(uint32_t insn, const void *tb_ptr,
+ TCGReg *r0, void **l1)
{
- const uint8_t *start = *tb_ptr;
-
- *n0 = tci_read_b(tb_ptr);
- *l1 = (void *)tci_read_label(tb_ptr);
- *l2 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
}
-static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1)
+static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *l1 = (void *)tci_read_label(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
}
-static void tci_args_rr(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1)
+static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *i1 = sextract32(insn, 12, 20);
}
-static void tci_args_ri(const uint8_t **tb_ptr,
- TCGReg *r0, tcg_target_ulong *i1)
+static void tci_args_rrm(uint32_t insn, TCGReg *r0,
+ TCGReg *r1, TCGMemOpIdx *m2)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *i1 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *m2 = extract32(insn, 20, 12);
}
-#if TCG_TARGET_REG_BITS == 64
-static void tci_args_rI(const uint8_t **tb_ptr,
- TCGReg *r0, tcg_target_ulong *i1)
+static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *i1 = tci_read_i(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-#endif
-
-static void tci_args_rrm(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *m2 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
}
-static void tci_args_rrr(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, TCGReg *r2)
+static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *i2 = sextract32(insn, 16, 16);
}
-static void tci_args_rrs(const uint8_t **tb_ptr,
- TCGReg *r0, TCGReg *r1, int32_t *i2)
-{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *i2 = tci_read_s32(tb_ptr);
-
- check_size(start, tb_ptr);
-}
-
-static void tci_args_rrrc(const uint8_t **tb_ptr,
+static void tci_args_rrrc(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *c3 = tci_read_b(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *c3 = extract32(insn, 20, 4);
}
-static void tci_args_rrrm(const uint8_t **tb_ptr,
+static void tci_args_rrrm(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *m3 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *m3 = extract32(insn, 20, 12);
}
-static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *i3 = tci_read_b(tb_ptr);
- *i4 = tci_read_b(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *i3 = extract32(insn, 20, 6);
+ *i4 = extract32(insn, 26, 6);
}
-static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
- TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4)
+static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGReg *r4)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *m4 = tci_read_i32(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
+ *r4 = extract32(insn, 24, 4);
}
#if TCG_TARGET_REG_BITS == 32
-static void tci_args_rrrr(const uint8_t **tb_ptr,
+static void tci_args_rrrr(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
}
-static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *r4 = tci_read_r(tb_ptr);
- *c5 = tci_read_b(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
+ *r4 = extract32(insn, 24, 4);
+ *c5 = extract32(insn, 28, 4);
}
-static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
- const uint8_t *start = *tb_ptr;
-
- *r0 = tci_read_r(tb_ptr);
- *r1 = tci_read_r(tb_ptr);
- *r2 = tci_read_r(tb_ptr);
- *r3 = tci_read_r(tb_ptr);
- *r4 = tci_read_r(tb_ptr);
- *r5 = tci_read_r(tb_ptr);
-
- check_size(start, tb_ptr);
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *r2 = extract32(insn, 16, 4);
+ *r3 = extract32(insn, 20, 4);
+ *r4 = extract32(insn, 24, 4);
+ *r5 = extract32(insn, 28, 4);
}
#endif
@@ -450,7 +324,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
const void *v_tb_ptr)
{
- const uint8_t *tb_ptr = v_tb_ptr;
+ const uint32_t *tb_ptr = v_tb_ptr;
tcg_target_ulong regs[TCG_TARGET_NB_REGS];
uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE)
/ sizeof(uint64_t)];
@@ -463,8 +337,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_assert(tb_ptr);
for (;;) {
- TCGOpcode opc = tb_ptr[0];
- TCGReg r0, r1, r2, r3;
+ uint32_t insn;
+ TCGOpcode opc;
+ TCGReg r0, r1, r2, r3, r4;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
@@ -472,15 +347,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r4, r5;
+ TCGReg r5;
uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
int32_t ofs;
- void *ptr, *cif;
+ void *ptr;
- /* Skip opcode and size entry. */
- tb_ptr += 2;
+ insn = *tb_ptr++;
+ opc = extract32(insn, 0, 8);
switch (opc) {
case INDEX_op_call:
@@ -496,12 +371,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
}
- tci_args_nll(&tb_ptr, &len, &ptr, &cif);
+ tci_args_nl(insn, tb_ptr, &len, &ptr);
/* Helper functions may need to access the "return address" */
tci_tb_ptr = (uintptr_t)tb_ptr;
- ffi_call(cif, ptr, stack, call_slots);
+ {
+ void **pptr = ptr;
+ ffi_call(pptr[1], pptr[0], stack, call_slots);
+ }
/* Any result winds up "left-aligned" in the stack[0] slot. */
switch (len) {
@@ -530,76 +408,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
case INDEX_op_br:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
tb_ptr = ptr;
continue;
case INDEX_op_setcond_i32:
- tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
+ tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition);
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
T1 = tci_uint64(regs[r2], regs[r1]);
T2 = tci_uint64(regs[r4], regs[r3]);
regs[r0] = tci_compare64(T1, T2, condition);
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
- tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition);
+ tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
break;
#endif
CASE_32_64(mov)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = regs[r1];
break;
- case INDEX_op_tci_movi_i32:
- tci_args_ri(&tb_ptr, &r0, &t1);
+ case INDEX_op_tci_movi:
+ tci_args_ri(insn, &r0, &t1);
regs[r0] = t1;
break;
+ case INDEX_op_tci_movl:
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
+ regs[r0] = *(tcg_target_ulong *)ptr;
+ break;
/* Load/store operations (32 bit). */
CASE_32_64(ld8u)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint8_t *)ptr;
break;
CASE_32_64(ld8s)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(int8_t *)ptr;
break;
CASE_32_64(ld16u)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint16_t *)ptr;
break;
CASE_32_64(ld16s)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(int16_t *)ptr;
break;
case INDEX_op_ld_i32:
CASE_64(ld32u)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint32_t *)ptr;
break;
CASE_32_64(st8)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint8_t *)ptr = regs[r0];
break;
CASE_32_64(st16)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint16_t *)ptr = regs[r0];
break;
case INDEX_op_st_i32:
CASE_64(st32)
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint32_t *)ptr = regs[r0];
break;
@@ -607,171 +489,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (mixed 32/64 bit). */
CASE_32_64(add)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] + regs[r2];
break;
CASE_32_64(sub)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] - regs[r2];
break;
CASE_32_64(mul)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] * regs[r2];
break;
CASE_32_64(and)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] & regs[r2];
break;
CASE_32_64(or)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] | regs[r2];
break;
CASE_32_64(xor)
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
/* Arithmetic operations (32 bit). */
case INDEX_op_div_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
break;
case INDEX_op_divu_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
break;
case INDEX_op_rem_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
break;
case INDEX_op_remu_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
/* Shift/rotate operations (32 bit). */
case INDEX_op_shl_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
break;
case INDEX_op_shr_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
break;
case INDEX_op_sar_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = rol32(regs[r1], regs[r2] & 31);
break;
case INDEX_op_rotr_i32:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ror32(regs[r1], regs[r2] & 31);
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
- tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
break;
#endif
case INDEX_op_brcond_i32:
- tci_args_rl(&tb_ptr, &r0, &ptr);
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
if ((uint32_t)regs[r0]) {
tb_ptr = ptr;
}
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
- tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 + T2);
break;
case INDEX_op_sub2_i32:
- tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
case INDEX_op_mulu2_i32:
- tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (int8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (int16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap16(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap32(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = ~regs[r1];
break;
#endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg)
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = -regs[r1];
break;
#endif
#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_tci_movi_i64:
- tci_args_rI(&tb_ptr, &r0, &t1);
- regs[r0] = t1;
- break;
-
/* Load/store operations (64 bit). */
case INDEX_op_ld32s_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(int32_t *)ptr;
break;
case INDEX_op_ld_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
regs[r0] = *(uint64_t *)ptr;
break;
case INDEX_op_st_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &ofs);
+ tci_args_rrs(insn, &r0, &r1, &ofs);
ptr = (void *)(regs[r1] + ofs);
*(uint64_t *)ptr = regs[r0];
break;
@@ -779,71 +656,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (64 bit). */
case INDEX_op_div_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
break;
case INDEX_op_divu_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
break;
case INDEX_op_rem_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
break;
case INDEX_op_remu_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] << (regs[r2] & 63);
break;
case INDEX_op_shr_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] >> (regs[r2] & 63);
break;
case INDEX_op_sar_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = rol64(regs[r1], regs[r2] & 63);
break;
case INDEX_op_rotr_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ror64(regs[r1], regs[r2] & 63);
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
- tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
break;
#endif
case INDEX_op_brcond_i64:
- tci_args_rl(&tb_ptr, &r0, &ptr);
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
if (regs[r0]) {
tb_ptr = ptr;
}
break;
case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (int32_t)regs[r1];
break;
case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = (uint32_t)regs[r1];
break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
regs[r0] = bswap64(regs[r1]);
break;
#endif
@@ -852,20 +729,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* QEMU specific operations. */
case INDEX_op_exit_tb:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
return (uintptr_t)ptr;
case INDEX_op_goto_tb:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
tb_ptr = *(void **)ptr;
break;
case INDEX_op_qemu_ld_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
@@ -901,14 +778,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_ld_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = regs[r2];
} else {
- tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
taddr = tci_uint64(regs[r3], regs[r2]);
+ oi = regs[r4];
}
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
@@ -959,10 +837,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_st_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
@@ -989,16 +867,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
tmp64 = regs[r0];
} else {
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = regs[r2];
} else {
- tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
taddr = tci_uint64(regs[r3], regs[r2]);
+ oi = regs[r4];
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
@@ -1082,87 +961,69 @@ static const char *str_c(TCGCond c)
/* Disassemble TCI bytecode. */
int print_insn_tci(bfd_vma addr, disassemble_info *info)
{
- uint8_t buf[256];
- int length, status;
+ const uint32_t *tb_ptr = (const void *)(uintptr_t)addr;
const TCGOpDef *def;
const char *op_name;
+ uint32_t insn;
TCGOpcode op;
- TCGReg r0, r1, r2, r3;
+ TCGReg r0, r1, r2, r3, r4;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r4, r5;
+ TCGReg r5;
#endif
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
TCGMemOpIdx oi;
uint8_t pos, len;
- void *ptr, *cif;
- const uint8_t *tb_ptr;
+ void *ptr;
- status = info->read_memory_func(addr, buf, 2, info);
- if (status != 0) {
- info->memory_error_func(status, addr, info);
- return -1;
- }
- op = buf[0];
- length = buf[1];
+ /* TCI is always the host, so we don't need to load indirect. */
+ insn = *tb_ptr++;
- if (length < 2) {
- info->fprintf_func(info->stream, "invalid length %d", length);
- return 1;
- }
-
- status = info->read_memory_func(addr + 2, buf + 2, length - 2, info);
- if (status != 0) {
- info->memory_error_func(status, addr + 2, info);
- return -1;
- }
+ info->fprintf_func(info->stream, "%08x ", insn);
+ op = extract32(insn, 0, 8);
def = &tcg_op_defs[op];
op_name = def->name;
- tb_ptr = buf + 2;
switch (op) {
case INDEX_op_br:
case INDEX_op_exit_tb:
case INDEX_op_goto_tb:
- tci_args_l(&tb_ptr, &ptr);
+ tci_args_l(insn, tb_ptr, &ptr);
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
case INDEX_op_call:
- tci_args_nll(&tb_ptr, &len, &ptr, &cif);
- info->fprintf_func(info->stream, "%-12s %d, %p, %p",
- op_name, len, ptr, cif);
+ tci_args_nl(insn, tb_ptr, &len, &ptr);
+ info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr);
break;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- tci_args_rl(&tb_ptr, &r0, &ptr);
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p",
op_name, str_r(r0), ptr);
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c);
+ tci_args_rrrc(insn, &r0, &r1, &r2, &c);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
break;
- case INDEX_op_tci_movi_i32:
- tci_args_ri(&tb_ptr, &r0, &i1);
- info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
+ case INDEX_op_tci_movi:
+ tci_args_ri(insn, &r0, &i1);
+ info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
op_name, str_r(r0), i1);
break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_tci_movi_i64:
- tci_args_rI(&tb_ptr, &r0, &i1);
- info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
- op_name, str_r(r0), i1);
+ case INDEX_op_tci_movl:
+ tci_args_rl(insn, tb_ptr, &r0, &ptr);
+ info->fprintf_func(info->stream, "%-12s %s, %p",
+ op_name, str_r(r0), ptr);
break;
-#endif
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -1183,7 +1044,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_st32_i64:
case INDEX_op_st_i32:
case INDEX_op_st_i64:
- tci_args_rrs(&tb_ptr, &r0, &r1, &s2);
+ tci_args_rrs(insn, &r0, &r1, &s2);
info->fprintf_func(info->stream, "%-12s %s, %s, %d",
op_name, str_r(r0), str_r(r1), s2);
break;
@@ -1210,7 +1071,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
- tci_args_rr(&tb_ptr, &r0, &r1);
+ tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s",
op_name, str_r(r0), str_r(r1));
break;
@@ -1245,28 +1106,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
- tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2));
break;
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
+ tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c);
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_c(c));
break;
case INDEX_op_mulu2_i32:
- tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3));
@@ -1274,7 +1135,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_r(r5));
@@ -1292,30 +1153,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS);
switch (len) {
case 2:
- tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ tci_args_rrm(insn, &r0, &r1, &oi);
info->fprintf_func(info->stream, "%-12s %s, %s, %x",
op_name, str_r(r0), str_r(r1), oi);
break;
case 3:
- tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x",
op_name, str_r(r0), str_r(r1), str_r(r2), oi);
break;
case 4:
- tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %x",
+ tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
+ info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1),
- str_r(r2), str_r(r3), oi);
+ str_r(r2), str_r(r3), str_r(r4));
break;
default:
g_assert_not_reached();
}
break;
+ case 0:
+ /* tcg_out_nop_fill uses zeros */
+ if (insn == 0) {
+ info->fprintf_func(info->stream, "align");
+ break;
+ }
+ /* fall through */
+
default:
info->fprintf_func(info->stream, "illegal opcode %d", op);
break;
}
- return length;
+ return sizeof(insn);
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 4841787e5f..acb5f6c75e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -22,20 +22,7 @@
* THE SOFTWARE.
*/
-/* TODO list:
- * - See TODO comments in code.
- */
-
-/* Marker for missing code. */
-#define TODO() \
- do { \
- fprintf(stderr, "TODO %s:%u: %s()\n", \
- __FILE__, __LINE__, __func__); \
- tcg_abort(); \
- } while (0)
-
-/* Bitfield n...m (in 32 bit value). */
-#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
+#include "../tcg-pool.c.inc"
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
{
@@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
- /* tcg_out_reloc always uses the same type, addend. */
- tcg_debug_assert(type == sizeof(tcg_target_long));
+ intptr_t diff = value - (intptr_t)(code_ptr + 1);
+
tcg_debug_assert(addend == 0);
- tcg_debug_assert(value != 0);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_patch32(code_ptr, value);
- } else {
- tcg_patch64(code_ptr, value);
- }
- return true;
-}
-
-/* Write value (native size). */
-static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
-{
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out32(s, v);
- } else {
- tcg_out64(s, v);
- }
-}
-
-/* Write opcode. */
-static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
-{
- tcg_out8(s, op);
- tcg_out8(s, 0);
-}
-
-/* Write register. */
-static void tcg_out_r(TCGContext *s, TCGArg t0)
-{
- tcg_debug_assert(t0 < TCG_TARGET_NB_REGS);
- tcg_out8(s, t0);
-}
-
-/* Write label. */
-static void tci_out_label(TCGContext *s, TCGLabel *label)
-{
- if (label->has_value) {
- tcg_out_i(s, label->u.value);
- tcg_debug_assert(label->u.value);
- } else {
- tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
- s->code_ptr += sizeof(tcg_target_ulong);
+ tcg_debug_assert(type == 20);
+
+ if (diff == sextract32(diff, 0, type)) {
+ tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff));
+ return true;
}
+ return false;
}
static void stack_bounds_check(TCGReg base, target_long offset)
@@ -285,239 +236,236 @@ static void stack_bounds_check(TCGReg base, target_long offset)
static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tci_out_label(s, l0);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_reloc(s, s->code_ptr, 20, l0, 0);
+ insn = deposit32(insn, 0, 8, op);
+ tcg_out32(s, insn);
}
static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
+ intptr_t diff;
- tcg_out_op_t(s, op);
- tcg_out_i(s, (uintptr_t)p0);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ /* Special case for exit_tb: map null -> 0. */
+ if (p0 == NULL) {
+ diff = 0;
+ } else {
+ diff = p0 - (void *)(s->code_ptr + 1);
+ tcg_debug_assert(diff != 0);
+ if (diff != sextract32(diff, 0, 20)) {
+ tcg_raise_tb_overflow(s);
+ }
+ }
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 12, 20, diff);
+ tcg_out32(s, insn);
}
static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out32(s, (uint8_t)op);
}
static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out32(s, i1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(i1 == sextract32(i1, 0, 20));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 20, i1);
+ tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
- TCGReg r0, uint64_t i1)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out64(s, i1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-#endif
-
static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tci_out_label(s, l1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_out_reloc(s, s->code_ptr, 20, l1, 0);
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGArg m2)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out32(s, m2);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(m2 == extract32(m2, 0, 12));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 20, 12, m2);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, intptr_t i2)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_debug_assert(i2 == (int32_t)i2);
- tcg_out32(s, i2);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(i2 == sextract32(i2, 0, 16));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 16, i2);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out8(s, c3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, c3);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out32(s, m3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(m3 == extract32(m3, 0, 12));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 12, m3);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out8(s, b3);
- tcg_out8(s, b4);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ tcg_debug_assert(b3 == extract32(b3, 0, 6));
+ tcg_debug_assert(b4 == extract32(b4, 0, 6));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 6, b3);
+ insn = deposit32(insn, 26, 6, b4);
+ tcg_out32(s, insn);
}
-static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0,
- TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4)
+static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out32(s, m4);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ insn = deposit32(insn, 24, 4, r4);
+ tcg_out32(s, insn);
}
#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGCond c5)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out_r(s, r4);
- tcg_out8(s, c5);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ insn = deposit32(insn, 24, 4, r4);
+ insn = deposit32(insn, 28, 4, c5);
+ tcg_out32(s, insn);
}
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
- tcg_out_op_t(s, op);
- tcg_out_r(s, r0);
- tcg_out_r(s, r1);
- tcg_out_r(s, r2);
- tcg_out_r(s, r3);
- tcg_out_r(s, r4);
- tcg_out_r(s, r5);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 4, r2);
+ insn = deposit32(insn, 20, 4, r3);
+ insn = deposit32(insn, 24, 4, r4);
+ insn = deposit32(insn, 28, 4, r5);
+ tcg_out32(s, insn);
}
#endif
+static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val,
+ TCGReg base, intptr_t offset)
+{
+ stack_bounds_check(base, offset);
+ if (offset != sextract32(offset, 0, 16)) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
+ tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS == 32
+ ? INDEX_op_add_i32 : INDEX_op_add_i64),
+ TCG_REG_TMP, TCG_REG_TMP, base);
+ base = TCG_REG_TMP;
+ offset = 0;
+ }
+ tcg_out_op_rrs(s, op, val, base, offset);
+}
+
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
intptr_t offset)
{
- stack_bounds_check(base, offset);
switch (type) {
case TCG_TYPE_I32:
- tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset);
+ tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset);
break;
#if TCG_TARGET_REG_BITS == 64
case TCG_TYPE_I64:
- tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset);
+ tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset);
break;
#endif
default:
@@ -547,22 +495,32 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
{
switch (type) {
case TCG_TYPE_I32:
- tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg);
- break;
#if TCG_TARGET_REG_BITS == 64
+ arg = (int32_t)arg;
+ /* fall through */
case TCG_TYPE_I64:
- tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg);
- break;
#endif
+ break;
default:
g_assert_not_reached();
}
+
+ if (arg == sextract32(arg, 0, 20)) {
+ tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg);
+ } else {
+ tcg_insn_unit insn = 0;
+
+ new_pool_label(s, arg, 20, s->code_ptr, 0);
+ insn = deposit32(insn, 0, 8, INDEX_op_tci_movl);
+ insn = deposit32(insn, 8, 4, ret);
+ tcg_out32(s, insn);
+ }
}
static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func,
ffi_cif *cif)
{
- uint8_t *old_code_ptr = s->code_ptr;
+ tcg_insn_unit insn = 0;
uint8_t which;
if (cif->rtype == &ffi_type_void) {
@@ -573,12 +531,10 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func,
tcg_debug_assert(cif->rtype->size == 8);
which = 2;
}
- tcg_out_op_t(s, INDEX_op_call);
- tcg_out8(s, which);
- tcg_out_i(s, (uintptr_t)func);
- tcg_out_i(s, (uintptr_t)cif);
-
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif);
+ insn = deposit32(insn, 0, 8, INDEX_op_call);
+ insn = deposit32(insn, 8, 4, which);
+ tcg_out32(s, insn);
}
#if TCG_TARGET_REG_BITS == 64
@@ -637,8 +593,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st_i32:
CASE_64(st32)
CASE_64(st)
- stack_bounds_check(args[1], args[2]);
- tcg_out_op_rrs(s, opc, args[0], args[1], args[2]);
+ tcg_out_ldst(s, opc, args[0], args[1], args[2]);
break;
CASE_32_64(add)
@@ -731,8 +686,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
} else {
- tcg_out_op_rrrrm(s, opc, args[0], args[1],
- args[2], args[3], args[4]);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
+ tcg_out_op_rrrrr(s, opc, args[0], args[1],
+ args[2], args[3], TCG_REG_TMP);
}
break;
@@ -780,6 +736,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
return arg_ct->ct & TCG_CT_CONST;
}
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ memset(p, 0, sizeof(*p) * count);
+}
+
static void tcg_target_init(TCGContext *s)
{
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
diff --git a/tcg/tci/README b/tcg/tci/README
index 9bb7d7a5d3..f72a40a395 100644
--- a/tcg/tci/README
+++ b/tcg/tci/README
@@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does.
Like each TCG host frontend, TCI implements the code generator in
tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci.
-The additional file tcg/tci.c adds the interpreter.
+The additional file tcg/tci.c adds the interpreter and disassembler.
-The bytecode consists of opcodes (same numeric values as those used by
-TCG), command length and arguments of variable size and number.
+The bytecode consists of opcodes (with only a few exceptions, with
+the same same numeric values and semantics as used by TCG), and up
+to six arguments packed into a 32-bit integer. See comments in tci.c
+for details on the encoding.
3) Usage
@@ -39,11 +41,6 @@ suggest using this option. Setting it automatically would need
additional code in configure which must be fixed when new native TCG
implementations are added.
-System emulation should work on any 32 or 64 bit host.
-User mode emulation might work. Maybe a new linker script (*.ld)
-is needed. Byte order might be wrong (on big endian hosts)
-and need fixes in configure.
-
For hosts with native TCG, the interpreter TCI can be enabled by
configure --enable-tcg-interpreter
@@ -118,13 +115,6 @@ u1 = linux-user-test works
in the interpreter. These opcodes raise a runtime exception, so it is
possible to see where code must be added.
-* The pseudo code is not optimized and still ugly. For hosts with special
- alignment requirements, it needs some fixes (maybe aligned bytecode
- would also improve speed for hosts which support byte alignment).
-
-* A better disassembler for the pseudo code would be nice (a very primitive
- disassembler is included in tcg-target.c.inc).
-
* It might be useful to have a runtime option which selects the native TCG
or TCI, so QEMU would have to include two TCGs. Today, selecting TCI
is a configure option, so you need two compilations of QEMU.
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units
2021-06-01 15:00 ` [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units Richard Henderson
@ 2021-06-12 10:21 ` Philippe Mathieu-Daudé
2021-06-12 15:40 ` Richard Henderson
2021-06-19 17:48 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-12 10:21 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> This removes all of the problems with unaligned accesses
> to the bytecode stream.
>
> With an 8-bit opcode at the bottom, we have 24 bits remaining,
> which are generally split into 6 4-bit slots. This fits well
> with the maximum length opcodes, e.g. INDEX_op_add2_i32, which
> have 6 register operands.
>
> We have, in previous patches, rearranged things such that there
> are no operations with a label which have more than one other
> operand. Which leaves us with a 20-bit field in which to encode
> a label, giving us a maximum TB size of 512k -- easily large.
>
> Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il].
> The former puts the immediate in the upper 20 bits of the insn,
> like we do for the label displacement. The later uses a label
> to reference an entry in the constant pool. Thus, in the worst
> case we still have a single memory reference for any constant,
> but now the constants are out-of-line of the bytecode and can
> be shared between different moves saving space.
>
> Change INDEX_op_call to use a label to reference a pair of
> pointers in the constant pool. This removes the only slightly
> dodgy link with the layout of struct TCGHelperInfo.
>
> The re-encode cannot be done in pieces.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 4 +-
> tcg/tci/tcg-target.h | 3 +-
> tcg/tci.c | 541 +++++++++++++++------------------------
> tcg/tci/tcg-target.c.inc | 379 ++++++++++++---------------
> tcg/tci/README | 20 +-
> 5 files changed, 384 insertions(+), 563 deletions(-)
[ ... ]
> + case 0:
> + /* tcg_out_nop_fill uses zeros */
> + if (insn == 0) {
> + info->fprintf_func(info->stream, "align");
"nop"?
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> + break;
> + }
> + /* fall through */
> +
> default:
> info->fprintf_func(info->stream, "illegal opcode %d", op);
> break;
> }
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units
2021-06-12 10:21 ` Philippe Mathieu-Daudé
@ 2021-06-12 15:40 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-12 15:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 6/12/21 3:21 AM, Philippe Mathieu-Daudé wrote:
> On 6/1/21 5:00 PM, Richard Henderson wrote:
>> This removes all of the problems with unaligned accesses
>> to the bytecode stream.
>>
>> With an 8-bit opcode at the bottom, we have 24 bits remaining,
>> which are generally split into 6 4-bit slots. This fits well
>> with the maximum length opcodes, e.g. INDEX_op_add2_i32, which
>> have 6 register operands.
>>
>> We have, in previous patches, rearranged things such that there
>> are no operations with a label which have more than one other
>> operand. Which leaves us with a 20-bit field in which to encode
>> a label, giving us a maximum TB size of 512k -- easily large.
>>
>> Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il].
>> The former puts the immediate in the upper 20 bits of the insn,
>> like we do for the label displacement. The later uses a label
>> to reference an entry in the constant pool. Thus, in the worst
>> case we still have a single memory reference for any constant,
>> but now the constants are out-of-line of the bytecode and can
>> be shared between different moves saving space.
>>
>> Change INDEX_op_call to use a label to reference a pair of
>> pointers in the constant pool. This removes the only slightly
>> dodgy link with the layout of struct TCGHelperInfo.
>>
>> The re-encode cannot be done in pieces.
>>
>> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/tcg/tcg-opc.h | 4 +-
>> tcg/tci/tcg-target.h | 3 +-
>> tcg/tci.c | 541 +++++++++++++++------------------------
>> tcg/tci/tcg-target.c.inc | 379 ++++++++++++---------------
>> tcg/tci/README | 20 +-
>> 5 files changed, 384 insertions(+), 563 deletions(-)
> [ ... ]
>
>> + case 0:
>> + /* tcg_out_nop_fill uses zeros */
>> + if (insn == 0) {
>> + info->fprintf_func(info->stream, "align");
>
> "nop"?
You can't execute it as a nop. It's just alignment.
>
> Otherwise,
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
>> + break;
>> + }
>> + /* fall through */
>> +
>> default:
>> info->fprintf_func(info->stream, "illegal opcode %d", op);
>> break;
>> }
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units
2021-06-01 15:00 ` [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-06-12 10:21 ` Philippe Mathieu-Daudé
@ 2021-06-19 17:48 ` Philippe Mathieu-Daudé
2021-06-19 18:05 ` Richard Henderson
1 sibling, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-19 17:48 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> This removes all of the problems with unaligned accesses
> to the bytecode stream.
>
> With an 8-bit opcode at the bottom, we have 24 bits remaining,
> which are generally split into 6 4-bit slots. This fits well
> with the maximum length opcodes, e.g. INDEX_op_add2_i32, which
> have 6 register operands.
>
> We have, in previous patches, rearranged things such that there
> are no operations with a label which have more than one other
> operand. Which leaves us with a 20-bit field in which to encode
> a label, giving us a maximum TB size of 512k -- easily large.
>
> Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il].
> The former puts the immediate in the upper 20 bits of the insn,
> like we do for the label displacement. The later uses a label
> to reference an entry in the constant pool. Thus, in the worst
> case we still have a single memory reference for any constant,
> but now the constants are out-of-line of the bytecode and can
> be shared between different moves saving space.
>
> Change INDEX_op_call to use a label to reference a pair of
> pointers in the constant pool. This removes the only slightly
> dodgy link with the layout of struct TCGHelperInfo.
>
> The re-encode cannot be done in pieces.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 4 +-
> tcg/tci/tcg-target.h | 3 +-
> tcg/tci.c | 541 +++++++++++++++------------------------
> tcg/tci/tcg-target.c.inc | 379 ++++++++++++---------------
> tcg/tci/README | 20 +-
> 5 files changed, 384 insertions(+), 563 deletions(-)
> @@ -1082,87 +961,69 @@ static const char *str_c(TCGCond c)
> /* Disassemble TCI bytecode. */
> int print_insn_tci(bfd_vma addr, disassemble_info *info)
> {
> case INDEX_op_setcond_i32:
> case INDEX_op_setcond_i64:
> - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c);
> + tci_args_rrrc(insn, &r0, &r1, &r2, &c);
> info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
> op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
> break;
>
> - case INDEX_op_tci_movi_i32:
> - tci_args_ri(&tb_ptr, &r0, &i1);
> - info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
> + case INDEX_op_tci_movi:
> + tci_args_ri(insn, &r0, &i1);
> + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
Missing space in format: "%s, 0x%"
> op_name, str_r(r0), i1);
> break;
>
> -#if TCG_TARGET_REG_BITS == 64
> - case INDEX_op_tci_movi_i64:
> - tci_args_rI(&tb_ptr, &r0, &i1);
> - info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
> - op_name, str_r(r0), i1);
> + case INDEX_op_tci_movl:
> + tci_args_rl(insn, tb_ptr, &r0, &ptr);
> + info->fprintf_func(info->stream, "%-12s %s, %p",
> + op_name, str_r(r0), ptr);
> break;
> -#endif
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units
2021-06-19 17:48 ` Philippe Mathieu-Daudé
@ 2021-06-19 18:05 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-19 18:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 6/19/21 10:48 AM, Philippe Mathieu-Daudé wrote:
>> + case INDEX_op_tci_movi:
>> + tci_args_ri(insn, &r0, &i1);
>> + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "",
>
> Missing space in format: "%s, 0x%"
Squashed, thanks.
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 16/27] tcg/tci: Implement goto_ptr
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (14 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 15/27] tcg/tci: Change encoding to uint32_t units Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-12 9:45 ` Philippe Mathieu-Daudé
2021-06-01 15:00 ` [PATCH v7 17/27] tcg/tci: Implement movcond Richard Henderson
` (12 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This operation is critical to staying within the interpretation
loop longer, which avoids the overhead of setup and teardown for
many TBs.
The check in tcg_prologue_init is disabled because TCI does
want to use NULL to indicate exit, as opposed to branching to
a real epilogue.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-con-set.h | 1 +
tcg/tci/tcg-target.h | 2 +-
tcg/tcg.c | 2 ++
tcg/tci.c | 19 +++++++++++++++++++
tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++
5 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
index 316730f32c..ae2dc3b844 100644
--- a/tcg/tci/tcg-target-con-set.h
+++ b/tcg/tci/tcg-target-con-set.h
@@ -9,6 +9,7 @@
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
+C_O0_I1(r)
C_O0_I2(r, r)
C_O0_I3(r, r, r)
C_O0_I4(r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index d953f2ead3..17911d3297 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -86,7 +86,7 @@
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
-#define TCG_TARGET_HAS_goto_ptr 0
+#define TCG_TARGET_HAS_goto_ptr 1
#define TCG_TARGET_HAS_direct_jump 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
diff --git a/tcg/tcg.c b/tcg/tcg.c
index c8e6dfb845..3d856371a1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1353,10 +1353,12 @@ void tcg_prologue_init(TCGContext *s)
}
#endif
+#ifndef CONFIG_TCG_INTERPRETER
/* Assert that goto_ptr is implemented completely. */
if (TCG_TARGET_HAS_goto_ptr) {
tcg_debug_assert(tcg_code_gen_epilogue != NULL);
}
+#endif
}
void tcg_func_start(TCGContext *s)
diff --git a/tcg/tci.c b/tcg/tci.c
index cb12de1cb5..3636b03adf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -71,6 +71,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0)
*l0 = diff ? (void *)tb_ptr + diff : NULL;
}
+static void tci_args_r(uint32_t insn, TCGReg *r0)
+{
+ *r0 = extract32(insn, 8, 4);
+}
+
static void tci_args_nl(uint32_t insn, const void *tb_ptr,
uint8_t *n0, void **l1)
{
@@ -737,6 +742,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tb_ptr = *(void **)ptr;
break;
+ case INDEX_op_goto_ptr:
+ tci_args_r(insn, &r0);
+ ptr = (void *)regs[r0];
+ if (!ptr) {
+ return 0;
+ }
+ tb_ptr = ptr;
+ break;
+
case INDEX_op_qemu_ld_i32:
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
tci_args_rrm(insn, &r0, &r1, &oi);
@@ -994,6 +1008,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
break;
+ case INDEX_op_goto_ptr:
+ tci_args_r(insn, &r0);
+ info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0));
+ break;
+
case INDEX_op_call:
tci_args_nl(insn, tb_ptr, &len, &ptr);
info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index acb5f6c75e..01a8e20c5d 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -27,6 +27,9 @@
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
{
switch (op) {
+ case INDEX_op_goto_ptr:
+ return C_O0_I1(r);
+
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
@@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0)
tcg_out32(s, insn);
}
+static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0)
+{
+ tcg_insn_unit insn = 0;
+
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ tcg_out32(s, insn);
+}
+
static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
{
tcg_out32(s, (uint8_t)op);
@@ -565,6 +577,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
set_jmp_reset_offset(s, args[0]);
break;
+ case INDEX_op_goto_ptr:
+ tcg_out_op_r(s, opc, args[0]);
+ break;
+
case INDEX_op_br:
tcg_out_op_l(s, opc, arg_label(args[0]));
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 16/27] tcg/tci: Implement goto_ptr
2021-06-01 15:00 ` [PATCH v7 16/27] tcg/tci: Implement goto_ptr Richard Henderson
@ 2021-06-12 9:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-12 9:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> This operation is critical to staying within the interpretation
> loop longer, which avoids the overhead of setup and teardown for
> many TBs.
>
> The check in tcg_prologue_init is disabled because TCI does
> want to use NULL to indicate exit, as opposed to branching to
> a real epilogue.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci/tcg-target-con-set.h | 1 +
> tcg/tci/tcg-target.h | 2 +-
> tcg/tcg.c | 2 ++
> tcg/tci.c | 19 +++++++++++++++++++
> tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++
> 5 files changed, 39 insertions(+), 1 deletion(-)
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index c8e6dfb845..3d856371a1 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1353,10 +1353,12 @@ void tcg_prologue_init(TCGContext *s)
> }
> #endif
>
> +#ifndef CONFIG_TCG_INTERPRETER
> /* Assert that goto_ptr is implemented completely. */
Maybe expand the comment briefly explaining the TCI case?
Otherwise:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> if (TCG_TARGET_HAS_goto_ptr) {
> tcg_debug_assert(tcg_code_gen_epilogue != NULL);
> }
> +#endif
> }
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 17/27] tcg/tci: Implement movcond
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (15 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 16/27] tcg/tci: Implement goto_ptr Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 18/27] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
` (11 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
When this opcode is not available in the backend, tcg middle-end
will expand this as a series of 5 opcodes. So implementing this
saves bytecode space.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c | 16 +++++++++++++++-
tcg/tci/tcg-target.c.inc | 10 +++++++---
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 17911d3297..f53773a555 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -82,7 +82,7 @@
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
@@ -119,7 +119,7 @@
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
diff --git a/tcg/tci.c b/tcg/tci.c
index 3636b03adf..1f4f52bac8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -171,6 +171,7 @@ static void tci_args_rrrr(uint32_t insn,
*r2 = extract32(insn, 16, 4);
*r3 = extract32(insn, 20, 4);
}
+#endif
static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
@@ -183,6 +184,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
*c5 = extract32(insn, 28, 4);
}
+#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
@@ -420,6 +422,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
break;
+ case INDEX_op_movcond_i32:
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
+ tmp32 = tci_compare32(regs[r1], regs[r2], condition);
+ regs[r0] = regs[tmp32 ? r3 : r4];
+ break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
@@ -432,6 +439,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
break;
+ case INDEX_op_movcond_i64:
+ tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
+ tmp32 = tci_compare64(regs[r1], regs[r2], condition);
+ regs[r0] = regs[tmp32 ? r3 : r4];
+ break;
#endif
CASE_32_64(mov)
tci_args_rr(insn, &r0, &r1);
@@ -1137,7 +1149,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
-#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
@@ -1145,6 +1158,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r3), str_r(r4), str_c(c));
break;
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 01a8e20c5d..e7a07c1811 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O0_I4(r, r, r, r);
case INDEX_op_mulu2_i32:
return C_O2_I2(r, r, r, r);
+#endif
+
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
return C_O1_I4(r, r, r, r, r);
-#endif
case INDEX_op_qemu_ld_i32:
return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
@@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 20, 4, r3);
tcg_out32(s, insn);
}
+#endif
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
@@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
+#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
@@ -589,12 +594,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]);
break;
-#if TCG_TARGET_REG_BITS == 32
+ CASE_32_64(movcond)
case INDEX_op_setcond2_i32:
tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2],
args[3], args[4], args[5]);
break;
-#endif
CASE_32_64(ld8u)
CASE_32_64(ld8s)
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 18/27] tcg/tci: Implement andc, orc, eqv, nand, nor
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (16 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 17/27] tcg/tci: Implement movcond Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 19/27] tcg/tci: Implement extract, sextract Richard Henderson
` (10 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
These were already present in tcg-target.c.inc,
but not in the interpreter.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 20 ++++++++++----------
tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index f53773a555..5945272a43 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -67,20 +67,20 @@
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
-#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_nor_i32 0
+#define TCG_TARGET_HAS_eqv_i32 1
+#define TCG_TARGET_HAS_nand_i32 1
+#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_orc_i32 0
+#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_muls2_i32 0
@@ -108,16 +108,16 @@
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
-#define TCG_TARGET_HAS_nand_i64 0
-#define TCG_TARGET_HAS_nor_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_eqv_i64 1
+#define TCG_TARGET_HAS_nand_i64 1
+#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 0
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_orc_i64 0
+#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
diff --git a/tcg/tci.c b/tcg/tci.c
index 1f4f52bac8..068ee8f1f4 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -529,6 +529,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
+#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
+ CASE_32_64(andc)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] & ~regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
+ CASE_32_64(orc)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] | ~regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
+ CASE_32_64(eqv)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] ^ regs[r2]);
+ break;
+#endif
+#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
+ CASE_32_64(nand)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] & regs[r2]);
+ break;
+#endif
+#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
+ CASE_32_64(nor)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] | regs[r2]);
+ break;
+#endif
/* Arithmetic operations (32 bit). */
@@ -1119,6 +1149,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
case INDEX_op_div_i32:
case INDEX_op_div_i64:
case INDEX_op_rem_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 19/27] tcg/tci: Implement extract, sextract
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (17 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 18/27] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:00 ` [PATCH v7 20/27] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
` (9 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 5945272a43..60b67b196b 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -69,8 +69,8 @@
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
-#define TCG_TARGET_HAS_extract_i32 0
-#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@@ -97,8 +97,8 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
-#define TCG_TARGET_HAS_extract_i64 0
-#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 068ee8f1f4..22ee32bc24 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -124,6 +124,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
*i2 = sextract32(insn, 16, 16);
}
+static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
+ uint8_t *i2, uint8_t *i3)
+{
+ *r0 = extract32(insn, 8, 4);
+ *r1 = extract32(insn, 12, 4);
+ *i2 = extract32(insn, 16, 6);
+ *i3 = extract32(insn, 22, 6);
+}
+
static void tci_args_rrrc(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -608,6 +617,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
break;
+#endif
+#if TCG_TARGET_HAS_extract_i32
+ case INDEX_op_extract_i32:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = extract32(regs[r1], pos, len);
+ break;
+#endif
+#if TCG_TARGET_HAS_sextract_i32
+ case INDEX_op_sextract_i32:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = sextract32(regs[r1], pos, len);
+ break;
#endif
case INDEX_op_brcond_i32:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
@@ -748,6 +769,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
break;
+#endif
+#if TCG_TARGET_HAS_extract_i64
+ case INDEX_op_extract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = extract64(regs[r1], pos, len);
+ break;
+#endif
+#if TCG_TARGET_HAS_sextract_i64
+ case INDEX_op_sextract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ regs[r0] = sextract64(regs[r1], pos, len);
+ break;
#endif
case INDEX_op_brcond_i64:
tci_args_rl(insn, tb_ptr, &r0, &ptr);
@@ -1189,6 +1222,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
break;
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
+ tci_args_rrbb(insn, &r0, &r1, &pos, &len);
+ info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
+ op_name, str_r(r0), str_r(r1), pos, len);
+ break;
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e7a07c1811..677ae2dceb 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
@@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
+static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
+ TCGReg r1, uint8_t b2, uint8_t b3)
+{
+ tcg_insn_unit insn = 0;
+
+ tcg_debug_assert(b2 == extract32(b2, 0, 6));
+ tcg_debug_assert(b3 == extract32(b3, 0, 6));
+ insn = deposit32(insn, 0, 8, op);
+ insn = deposit32(insn, 8, 4, r0);
+ insn = deposit32(insn, 12, 4, r1);
+ insn = deposit32(insn, 16, 6, b2);
+ insn = deposit32(insn, 22, 6, b3);
+ tcg_out32(s, insn);
+}
+
static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
{
@@ -651,6 +670,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */
+ CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
+ {
+ TCGArg pos = args[2], len = args[3];
+ TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32;
+
+ tcg_debug_assert(pos < max);
+ tcg_debug_assert(pos + len <= max);
+
+ tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len);
+ }
+ break;
+
CASE_32_64(brcond)
tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
? INDEX_op_setcond_i32 : INDEX_op_setcond_i64),
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 20/27] tcg/tci: Implement clz, ctz, ctpop
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (18 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 19/27] tcg/tci: Implement extract, sextract Richard Henderson
@ 2021-06-01 15:00 ` Richard Henderson
2021-06-01 15:01 ` [PATCH v7 21/27] tcg/tci: Implement mulu2, muls2 Richard Henderson
` (8 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 12 +++++------
tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c.inc | 9 ++++++++
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 60b67b196b..59859bd8a6 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -75,9 +75,9 @@
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
-#define TCG_TARGET_HAS_clz_i32 0
-#define TCG_TARGET_HAS_ctz_i32 0
-#define TCG_TARGET_HAS_ctpop_i32 0
+#define TCG_TARGET_HAS_clz_i32 1
+#define TCG_TARGET_HAS_ctz_i32 1
+#define TCG_TARGET_HAS_ctpop_i32 1
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_orc_i32 1
@@ -112,9 +112,9 @@
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
-#define TCG_TARGET_HAS_clz_i64 0
-#define TCG_TARGET_HAS_ctz_i64 0
-#define TCG_TARGET_HAS_ctpop_i64 0
+#define TCG_TARGET_HAS_clz_i64 1
+#define TCG_TARGET_HAS_ctz_i64 1
+#define TCG_TARGET_HAS_ctpop_i64 1
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_orc_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 22ee32bc24..1e2737e079 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -587,6 +587,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
+#if TCG_TARGET_HAS_clz_i32
+ case INDEX_op_clz_i32:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ tmp32 = regs[r1];
+ regs[r0] = tmp32 ? clz32(tmp32) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctz_i32
+ case INDEX_op_ctz_i32:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ tmp32 = regs[r1];
+ regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctpop_i32
+ case INDEX_op_ctpop_i32:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = ctpop32(regs[r1]);
+ break;
+#endif
/* Shift/rotate operations (32 bit). */
@@ -739,6 +759,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
+#if TCG_TARGET_HAS_clz_i64
+ case INDEX_op_clz_i64:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctz_i64
+ case INDEX_op_ctz_i64:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_ctpop_i64
+ case INDEX_op_ctpop_i64:
+ tci_args_rr(insn, &r0, &r1);
+ regs[r0] = ctpop64(regs[r1]);
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1165,6 +1203,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_not_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s",
op_name, str_r(r0), str_r(r1));
@@ -1210,6 +1250,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2));
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 677ae2dceb..748bc13d4e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
@@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_setcond_i64:
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
return C_O1_I2(r, r, r);
case INDEX_op_brcond_i32:
@@ -655,6 +661,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
+ CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */
+ CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */
tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
break;
@@ -703,6 +711,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
+ CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 21/27] tcg/tci: Implement mulu2, muls2
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (19 preceding siblings ...)
2021-06-01 15:00 ` [PATCH v7 20/27] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-01 15:01 ` [PATCH v7 22/27] tcg/tci: Implement add2, sub2 Richard Henderson
` (7 subsequent siblings)
28 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit
hosts as well. The muls2_i32 and the 64-bit opcodes are new.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 35 +++++++++++++++++++++++++++++------
tcg/tci/tcg-target.c.inc | 16 ++++++++++------
3 files changed, 43 insertions(+), 16 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 59859bd8a6..71a44bbfb0 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -83,7 +83,7 @@
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_muls2_i32 0
+#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_goto_ptr 1
@@ -120,13 +120,13 @@
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
-#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muls2_i64 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
-#define TCG_TARGET_HAS_mulu2_i32 0
+#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
-#define TCG_TARGET_HAS_mulu2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#else
diff --git a/tcg/tci.c b/tcg/tci.c
index 1e2737e079..811af1e618 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -39,7 +39,7 @@ __thread uintptr_t tci_tb_ptr;
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
{
- regs[low_index] = value;
+ regs[low_index] = (uint32_t)value;
regs[high_index] = value >> 32;
}
@@ -171,7 +171,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
*r4 = extract32(insn, 24, 4);
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrr(uint32_t insn,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
{
@@ -180,7 +179,6 @@ static void tci_args_rrrr(uint32_t insn,
*r2 = extract32(insn, 16, 4);
*r3 = extract32(insn, 20, 4);
}
-#endif
static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
@@ -669,11 +667,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
+#endif /* TCG_TARGET_REG_BITS == 32 */
+#if TCG_TARGET_HAS_mulu2_i32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
- tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
+ tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3];
+ tci_write_reg64(regs, r1, r0, tmp64);
break;
-#endif /* TCG_TARGET_REG_BITS == 32 */
+#endif
+#if TCG_TARGET_HAS_muls2_i32
+ case INDEX_op_muls2_i32:
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3];
+ tci_write_reg64(regs, r1, r0, tmp64);
+ break;
+#endif
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
tci_args_rr(insn, &r0, &r1);
@@ -777,6 +785,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
regs[r0] = ctpop64(regs[r1]);
break;
#endif
+#if TCG_TARGET_HAS_mulu2_i64
+ case INDEX_op_mulu2_i64:
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]);
+ break;
+#endif
+#if TCG_TARGET_HAS_muls2_i64
+ case INDEX_op_muls2_i64:
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1284,14 +1304,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r3), str_r(r4), str_c(c));
break;
-#if TCG_TARGET_REG_BITS == 32
case INDEX_op_mulu2_i32:
+ case INDEX_op_mulu2_i64:
+ case INDEX_op_muls2_i32:
+ case INDEX_op_muls2_i64:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1),
str_r(r2), str_r(r3));
break;
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 748bc13d4e..e617c46366 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O2_I4(r, r, r, r, r, r);
case INDEX_op_brcond2_i32:
return C_O0_I4(r, r, r, r);
- case INDEX_op_mulu2_i32:
- return C_O2_I2(r, r, r, r);
#endif
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_mulu2_i64:
+ case INDEX_op_muls2_i32:
+ case INDEX_op_muls2_i64:
+ return C_O2_I2(r, r, r, r);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
case INDEX_op_setcond2_i32:
@@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0,
tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
{
@@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 20, 4, r3);
tcg_out32(s, insn);
}
-#endif
static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
@@ -726,10 +728,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
args[0], args[1], args[2], args[3], args[4]);
tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5]));
break;
- case INDEX_op_mulu2_i32:
+#endif
+
+ CASE_32_64(mulu2)
+ CASE_32_64(muls2)
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
break;
-#endif
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_st_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 22/27] tcg/tci: Implement add2, sub2
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (20 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 21/27] tcg/tci: Implement mulu2, muls2 Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-12 9:36 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
` (6 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
We already had the 32-bit versions for a 32-bit host; expand this
to 64-bit hosts as well. The 64-bit opcodes are new.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 8 ++++----
tcg/tci.c | 40 ++++++++++++++++++++++++++--------------
tcg/tci/tcg-target.c.inc | 15 ++++++++-------
3 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 71a44bbfb0..515b3c7a56 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -121,11 +121,11 @@
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
-#define TCG_TARGET_HAS_add2_i32 0
-#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_add2_i32 1
+#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
-#define TCG_TARGET_HAS_add2_i64 0
-#define TCG_TARGET_HAS_sub2_i64 0
+#define TCG_TARGET_HAS_add2_i64 1
+#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
diff --git a/tcg/tci.c b/tcg/tci.c
index 811af1e618..eb9b1ab463 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -191,7 +191,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
*c5 = extract32(insn, 28, 4);
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
{
@@ -202,7 +201,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
*r4 = extract32(insn, 24, 4);
*r5 = extract32(insn, 28, 4);
}
-#endif
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
@@ -353,17 +351,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
for (;;) {
uint32_t insn;
TCGOpcode opc;
- TCGReg r0, r1, r2, r3, r4;
+ TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
uint8_t pos, len;
uint32_t tmp32;
uint64_t tmp64;
-#if TCG_TARGET_REG_BITS == 32
- TCGReg r5;
uint64_t T1, T2;
-#endif
TCGMemOpIdx oi;
int32_t ofs;
void *ptr;
@@ -654,20 +649,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tb_ptr = ptr;
}
break;
-#if TCG_TARGET_REG_BITS == 32
+#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
case INDEX_op_add2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 + T2);
break;
+#endif
+#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
case INDEX_op_sub2_i32:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
T1 = tci_uint64(regs[r3], regs[r2]);
T2 = tci_uint64(regs[r5], regs[r4]);
tci_write_reg64(regs, r1, r0, T1 - T2);
break;
-#endif /* TCG_TARGET_REG_BITS == 32 */
+#endif
#if TCG_TARGET_HAS_mulu2_i32
case INDEX_op_mulu2_i32:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
@@ -797,6 +794,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
break;
#endif
+#if TCG_TARGET_HAS_add2_i64
+ case INDEX_op_add2_i64:
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = regs[r2] + regs[r4];
+ T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
+ regs[r0] = T1;
+ regs[r1] = T2;
+ break;
+#endif
+#if TCG_TARGET_HAS_add2_i64
+ case INDEX_op_sub2_i64:
+ tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
+ T1 = regs[r2] - regs[r4];
+ T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
+ regs[r0] = T1;
+ regs[r1] = T2;
+ break;
+#endif
/* Shift/rotate operations (64 bit). */
@@ -1113,10 +1128,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
const char *op_name;
uint32_t insn;
TCGOpcode op;
- TCGReg r0, r1, r2, r3, r4;
-#if TCG_TARGET_REG_BITS == 32
- TCGReg r5;
-#endif
+ TCGReg r0, r1, r2, r3, r4, r5;
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
@@ -1314,15 +1326,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
str_r(r2), str_r(r3));
break;
-#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2),
str_r(r3), str_r(r4), str_r(r5));
break;
-#endif
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index e617c46366..bb04c326e8 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_brcond_i64:
return C_O0_I2(r, r);
-#if TCG_TARGET_REG_BITS == 32
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
return C_O2_I4(r, r, r, r, r, r);
+
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
return C_O0_I4(r, r, r, r);
#endif
@@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 32
static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
TCGReg r0, TCGReg r1, TCGReg r2,
TCGReg r3, TCGReg r4, TCGReg r5)
@@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op,
insn = deposit32(insn, 28, 4, r5);
tcg_out32(s, insn);
}
-#endif
static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val,
TCGReg base, intptr_t offset)
@@ -717,12 +717,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
+ CASE_32_64(add2)
+ CASE_32_64(sub2)
tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
args[3], args[4], args[5]);
break;
+
+#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP,
args[0], args[1], args[2], args[3], args[4]);
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 22/27] tcg/tci: Implement add2, sub2
2021-06-01 15:01 ` [PATCH v7 22/27] tcg/tci: Implement add2, sub2 Richard Henderson
@ 2021-06-12 9:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-12 9:36 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:01 PM, Richard Henderson wrote:
> We already had the 32-bit versions for a 32-bit host; expand this
> to 64-bit hosts as well. The 64-bit opcodes are new.
>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci/tcg-target.h | 8 ++++----
> tcg/tci.c | 40 ++++++++++++++++++++++++++--------------
> tcg/tci/tcg-target.c.inc | 15 ++++++++-------
> 3 files changed, 38 insertions(+), 25 deletions(-)
> +#if TCG_TARGET_HAS_add2_i64
> + case INDEX_op_add2_i64:
> + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
> + T1 = regs[r2] + regs[r4];
// lo
> + T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
// hi + lo ovf
> + regs[r0] = T1;
// lo
> + regs[r1] = T2;
// hi
OK.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> + break;
> +#endif
> +#if TCG_TARGET_HAS_add2_i64
> + case INDEX_op_sub2_i64:
> + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
> + T1 = regs[r2] - regs[r4];
> + T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
> + regs[r0] = T1;
> + regs[r1] = T2;
> + break;
> +#endif
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (21 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 22/27] tcg/tci: Implement add2, sub2 Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-02 18:01 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
` (5 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel
We can share this code between 32-bit and 64-bit loads and stores.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 183 +++++++++++++++++++++---------------------------------
1 file changed, 71 insertions(+), 112 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index eb9b1ab463..36558210a1 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -315,6 +315,73 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
#define qemu_st_beq(X) \
cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+
+ switch (mop) {
+ case MO_UB:
+ return qemu_ld_ub;
+ case MO_SB:
+ return (int8_t)qemu_ld_ub;
+ case MO_LEUW:
+ return qemu_ld_leuw;
+ case MO_LESW:
+ return (int16_t)qemu_ld_leuw;
+ case MO_LEUL:
+ return qemu_ld_leul;
+ case MO_LESL:
+ return (int32_t)qemu_ld_leul;
+ case MO_LEQ:
+ return qemu_ld_leq;
+ case MO_BEUW:
+ return qemu_ld_beuw;
+ case MO_BESW:
+ return (int16_t)qemu_ld_beuw;
+ case MO_BEUL:
+ return qemu_ld_beul;
+ case MO_BESL:
+ return (int32_t)qemu_ld_beul;
+ case MO_BEQ:
+ return qemu_ld_beq;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+
+ switch (mop) {
+ case MO_UB:
+ qemu_st_b(val);
+ break;
+ case MO_LEUW:
+ qemu_st_lew(val);
+ break;
+ case MO_LEUL:
+ qemu_st_lel(val);
+ break;
+ case MO_LEQ:
+ qemu_st_leq(val);
+ break;
+ case MO_BEUW:
+ qemu_st_bew(val);
+ break;
+ case MO_BEUL:
+ qemu_st_bel(val);
+ break;
+ case MO_BEQ:
+ qemu_st_beq(val);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
#if TCG_TARGET_REG_BITS == 64
# define CASE_32_64(x) \
case glue(glue(INDEX_op_, x), _i64): \
@@ -907,34 +974,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp32 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp32 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp32 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp32 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp32 = qemu_ld_leul;
- break;
- case MO_BEUW:
- tmp32 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp32 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp32 = qemu_ld_beul;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
regs[r0] = tmp32;
break;
@@ -950,46 +990,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r3], regs[r2]);
oi = regs[r4];
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp64 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp64 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp64 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp64 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp64 = qemu_ld_leul;
- break;
- case MO_LESL:
- tmp64 = (int32_t)qemu_ld_leul;
- break;
- case MO_LEQ:
- tmp64 = qemu_ld_leq;
- break;
- case MO_BEUW:
- tmp64 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp64 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp64 = qemu_ld_beul;
- break;
- case MO_BESL:
- tmp64 = (int32_t)qemu_ld_beul;
- break;
- case MO_BEQ:
- tmp64 = qemu_ld_beq;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg64(regs, r1, r0, tmp64);
} else {
@@ -1006,25 +1007,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp32);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp32);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp32);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp32);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp32);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
break;
case INDEX_op_qemu_st_i64:
@@ -1043,31 +1026,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp64);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp64);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp64);
- break;
- case MO_LEQ:
- qemu_st_leq(tmp64);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp64);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp64);
- break;
- case MO_BEQ:
- qemu_st_beq(tmp64);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
break;
case INDEX_op_mb:
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces"
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (22 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-12 9:24 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
` (4 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel
This reverts commit dc09f047eddec8f4a1991c4f5f4a428d7aa3f2c0.
For tcg, tracepoints are expanded inline in tcg opcodes.
Using a helper which generates a second tracepoint is incorrect.
For system mode, the extraction and re-packing of MemOp and mmu_idx
lost the alignment information from MemOp. So we were no longer
raising alignment exceptions for !TARGET_ALIGNED_ONLY guests.
This can be seen in tests/tcg/xtensa/test_load_store.S.
For user mode, we must update to the new signature of g2h() so that
the revert compiles. We can leave set_helper_retaddr for later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 73 ++++++++++++++++++++++++++++++++++---------------------
1 file changed, 45 insertions(+), 28 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 36558210a1..8b17b244bf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -286,34 +286,51 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
return result;
}
-#define qemu_ld_ub \
- cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_leuw \
- cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_leul \
- cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_leq \
- cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_beuw \
- cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_beul \
- cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_ld_beq \
- cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_b(X) \
- cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_lew(X) \
- cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_lel(X) \
- cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_leq(X) \
- cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_bew(X) \
- cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_bel(X) \
- cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
-#define qemu_st_beq(X) \
- cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+#ifdef CONFIG_SOFTMMU
+# define qemu_ld_ub \
+ helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_ld_leuw \
+ helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_ld_leul \
+ helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_ld_leq \
+ helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_ld_beuw \
+ helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_ld_beul \
+ helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_ld_beq \
+ helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
+# define qemu_st_b(X) \
+ helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+# define qemu_st_lew(X) \
+ helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+# define qemu_st_lel(X) \
+ helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+# define qemu_st_leq(X) \
+ helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+# define qemu_st_bew(X) \
+ helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+# define qemu_st_bel(X) \
+ helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+# define qemu_st_beq(X) \
+ helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
+#else
+# define qemu_ld_ub ldub_p(g2h(env_cpu(env), taddr))
+# define qemu_ld_leuw lduw_le_p(g2h(env_cpu(env), taddr))
+# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(env_cpu(env), taddr))
+# define qemu_ld_leq ldq_le_p(g2h(env_cpu(env), taddr))
+# define qemu_ld_beuw lduw_be_p(g2h(env_cpu(env), taddr))
+# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(env_cpu(env), taddr))
+# define qemu_ld_beq ldq_be_p(g2h(env_cpu(env), taddr))
+# define qemu_st_b(X) stb_p(g2h(env_cpu(env), taddr), X)
+# define qemu_st_lew(X) stw_le_p(g2h(env_cpu(env), taddr), X)
+# define qemu_st_lel(X) stl_le_p(g2h(env_cpu(env), taddr), X)
+# define qemu_st_leq(X) stq_le_p(g2h(env_cpu(env), taddr), X)
+# define qemu_st_bew(X) stw_be_p(g2h(env_cpu(env), taddr), X)
+# define qemu_st_bel(X) stl_be_p(g2h(env_cpu(env), taddr), X)
+# define qemu_st_beq(X) stq_be_p(g2h(env_cpu(env), taddr), X)
+#endif
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
TCGMemOpIdx oi, const void *tb_ptr)
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces"
2021-06-01 15:01 ` [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
@ 2021-06-12 9:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-12 9:24 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:01 PM, Richard Henderson wrote:
> This reverts commit dc09f047eddec8f4a1991c4f5f4a428d7aa3f2c0.
>
> For tcg, tracepoints are expanded inline in tcg opcodes.
> Using a helper which generates a second tracepoint is incorrect.
>
> For system mode, the extraction and re-packing of MemOp and mmu_idx
> lost the alignment information from MemOp. So we were no longer
> raising alignment exceptions for !TARGET_ALIGNED_ONLY guests.
> This can be seen in tests/tcg/xtensa/test_load_store.S.
>
> For user mode, we must update to the new signature of g2h() so that
> the revert compiles. We can leave set_helper_retaddr for later.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 73 ++++++++++++++++++++++++++++++++++---------------------
> 1 file changed, 45 insertions(+), 28 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (23 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-02 18:03 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
` (3 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel
These macros are only used in one place. By expanding,
we get to apply some common-subexpression elimination
and create some local variables.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 165 +++++++++++++++++++++++++++++++++---------------------
1 file changed, 100 insertions(+), 65 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 8b17b244bf..11219fec18 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -286,85 +286,88 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
return result;
}
-#ifdef CONFIG_SOFTMMU
-# define qemu_ld_ub \
- helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_leuw \
- helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_leul \
- helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_leq \
- helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_beuw \
- helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_beul \
- helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_ld_beq \
- helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
-# define qemu_st_b(X) \
- helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_lew(X) \
- helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_lel(X) \
- helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_leq(X) \
- helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_bew(X) \
- helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_bel(X) \
- helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-# define qemu_st_beq(X) \
- helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
-#else
-# define qemu_ld_ub ldub_p(g2h(env_cpu(env), taddr))
-# define qemu_ld_leuw lduw_le_p(g2h(env_cpu(env), taddr))
-# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(env_cpu(env), taddr))
-# define qemu_ld_leq ldq_le_p(g2h(env_cpu(env), taddr))
-# define qemu_ld_beuw lduw_be_p(g2h(env_cpu(env), taddr))
-# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(env_cpu(env), taddr))
-# define qemu_ld_beq ldq_be_p(g2h(env_cpu(env), taddr))
-# define qemu_st_b(X) stb_p(g2h(env_cpu(env), taddr), X)
-# define qemu_st_lew(X) stw_le_p(g2h(env_cpu(env), taddr), X)
-# define qemu_st_lel(X) stl_le_p(g2h(env_cpu(env), taddr), X)
-# define qemu_st_leq(X) stq_le_p(g2h(env_cpu(env), taddr), X)
-# define qemu_st_bew(X) stw_be_p(g2h(env_cpu(env), taddr), X)
-# define qemu_st_bel(X) stl_be_p(g2h(env_cpu(env), taddr), X)
-# define qemu_st_beq(X) stq_be_p(g2h(env_cpu(env), taddr), X)
-#endif
-
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
TCGMemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+#ifdef CONFIG_SOFTMMU
+ uintptr_t ra = (uintptr_t)tb_ptr;
+
switch (mop) {
case MO_UB:
- return qemu_ld_ub;
+ return helper_ret_ldub_mmu(env, taddr, oi, ra);
case MO_SB:
- return (int8_t)qemu_ld_ub;
+ return helper_ret_ldsb_mmu(env, taddr, oi, ra);
case MO_LEUW:
- return qemu_ld_leuw;
+ return helper_le_lduw_mmu(env, taddr, oi, ra);
case MO_LESW:
- return (int16_t)qemu_ld_leuw;
+ return helper_le_ldsw_mmu(env, taddr, oi, ra);
case MO_LEUL:
- return qemu_ld_leul;
+ return helper_le_ldul_mmu(env, taddr, oi, ra);
case MO_LESL:
- return (int32_t)qemu_ld_leul;
+ return helper_le_ldsl_mmu(env, taddr, oi, ra);
case MO_LEQ:
- return qemu_ld_leq;
+ return helper_le_ldq_mmu(env, taddr, oi, ra);
case MO_BEUW:
- return qemu_ld_beuw;
+ return helper_be_lduw_mmu(env, taddr, oi, ra);
case MO_BESW:
- return (int16_t)qemu_ld_beuw;
+ return helper_be_ldsw_mmu(env, taddr, oi, ra);
case MO_BEUL:
- return qemu_ld_beul;
+ return helper_be_ldul_mmu(env, taddr, oi, ra);
case MO_BESL:
- return (int32_t)qemu_ld_beul;
+ return helper_be_ldsl_mmu(env, taddr, oi, ra);
case MO_BEQ:
- return qemu_ld_beq;
+ return helper_be_ldq_mmu(env, taddr, oi, ra);
default:
g_assert_not_reached();
}
+#else
+ void *haddr = g2h(env_cpu(env), taddr);
+ uint64_t ret;
+
+ switch (mop) {
+ case MO_UB:
+ ret = ldub_p(haddr);
+ break;
+ case MO_SB:
+ ret = ldsb_p(haddr);
+ break;
+ case MO_LEUW:
+ ret = lduw_le_p(haddr);
+ break;
+ case MO_LESW:
+ ret = ldsw_le_p(haddr);
+ break;
+ case MO_LEUL:
+ ret = (uint32_t)ldl_le_p(haddr);
+ break;
+ case MO_LESL:
+ ret = (int32_t)ldl_le_p(haddr);
+ break;
+ case MO_LEQ:
+ ret = ldq_le_p(haddr);
+ break;
+ case MO_BEUW:
+ ret = lduw_be_p(haddr);
+ break;
+ case MO_BESW:
+ ret = ldsw_be_p(haddr);
+ break;
+ case MO_BEUL:
+ ret = (uint32_t)ldl_be_p(haddr);
+ break;
+ case MO_BESL:
+ ret = (int32_t)ldl_be_p(haddr);
+ break;
+ case MO_BEQ:
+ ret = ldq_be_p(haddr);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return ret;
+#endif
}
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
@@ -372,31 +375,63 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+#ifdef CONFIG_SOFTMMU
+ uintptr_t ra = (uintptr_t)tb_ptr;
+
switch (mop) {
case MO_UB:
- qemu_st_b(val);
+ helper_ret_stb_mmu(env, taddr, val, oi, ra);
break;
case MO_LEUW:
- qemu_st_lew(val);
+ helper_le_stw_mmu(env, taddr, val, oi, ra);
break;
case MO_LEUL:
- qemu_st_lel(val);
+ helper_le_stl_mmu(env, taddr, val, oi, ra);
break;
case MO_LEQ:
- qemu_st_leq(val);
+ helper_le_stq_mmu(env, taddr, val, oi, ra);
break;
case MO_BEUW:
- qemu_st_bew(val);
+ helper_be_stw_mmu(env, taddr, val, oi, ra);
break;
case MO_BEUL:
- qemu_st_bel(val);
+ helper_be_stl_mmu(env, taddr, val, oi, ra);
break;
case MO_BEQ:
- qemu_st_beq(val);
+ helper_be_stq_mmu(env, taddr, val, oi, ra);
break;
default:
g_assert_not_reached();
}
+#else
+ void *haddr = g2h(env_cpu(env), taddr);
+
+ switch (mop) {
+ case MO_UB:
+ stb_p(haddr, val);
+ break;
+ case MO_LEUW:
+ stw_le_p(haddr, val);
+ break;
+ case MO_LEUL:
+ stl_le_p(haddr, val);
+ break;
+ case MO_LEQ:
+ stq_le_p(haddr, val);
+ break;
+ case MO_BEUW:
+ stw_be_p(haddr, val);
+ break;
+ case MO_BEUL:
+ stl_be_p(haddr, val);
+ break;
+ case MO_BEQ:
+ stq_be_p(haddr, val);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
}
#if TCG_TARGET_REG_BITS == 64
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros
2021-06-01 15:01 ` [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
@ 2021-06-02 18:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-02 18:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:01 PM, Richard Henderson wrote:
> These macros are only used in one place. By expanding,
> we get to apply some common-subexpression elimination
> and create some local variables.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 165 +++++++++++++++++++++++++++++++++---------------------
> 1 file changed, 100 insertions(+), 65 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (24 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 25/27] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-12 9:24 ` Philippe Mathieu-Daudé
2021-06-01 15:01 ` [PATCH v7 27/27] tests/tcg: Increase timeout for TCI Richard Henderson
` (2 subsequent siblings)
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel
Wrap guest memory operations for tci like we do for cpu_ld*_data.
We cannot actually use the cpu_ldst.h interface without duplicating
the memory trace operations performed within, which will already
have been expanded into the tcg opcode stream.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 11219fec18..c61eb6b900 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -290,10 +290,9 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
TCGMemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
-
-#ifdef CONFIG_SOFTMMU
uintptr_t ra = (uintptr_t)tb_ptr;
+#ifdef CONFIG_SOFTMMU
switch (mop) {
case MO_UB:
return helper_ret_ldub_mmu(env, taddr, oi, ra);
@@ -326,6 +325,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
void *haddr = g2h(env_cpu(env), taddr);
uint64_t ret;
+ set_helper_retaddr(ra);
switch (mop) {
case MO_UB:
ret = ldub_p(haddr);
@@ -366,6 +366,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
default:
g_assert_not_reached();
}
+ clear_helper_retaddr();
return ret;
#endif
}
@@ -374,10 +375,9 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
TCGMemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
-
-#ifdef CONFIG_SOFTMMU
uintptr_t ra = (uintptr_t)tb_ptr;
+#ifdef CONFIG_SOFTMMU
switch (mop) {
case MO_UB:
helper_ret_stb_mmu(env, taddr, val, oi, ra);
@@ -406,6 +406,7 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
#else
void *haddr = g2h(env_cpu(env), taddr);
+ set_helper_retaddr(ra);
switch (mop) {
case MO_UB:
stb_p(haddr, val);
@@ -431,6 +432,7 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
default:
g_assert_not_reached();
}
+ clear_helper_retaddr();
#endif
}
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr
2021-06-01 15:01 ` [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
@ 2021-06-12 9:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-12 9:24 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:01 PM, Richard Henderson wrote:
> Wrap guest memory operations for tci like we do for cpu_ld*_data.
>
> We cannot actually use the cpu_ldst.h interface without duplicating
> the memory trace operations performed within, which will already
> have been expanded into the tcg opcode stream.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v7 27/27] tests/tcg: Increase timeout for TCI
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (25 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
@ 2021-06-01 15:01 ` Richard Henderson
2021-06-02 9:26 ` Alex Bennée
2021-06-01 15:30 ` [PATCH v7 00/27] TCI fixes and cleanups no-reply
2021-06-19 17:42 ` Philippe Mathieu-Daudé
28 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2021-06-01 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Thomas Huth, Philippe Mathieu-Daudé
The longest test at the moment seems to be a (slower)
aarch64 host, for which test-mmap takes 64 seconds.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configure | 3 +++
tests/tcg/Makefile.target | 6 ++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index 90c0807347..69091ff8ba 100755
--- a/configure
+++ b/configure
@@ -5846,6 +5846,9 @@ fi
if test "$optreset" = "yes" ; then
echo "HAVE_OPTRESET=y" >> $config_host_mak
fi
+if test "$tcg" = "enabled" -a "$tcg_interpreter" = "true" ; then
+ echo "CONFIG_TCG_INTERPRETER=y" >> $config_host_mak
+fi
if test "$fdatasync" = "yes" ; then
echo "CONFIG_FDATASYNC=y" >> $config_host_mak
fi
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index b29fae4630..63cf1b2573 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -81,8 +81,10 @@ LDFLAGS=
QEMU_OPTS=
-# If TCG debugging is enabled things are a lot slower
-ifeq ($(CONFIG_DEBUG_TCG),y)
+# If TCG debugging, or TCI is enabled things are a lot slower
+ifneq ($(CONFIG_TCG_INTERPRETER),)
+TIMEOUT=90
+else ifneq ($(CONFIG_DEBUG_TCG),)
TIMEOUT=60
else
TIMEOUT=15
--
2.25.1
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [PATCH v7 27/27] tests/tcg: Increase timeout for TCI
2021-06-01 15:01 ` [PATCH v7 27/27] tests/tcg: Increase timeout for TCI Richard Henderson
@ 2021-06-02 9:26 ` Alex Bennée
0 siblings, 0 replies; 47+ messages in thread
From: Alex Bennée @ 2021-06-02 9:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Thomas Huth, Philippe Mathieu-Daudé, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> The longest test at the moment seems to be a (slower)
> aarch64 host, for which test-mmap takes 64 seconds.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> configure | 3 +++
> tests/tcg/Makefile.target | 6 ++++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/configure b/configure
> index 90c0807347..69091ff8ba 100755
> --- a/configure
> +++ b/configure
> @@ -5846,6 +5846,9 @@ fi
> if test "$optreset" = "yes" ; then
> echo "HAVE_OPTRESET=y" >> $config_host_mak
> fi
> +if test "$tcg" = "enabled" -a "$tcg_interpreter" = "true" ; then
> + echo "CONFIG_TCG_INTERPRETER=y" >> $config_host_mak
> +fi
> if test "$fdatasync" = "yes" ; then
> echo "CONFIG_FDATASYNC=y" >> $config_host_mak
> fi
> diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
> index b29fae4630..63cf1b2573 100644
> --- a/tests/tcg/Makefile.target
> +++ b/tests/tcg/Makefile.target
> @@ -81,8 +81,10 @@ LDFLAGS=
> QEMU_OPTS=
>
>
> -# If TCG debugging is enabled things are a lot slower
> -ifeq ($(CONFIG_DEBUG_TCG),y)
> +# If TCG debugging, or TCI is enabled things are a lot slower
> +ifneq ($(CONFIG_TCG_INTERPRETER),)
> +TIMEOUT=90
> +else ifneq ($(CONFIG_DEBUG_TCG),)
> TIMEOUT=60
> else
> TIMEOUT=15
Acked-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v7 00/27] TCI fixes and cleanups
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (26 preceding siblings ...)
2021-06-01 15:01 ` [PATCH v7 27/27] tests/tcg: Increase timeout for TCI Richard Henderson
@ 2021-06-01 15:30 ` no-reply
2021-06-19 17:42 ` Philippe Mathieu-Daudé
28 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2021-06-01 15:30 UTC (permalink / raw)
To: richard.henderson; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20210601150106.12761-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210601150106.12761-1-richard.henderson@linaro.org
Subject: [PATCH v7 00/27] TCI fixes and cleanups
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20210601143749.1669-1-anaidu.gollu@samsung.com -> patchew/20210601143749.1669-1-anaidu.gollu@samsung.com
* [new tag] patchew/20210601150106.12761-1-richard.henderson@linaro.org -> patchew/20210601150106.12761-1-richard.henderson@linaro.org
Switched to a new branch 'test'
ff73f2a tests/tcg: Increase timeout for TCI
f786057 tcg/tci: Use {set,clear}_helper_retaddr
190ad1f tcg/tci: Remove the qemu_ld/st_type macros
1e2156a Revert "tcg/tci: Use exec/cpu_ldst.h interfaces"
5500fe7 tcg/tci: Split out tci_qemu_ld, tci_qemu_st
cc70f98 tcg/tci: Implement add2, sub2
fe9d5c6 tcg/tci: Implement mulu2, muls2
2da224a tcg/tci: Implement clz, ctz, ctpop
e4cd4f1 tcg/tci: Implement extract, sextract
e637074 tcg/tci: Implement andc, orc, eqv, nand, nor
fe78aa9 tcg/tci: Implement movcond
4244f97 tcg/tci: Implement goto_ptr
d5129d0 tcg/tci: Change encoding to uint32_t units
b9936ff tcg/tci: Remove tci_write_reg
55ddc15 tcg/tci: Emit setcond before brcond
7d88fcd tcg/tci: Reserve r13 for a temporary
e4d9785 tcg/tci: Use ffi for calls
7c53811 tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
df9f663 tcg/tci: Improve tcg_target_call_clobber_regs
7b199c1 tcg: Build ffi data structures for helpers
4cdaf7c tcg: Add tcg_call_func
b5d0c45 tcg: Store the TCGHelperInfo in the TCGOp for call
998791a accel/tcg: Add tcg call flags to plugins helpers
31812d5 plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb
b12d667 accel/tcg/plugin-gen: Drop inline markers
857f3d7 tcg: Add tcg_call_flags
7507c52 tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
=== OUTPUT BEGIN ===
1/27 Checking commit 7507c521494e (tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode)
2/27 Checking commit 857f3d7ba371 (tcg: Add tcg_call_flags)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#21:
new file mode 100644
total: 0 errors, 1 warnings, 106 lines checked
Patch 2/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/27 Checking commit b12d66702acb (accel/tcg/plugin-gen: Drop inline markers)
4/27 Checking commit 31812d57a48c (plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb)
5/27 Checking commit 998791ad868e (accel/tcg: Add tcg call flags to plugins helpers)
WARNING: line over 80 characters
#27: FILE: accel/tcg/plugin-helpers.h:3:
+DEF_HELPER_FLAGS_4(plugin_vcpu_mem_cb, TCG_CALL_NO_RWG, void, i32, i32, i64, ptr)
total: 0 errors, 1 warnings, 6 lines checked
Patch 5/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/27 Checking commit b5d0c45e0f8b (tcg: Store the TCGHelperInfo in the TCGOp for call)
7/27 Checking commit 4cdaf7c2074a (tcg: Add tcg_call_func)
8/27 Checking commit 7b199c1dd9c5 (tcg: Build ffi data structures for helpers)
9/27 Checking commit df9f6637a168 (tcg/tci: Improve tcg_target_call_clobber_regs)
10/27 Checking commit 7c538119a809 (tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order)
11/27 Checking commit e4d97852d0bf (tcg/tci: Use ffi for calls)
ERROR: suspect code indent for conditional statements (8, 11)
#74: FILE: tcg/tcg.c:2148:
if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
+ /*
total: 1 errors, 0 warnings, 392 lines checked
Patch 11/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/27 Checking commit 7d88fcde0f51 (tcg/tci: Reserve r13 for a temporary)
13/27 Checking commit 55ddc15b0444 (tcg/tci: Emit setcond before brcond)
14/27 Checking commit b9936ff729dd (tcg/tci: Remove tci_write_reg)
15/27 Checking commit d5129d03bd95 (tcg/tci: Change encoding to uint32_t units)
16/27 Checking commit 4244f975b69a (tcg/tci: Implement goto_ptr)
17/27 Checking commit fe78aa960301 (tcg/tci: Implement movcond)
18/27 Checking commit e6370741791a (tcg/tci: Implement andc, orc, eqv, nand, nor)
19/27 Checking commit e4cd4f1ec298 (tcg/tci: Implement extract, sextract)
20/27 Checking commit 2da224ab55ce (tcg/tci: Implement clz, ctz, ctpop)
21/27 Checking commit fe9d5c60a7de (tcg/tci: Implement mulu2, muls2)
22/27 Checking commit cc70f986db4d (tcg/tci: Implement add2, sub2)
23/27 Checking commit 5500fe728bcf (tcg/tci: Split out tci_qemu_ld, tci_qemu_st)
24/27 Checking commit 1e2156aa0738 (Revert "tcg/tci: Use exec/cpu_ldst.h interfaces")
25/27 Checking commit 190ad1f3880e (tcg/tci: Remove the qemu_ld/st_type macros)
26/27 Checking commit f7860570bfc8 (tcg/tci: Use {set,clear}_helper_retaddr)
27/27 Checking commit ff73f2a5fabe (tests/tcg: Increase timeout for TCI)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210601150106.12761-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [PATCH v7 00/27] TCI fixes and cleanups
2021-06-01 15:00 [PATCH v7 00/27] TCI fixes and cleanups Richard Henderson
` (27 preceding siblings ...)
2021-06-01 15:30 ` [PATCH v7 00/27] TCI fixes and cleanups no-reply
@ 2021-06-19 17:42 ` Philippe Mathieu-Daudé
28 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-19 17:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/1/21 5:00 PM, Richard Henderson wrote:
> Richard Henderson (27):
> tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
> tcg: Add tcg_call_flags
> accel/tcg/plugin-gen: Drop inline markers
> plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb
> accel/tcg: Add tcg call flags to plugins helpers
> tcg: Store the TCGHelperInfo in the TCGOp for call
> tcg: Add tcg_call_func
> tcg: Build ffi data structures for helpers
> tcg/tci: Improve tcg_target_call_clobber_regs
> tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
> tcg/tci: Use ffi for calls
> tcg/tci: Reserve r13 for a temporary
> tcg/tci: Emit setcond before brcond
> tcg/tci: Remove tci_write_reg
> tcg/tci: Change encoding to uint32_t units
> tcg/tci: Implement goto_ptr
> tcg/tci: Implement movcond
> tcg/tci: Implement andc, orc, eqv, nand, nor
> tcg/tci: Implement extract, sextract
> tcg/tci: Implement clz, ctz, ctpop
> tcg/tci: Implement mulu2, muls2
> tcg/tci: Implement add2, sub2
> tcg/tci: Split out tci_qemu_ld, tci_qemu_st
> Revert "tcg/tci: Use exec/cpu_ldst.h interfaces"
> tcg/tci: Remove the qemu_ld/st_type macros
> tcg/tci: Use {set,clear}_helper_retaddr
> tests/tcg: Increase timeout for TCI
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 47+ messages in thread