From: Steven Lee <steven_lee@aspeedtech.com> To: Linus Walleij <linus.walleij@linaro.org>, Bartosz Golaszewski <bgolaszewski@baylibre.com>, Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>, "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, "moderated list:ARM/ASPEED MACHINE SUPPORT" <linux-arm-kernel@lists.infradead.org>, "moderated list:ARM/ASPEED MACHINE SUPPORT" <linux-aspeed@lists.ozlabs.org>, open list <linux-kernel@vger.kernel.org> Cc: <steven_lee@aspeedtech.com>, <Hongweiz@ami.com>, <ryan_chen@aspeedtech.com>, <billy_tsai@aspeedtech.com> Subject: [PATCH v3 4/5] gpio: gpio-aspeed-sgpio: Add set_config function Date: Thu, 3 Jun 2021 18:18:20 +0800 [thread overview] Message-ID: <20210603101822.9645-5-steven_lee@aspeedtech.com> (raw) In-Reply-To: <20210603101822.9645-1-steven_lee@aspeedtech.com> AST SoC supports *retain pin state* function when wdt reset. The patch adds set_config function for handling sgpio reset tolerance register. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> --- drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index aa894c92143e..8003308811f7 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -52,9 +52,10 @@ struct aspeed_sgpio { }; struct aspeed_sgpio_bank { - uint16_t val_regs; - uint16_t rdata_reg; - uint16_t irq_regs; + u16 val_regs; + u16 rdata_reg; + u16 irq_regs; + u16 tolerance_regs; const char names[4][3]; }; @@ -70,24 +71,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = { .val_regs = 0x0000, .rdata_reg = 0x0070, .irq_regs = 0x0004, + .tolerance_regs = 0x0018, .names = { "A", "B", "C", "D" }, }, { .val_regs = 0x001C, .rdata_reg = 0x0074, .irq_regs = 0x0020, + .tolerance_regs = 0x0034, .names = { "E", "F", "G", "H" }, }, { .val_regs = 0x0038, .rdata_reg = 0x0078, .irq_regs = 0x003C, + .tolerance_regs = 0x0050, .names = { "I", "J", "K", "L" }, }, { .val_regs = 0x0090, .rdata_reg = 0x007C, .irq_regs = 0x0094, + .tolerance_regs = 0x00A8, .names = { "M", "N", "O", "P" }, }, }; @@ -100,6 +105,7 @@ enum aspeed_sgpio_reg { reg_irq_type1, reg_irq_type2, reg_irq_status, + reg_tolerance, }; #define GPIO_VAL_VALUE 0x00 @@ -128,6 +134,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio, return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; case reg_irq_status: return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; + case reg_tolerance: + return gpio->base + bank->tolerance_regs; default: /* acturally if code runs to here, it's an error case */ BUG(); @@ -484,6 +492,44 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio, return 0; } +static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, + unsigned int offset, bool enable) +{ + struct aspeed_sgpio *gpio = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *reg; + u32 val; + + reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance); + + spin_lock_irqsave(&gpio->lock, flags); + + val = readl(reg); + + if (enable) + val |= GPIO_BIT(offset, gpio); + else + val &= ~GPIO_BIT(offset, gpio); + + writel(val, reg); + + spin_unlock_irqrestore(&gpio->lock, flags); + + return 0; +} + +static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + unsigned long param = pinconf_to_config_param(config); + u32 arg = pinconf_to_config_argument(config); + + if (param == PIN_CONFIG_PERSIST_STATE) + return aspeed_sgpio_reset_tolerance(chip, offset, arg); + else + return -EOPNOTSUPP; +} + static const struct aspeed_sgpio_pdata ast2600_sgpiom1_pdata = { .max_ngpios = 128, .pin_mask = GENMASK(10, 6), @@ -591,7 +637,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev) gpio->chip.free = NULL; gpio->chip.get = aspeed_sgpio_get; gpio->chip.set = aspeed_sgpio_set; - gpio->chip.set_config = NULL; + gpio->chip.set_config = aspeed_sgpio_set_config; gpio->chip.label = dev_name(&pdev->dev); gpio->chip.base = -1; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Steven Lee <steven_lee@aspeedtech.com> To: Linus Walleij <linus.walleij@linaro.org>, Bartosz Golaszewski <bgolaszewski@baylibre.com>, Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>, "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, "moderated list:ARM/ASPEED MACHINE SUPPORT" <linux-arm-kernel@lists.infradead.org>, "moderated list:ARM/ASPEED MACHINE SUPPORT" <linux-aspeed@lists.ozlabs.org>, open list <linux-kernel@vger.kernel.org> Cc: <steven_lee@aspeedtech.com>, <Hongweiz@ami.com>, <ryan_chen@aspeedtech.com>, <billy_tsai@aspeedtech.com> Subject: [PATCH v3 4/5] gpio: gpio-aspeed-sgpio: Add set_config function Date: Thu, 3 Jun 2021 18:18:20 +0800 [thread overview] Message-ID: <20210603101822.9645-5-steven_lee@aspeedtech.com> (raw) In-Reply-To: <20210603101822.9645-1-steven_lee@aspeedtech.com> AST SoC supports *retain pin state* function when wdt reset. The patch adds set_config function for handling sgpio reset tolerance register. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> --- drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index aa894c92143e..8003308811f7 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -52,9 +52,10 @@ struct aspeed_sgpio { }; struct aspeed_sgpio_bank { - uint16_t val_regs; - uint16_t rdata_reg; - uint16_t irq_regs; + u16 val_regs; + u16 rdata_reg; + u16 irq_regs; + u16 tolerance_regs; const char names[4][3]; }; @@ -70,24 +71,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = { .val_regs = 0x0000, .rdata_reg = 0x0070, .irq_regs = 0x0004, + .tolerance_regs = 0x0018, .names = { "A", "B", "C", "D" }, }, { .val_regs = 0x001C, .rdata_reg = 0x0074, .irq_regs = 0x0020, + .tolerance_regs = 0x0034, .names = { "E", "F", "G", "H" }, }, { .val_regs = 0x0038, .rdata_reg = 0x0078, .irq_regs = 0x003C, + .tolerance_regs = 0x0050, .names = { "I", "J", "K", "L" }, }, { .val_regs = 0x0090, .rdata_reg = 0x007C, .irq_regs = 0x0094, + .tolerance_regs = 0x00A8, .names = { "M", "N", "O", "P" }, }, }; @@ -100,6 +105,7 @@ enum aspeed_sgpio_reg { reg_irq_type1, reg_irq_type2, reg_irq_status, + reg_tolerance, }; #define GPIO_VAL_VALUE 0x00 @@ -128,6 +134,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio, return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; case reg_irq_status: return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; + case reg_tolerance: + return gpio->base + bank->tolerance_regs; default: /* acturally if code runs to here, it's an error case */ BUG(); @@ -484,6 +492,44 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio, return 0; } +static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, + unsigned int offset, bool enable) +{ + struct aspeed_sgpio *gpio = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *reg; + u32 val; + + reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance); + + spin_lock_irqsave(&gpio->lock, flags); + + val = readl(reg); + + if (enable) + val |= GPIO_BIT(offset, gpio); + else + val &= ~GPIO_BIT(offset, gpio); + + writel(val, reg); + + spin_unlock_irqrestore(&gpio->lock, flags); + + return 0; +} + +static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + unsigned long param = pinconf_to_config_param(config); + u32 arg = pinconf_to_config_argument(config); + + if (param == PIN_CONFIG_PERSIST_STATE) + return aspeed_sgpio_reset_tolerance(chip, offset, arg); + else + return -EOPNOTSUPP; +} + static const struct aspeed_sgpio_pdata ast2600_sgpiom1_pdata = { .max_ngpios = 128, .pin_mask = GENMASK(10, 6), @@ -591,7 +637,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev) gpio->chip.free = NULL; gpio->chip.get = aspeed_sgpio_get; gpio->chip.set = aspeed_sgpio_set; - gpio->chip.set_config = NULL; + gpio->chip.set_config = aspeed_sgpio_set_config; gpio->chip.label = dev_name(&pdev->dev); gpio->chip.base = -1; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-03 10:19 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-03 10:18 [PATCH v3 0/5] ASPEED sgpio driver enhancement Steven Lee 2021-06-03 10:18 ` Steven Lee 2021-06-03 10:18 ` [PATCH v3 1/5] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee 2021-06-03 10:18 ` Steven Lee 2021-06-03 23:25 ` Andrew Jeffery 2021-06-03 23:25 ` Andrew Jeffery 2021-06-04 3:30 ` Steven Lee 2021-06-04 3:30 ` Steven Lee 2021-06-04 3:40 ` Andrew Jeffery 2021-06-04 3:40 ` Andrew Jeffery 2021-06-09 9:17 ` Linus Walleij 2021-06-09 9:17 ` Linus Walleij 2021-06-03 10:18 ` [PATCH v3 2/5] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee 2021-06-03 10:18 ` Steven Lee 2021-06-03 23:29 ` Andrew Jeffery 2021-06-03 23:29 ` Andrew Jeffery 2021-06-03 10:18 ` [PATCH v3 3/5] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee 2021-06-03 10:18 ` Steven Lee 2021-06-03 11:05 ` Andy Shevchenko 2021-06-03 11:05 ` Andy Shevchenko 2021-06-04 2:08 ` Steven Lee 2021-06-04 2:08 ` Steven Lee 2021-06-04 2:14 ` Steven Lee 2021-06-04 2:14 ` Steven Lee 2021-06-04 10:21 ` Andy Shevchenko 2021-06-04 10:21 ` Andy Shevchenko 2021-06-03 10:18 ` Steven Lee [this message] 2021-06-03 10:18 ` [PATCH v3 4/5] gpio: gpio-aspeed-sgpio: Add set_config function Steven Lee 2021-06-03 11:07 ` Andy Shevchenko 2021-06-03 11:07 ` Andy Shevchenko 2021-06-04 2:18 ` Steven Lee 2021-06-04 2:18 ` Steven Lee 2021-06-03 10:18 ` [PATCH v3 5/5] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct Steven Lee 2021-06-03 10:18 ` Steven Lee 2021-06-03 23:28 ` Andrew Jeffery 2021-06-03 23:28 ` Andrew Jeffery
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210603101822.9645-5-steven_lee@aspeedtech.com \ --to=steven_lee@aspeedtech.com \ --cc=Hongweiz@ami.com \ --cc=andrew@aj.id.au \ --cc=bgolaszewski@baylibre.com \ --cc=billy_tsai@aspeedtech.com \ --cc=devicetree@vger.kernel.org \ --cc=joel@jms.id.au \ --cc=linus.walleij@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-aspeed@lists.ozlabs.org \ --cc=linux-gpio@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=robh+dt@kernel.org \ --cc=ryan_chen@aspeedtech.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.