From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org Cc: Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 10/12] serial: sh-sci: Add support for RZ/G2L SoC Date: Thu, 3 Jun 2021 23:17:56 +0100 [thread overview] Message-ID: <20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20210603221758.10305-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Biju Das <biju.das.jz@bp.renesas.com> Add serial support for RZ/G2L SoC with earlycon and extended mode register support. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/tty/serial/sh-sci.c | 12 +++++++++++- drivers/tty/serial/sh-sci.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ef37fdf37612..798ccd88251f 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -289,7 +289,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { }, /* - * The "SCIFA" that is in RZ/T and RZ/A2. + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. * It looks like a normal SCIF with FIFO data, but with a * compressed address space. Also, the break out of interrupts * are different: ERI/BRI, RXI, TXI, TEI, DRI. @@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { [SCFDR] = { 0x0E, 16 }, [SCSPTR] = { 0x10, 16 }, [SCLSR] = { 0x12, 16 }, + [SEMR] = { 0x14, 8 }, }, .fifosize = 16, .overrun_reg = SCLSR, @@ -2514,6 +2515,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_cflag & PARENB) bits++; + if (sci_getreg(port, SEMR)->size) + serial_port_out(port, SEMR, 0); + if (best_clk >= 0) { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) switch (srr + 1) { @@ -3170,6 +3174,10 @@ static const struct of_device_id of_sci_match[] = { .compatible = "renesas,scif-r7s9210", .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), }, + { + .compatible = "renesas,scif-r9a07g044", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), + }, /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3452,6 +3460,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device, port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; return early_console_setup(device, PORT_SCIF); } + static int __init scifa_early_console_setup(struct earlycon_device *device, const char *opt) { @@ -3471,6 +3480,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device, OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index c0dfe4382898..c0ae78632dda 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -31,6 +31,7 @@ enum { SCCKS, /* BRG Clock Select Register */ HSRTRGR, /* Rx FIFO Data Count Trigger Register */ HSTTRGR, /* Tx FIFO Data Count Trigger Register */ + SEMR, /* Serial extended mode register */ SCIx_NR_REGS, }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org Cc: Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 10/12] serial: sh-sci: Add support for RZ/G2L SoC Date: Thu, 3 Jun 2021 23:17:56 +0100 [thread overview] Message-ID: <20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20210603221758.10305-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Biju Das <biju.das.jz@bp.renesas.com> Add serial support for RZ/G2L SoC with earlycon and extended mode register support. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/tty/serial/sh-sci.c | 12 +++++++++++- drivers/tty/serial/sh-sci.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ef37fdf37612..798ccd88251f 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -289,7 +289,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { }, /* - * The "SCIFA" that is in RZ/T and RZ/A2. + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. * It looks like a normal SCIF with FIFO data, but with a * compressed address space. Also, the break out of interrupts * are different: ERI/BRI, RXI, TXI, TEI, DRI. @@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { [SCFDR] = { 0x0E, 16 }, [SCSPTR] = { 0x10, 16 }, [SCLSR] = { 0x12, 16 }, + [SEMR] = { 0x14, 8 }, }, .fifosize = 16, .overrun_reg = SCLSR, @@ -2514,6 +2515,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_cflag & PARENB) bits++; + if (sci_getreg(port, SEMR)->size) + serial_port_out(port, SEMR, 0); + if (best_clk >= 0) { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) switch (srr + 1) { @@ -3170,6 +3174,10 @@ static const struct of_device_id of_sci_match[] = { .compatible = "renesas,scif-r7s9210", .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), }, + { + .compatible = "renesas,scif-r9a07g044", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), + }, /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3452,6 +3460,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device, port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; return early_console_setup(device, PORT_SCIF); } + static int __init scifa_early_console_setup(struct earlycon_device *device, const char *opt) { @@ -3471,6 +3480,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device, OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index c0dfe4382898..c0ae78632dda 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -31,6 +31,7 @@ enum { SCCKS, /* BRG Clock Select Register */ HSRTRGR, /* Rx FIFO Data Count Trigger Register */ HSTTRGR, /* Tx FIFO Data Count Trigger Register */ + SEMR, /* Serial extended mode register */ SCIx_NR_REGS, }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-03 22:18 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-03 22:17 [PATCH v2 00/12] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-03 22:17 ` [PATCH v2 01/12] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-08 15:23 ` Geert Uytterhoeven 2021-06-08 15:23 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 02/12] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Lad Prabhakar 2021-06-03 22:17 ` [PATCH v2 02/12] dt-bindings: arm: renesas: Document Renesas RZ/G2{L, LC} " Lad Prabhakar 2021-06-08 15:23 ` [PATCH v2 02/12] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} " Geert Uytterhoeven 2021-06-08 15:23 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 03/12] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-08 15:23 ` Geert Uytterhoeven 2021-06-08 15:23 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 04/12] soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-08 15:24 ` Geert Uytterhoeven 2021-06-08 15:24 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 05/12] arm64: defconfig: Enable ARCH_R9A07G044 Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-08 15:24 ` Geert Uytterhoeven 2021-06-08 15:24 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 06/12] clk: renesas: Define RZ/G2L CPG Clock Definitions Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-08 15:24 ` Geert Uytterhoeven 2021-06-08 15:24 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 07/12] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-08 15:08 ` Geert Uytterhoeven 2021-06-08 15:08 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 08/12] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-03 22:17 ` [PATCH v2 09/12] clk: renesas: Add support for R9A07G044 SoC Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar [this message] 2021-06-03 22:17 ` [PATCH v2 10/12] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar 2021-06-08 15:03 ` Geert Uytterhoeven 2021-06-08 15:03 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar 2021-06-03 22:17 ` [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for RZ/G2{L, LC} SoC's Lad Prabhakar 2021-06-04 13:54 ` [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Biju Das 2021-06-04 13:54 ` Biju Das 2021-06-09 7:01 ` Geert Uytterhoeven 2021-06-09 7:01 ` Geert Uytterhoeven 2021-06-09 7:08 ` Biju Das 2021-06-09 7:08 ` Biju Das 2021-06-09 6:52 ` Geert Uytterhoeven 2021-06-09 6:52 ` Geert Uytterhoeven 2021-06-03 22:17 ` [PATCH v2 12/12] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar 2021-06-03 22:17 ` Lad Prabhakar 2021-06-09 7:17 ` Geert Uytterhoeven 2021-06-09 7:17 ` Geert Uytterhoeven 2021-06-09 7:55 ` Lad, Prabhakar 2021-06-09 7:55 ` Lad, Prabhakar 2021-06-07 11:00 ` [PATCH v2 00/12] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad, Prabhakar 2021-06-07 11:00 ` Lad, Prabhakar
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