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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
	qemu-arm@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Claudio Fontana" <cfontana@suse.de>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: [PATCH v16 21/99] target/arm: tcg: split tlb_helper user-only and sysemu-only parts
Date: Fri,  4 Jun 2021 16:51:54 +0100	[thread overview]
Message-ID: <20210604155312.15902-22-alex.bennee@linaro.org> (raw)
In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org>

From: Claudio Fontana <cfontana@suse.de>

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 target/arm/tcg/tlb_helper.h        | 17 ++++++
 target/arm/tcg/sysemu/tlb_helper.c | 83 +++++++++++++++++++++++++
 target/arm/tcg/tlb_helper.c        | 97 ++----------------------------
 target/arm/tcg/user/tlb_helper.c   | 32 ++++++++++
 target/arm/tcg/sysemu/meson.build  |  1 +
 target/arm/tcg/user/meson.build    |  1 +
 6 files changed, 138 insertions(+), 93 deletions(-)
 create mode 100644 target/arm/tcg/tlb_helper.h
 create mode 100644 target/arm/tcg/sysemu/tlb_helper.c
 create mode 100644 target/arm/tcg/user/tlb_helper.c

diff --git a/target/arm/tcg/tlb_helper.h b/target/arm/tcg/tlb_helper.h
new file mode 100644
index 0000000000..6ce3d315cf
--- /dev/null
+++ b/target/arm/tcg/tlb_helper.h
@@ -0,0 +1,17 @@
+/*
+ * ARM TLB (Translation lookaside buffer) helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef TLB_HELPER_H
+#define TLB_HELPER_H
+
+#include "cpu.h"
+
+void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+                                     MMUAccessType access_type,
+                                     int mmu_idx, ARMMMUFaultInfo *fi);
+
+#endif /* TLB_HELPER_H */
diff --git a/target/arm/tcg/sysemu/tlb_helper.c b/target/arm/tcg/sysemu/tlb_helper.c
new file mode 100644
index 0000000000..586f602989
--- /dev/null
+++ b/target/arm/tcg/sysemu/tlb_helper.c
@@ -0,0 +1,83 @@
+/*
+ * ARM TLB (Translation lookaside buffer) helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+#include "exec/exec-all.h"
+#include "tcg/tlb_helper.h"
+
+/*
+ * arm_cpu_do_transaction_failed: handle a memory system error response
+ * (eg "no device/memory present at address") by raising an external abort
+ * exception
+ */
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+                                   vaddr addr, unsigned size,
+                                   MMUAccessType access_type,
+                                   int mmu_idx, MemTxAttrs attrs,
+                                   MemTxResult response, uintptr_t retaddr)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    ARMMMUFaultInfo fi = {};
+
+    /* now we have a real cpu fault */
+    cpu_restore_state(cs, retaddr, true);
+
+    fi.ea = arm_extabort_type(response);
+    fi.type = ARMFault_SyncExternal;
+    arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
+}
+
+bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                      MMUAccessType access_type, int mmu_idx,
+                      bool probe, uintptr_t retaddr)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    ARMMMUFaultInfo fi = {};
+    hwaddr phys_addr;
+    target_ulong page_size;
+    int prot, ret;
+    MemTxAttrs attrs = {};
+    ARMCacheAttrs cacheattrs = {};
+
+    /*
+     * Walk the page table and (if the mapping exists) add the page
+     * to the TLB.  On success, return true.  Otherwise, if probing,
+     * return false.  Otherwise populate fsr with ARM DFSR/IFSR fault
+     * register format, and signal the fault.
+     */
+    ret = get_phys_addr(&cpu->env, address, access_type,
+                        core_to_arm_mmu_idx(&cpu->env, mmu_idx),
+                        &phys_addr, &attrs, &prot, &page_size,
+                        &fi, &cacheattrs);
+    if (likely(!ret)) {
+        /*
+         * Map a single [sub]page. Regions smaller than our declared
+         * target page size are handled specially, so for those we
+         * pass in the exact addresses.
+         */
+        if (page_size >= TARGET_PAGE_SIZE) {
+            phys_addr &= TARGET_PAGE_MASK;
+            address &= TARGET_PAGE_MASK;
+        }
+        /* Notice and record tagged memory. */
+        if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
+            arm_tlb_mte_tagged(&attrs) = true;
+        }
+
+        tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
+                                prot, mmu_idx, page_size);
+        return true;
+    } else if (probe) {
+        return false;
+    } else {
+        /* now we have a real cpu fault */
+        cpu_restore_state(cs, retaddr, true);
+        arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
+    }
+}
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index 3107f9823e..77aefc274d 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -9,6 +9,7 @@
 #include "cpu.h"
 #include "internals.h"
 #include "exec/exec-all.h"
+#include "tcg/tlb_helper.h"
 
 static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
                                             unsigned int target_el,
@@ -49,9 +50,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
     return syn;
 }
 
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
-                                            MMUAccessType access_type,
-                                            int mmu_idx, ARMMMUFaultInfo *fi)
+void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+                                     MMUAccessType access_type,
+                                     int mmu_idx, ARMMMUFaultInfo *fi)
 {
     CPUARMState *env = &cpu->env;
     int target_el;
@@ -122,93 +123,3 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
     fi.type = ARMFault_Alignment;
     arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
 }
-
-#if !defined(CONFIG_USER_ONLY)
-
-/*
- * arm_cpu_do_transaction_failed: handle a memory system error response
- * (eg "no device/memory present at address") by raising an external abort
- * exception
- */
-void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
-                                   vaddr addr, unsigned size,
-                                   MMUAccessType access_type,
-                                   int mmu_idx, MemTxAttrs attrs,
-                                   MemTxResult response, uintptr_t retaddr)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    ARMMMUFaultInfo fi = {};
-
-    /* now we have a real cpu fault */
-    cpu_restore_state(cs, retaddr, true);
-
-    fi.ea = arm_extabort_type(response);
-    fi.type = ARMFault_SyncExternal;
-    arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
-}
-
-#endif /* !defined(CONFIG_USER_ONLY) */
-
-bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                      MMUAccessType access_type, int mmu_idx,
-                      bool probe, uintptr_t retaddr)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    ARMMMUFaultInfo fi = {};
-
-#ifdef CONFIG_USER_ONLY
-    int flags = page_get_flags(useronly_clean_ptr(address));
-    if (flags & PAGE_VALID) {
-        fi.type = ARMFault_Permission;
-    } else {
-        fi.type = ARMFault_Translation;
-    }
-    fi.level = 3;
-
-    /* now we have a real cpu fault */
-    cpu_restore_state(cs, retaddr, true);
-    arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
-#else
-    hwaddr phys_addr;
-    target_ulong page_size;
-    int prot, ret;
-    MemTxAttrs attrs = {};
-    ARMCacheAttrs cacheattrs = {};
-
-    /*
-     * Walk the page table and (if the mapping exists) add the page
-     * to the TLB.  On success, return true.  Otherwise, if probing,
-     * return false.  Otherwise populate fsr with ARM DFSR/IFSR fault
-     * register format, and signal the fault.
-     */
-    ret = get_phys_addr(&cpu->env, address, access_type,
-                        core_to_arm_mmu_idx(&cpu->env, mmu_idx),
-                        &phys_addr, &attrs, &prot, &page_size,
-                        &fi, &cacheattrs);
-    if (likely(!ret)) {
-        /*
-         * Map a single [sub]page. Regions smaller than our declared
-         * target page size are handled specially, so for those we
-         * pass in the exact addresses.
-         */
-        if (page_size >= TARGET_PAGE_SIZE) {
-            phys_addr &= TARGET_PAGE_MASK;
-            address &= TARGET_PAGE_MASK;
-        }
-        /* Notice and record tagged memory. */
-        if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
-            arm_tlb_mte_tagged(&attrs) = true;
-        }
-
-        tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
-                                prot, mmu_idx, page_size);
-        return true;
-    } else if (probe) {
-        return false;
-    } else {
-        /* now we have a real cpu fault */
-        cpu_restore_state(cs, retaddr, true);
-        arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
-    }
-#endif
-}
diff --git a/target/arm/tcg/user/tlb_helper.c b/target/arm/tcg/user/tlb_helper.c
new file mode 100644
index 0000000000..9f24c96ba0
--- /dev/null
+++ b/target/arm/tcg/user/tlb_helper.c
@@ -0,0 +1,32 @@
+/*
+ * ARM TLB (Translation lookaside buffer) helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+#include "exec/exec-all.h"
+#include "tcg/tlb_helper.h"
+
+bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                      MMUAccessType access_type, int mmu_idx,
+                      bool probe, uintptr_t retaddr)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    ARMMMUFaultInfo fi = {};
+
+    int flags = page_get_flags(useronly_clean_ptr(address));
+    if (flags & PAGE_VALID) {
+        fi.type = ARMFault_Permission;
+    } else {
+        fi.type = ARMFault_Translation;
+    }
+    fi.level = 3;
+
+    /* now we have a real cpu fault */
+    cpu_restore_state(cs, retaddr, true);
+    arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
+}
diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meson.build
index 1a4d7a0940..8f5e955cbd 100644
--- a/target/arm/tcg/sysemu/meson.build
+++ b/target/arm/tcg/sysemu/meson.build
@@ -1,4 +1,5 @@
 arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
   'debug_helper.c',
   'mte_helper.c',
+  'tlb_helper.c',
 ))
diff --git a/target/arm/tcg/user/meson.build b/target/arm/tcg/user/meson.build
index e681e5f5a1..cdca5d970c 100644
--- a/target/arm/tcg/user/meson.build
+++ b/target/arm/tcg/user/meson.build
@@ -1,3 +1,4 @@
 arm_user_ss.add(when: 'CONFIG_TCG', if_true: files(
   'mte_helper.c',
+  'tlb_helper.c',
 ))
-- 
2.20.1



  parent reply	other threads:[~2021-06-04 16:15 UTC|newest]

Thread overview: 207+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04 15:51 [PATCH v16 00/99] arm tcg/kvm refactor and split with kvm only support Alex Bennée
2021-06-04 15:51 ` [PATCH v16 01/99] MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section Alex Bennée
2021-06-04 18:26   ` Richard Henderson
2021-06-04 15:51 ` [PATCH v16 02/99] accel: Introduce 'query-accels' QMP command Alex Bennée
2021-06-07 13:07   ` Thomas Huth
2021-06-08  9:07     ` Philippe Mathieu-Daudé
2021-06-08 15:41   ` Markus Armbruster
2021-06-08 15:43     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 03/99] qtest: Add qtest_has_accel() method Alex Bennée
2021-06-07 13:16   ` Thomas Huth
2021-06-08  9:48     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 04/99] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for KVM Alex Bennée
2021-06-04 21:01   ` Richard Henderson
2021-06-07 13:22   ` Thomas Huth
2021-06-08  8:22     ` Philippe Mathieu-Daudé
2021-06-08 10:49       ` Philippe Mathieu-Daudé
2021-06-08 12:39         ` Philippe Mathieu-Daudé
2021-06-08 14:28           ` Eric Blake
2021-06-08 17:20           ` Claudio Fontana
2021-06-04 15:51 ` [PATCH v16 05/99] qtest/arm-cpu-features: Restrict sve_tests_sve_off_kvm test to KVM Alex Bennée
2021-06-04 21:02   ` Richard Henderson
2021-06-04 15:51 ` [PATCH v16 06/99] qtest/arm-cpu-features: Remove TCG fallback to KVM specific tests Alex Bennée
2021-06-04 21:03   ` Richard Henderson
2021-06-07 13:28   ` Thomas Huth
2021-06-08  8:23     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 07/99] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for TCG Alex Bennée
2021-06-04 21:04   ` Richard Henderson
2021-06-07 13:32   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 08/99] qtest/migration-test: Skip tests if KVM not builtin on s390x/ppc64 Alex Bennée
2021-06-04 21:11   ` Richard Henderson
2021-06-08  8:26     ` Philippe Mathieu-Daudé
2021-06-07 13:33   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 09/99] qtest/bios-tables-test: Rename tests not TCG specific Alex Bennée
2021-06-07 13:39   ` Thomas Huth
2021-06-08  8:33     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 10/99] qtest/bios-tables-test: Rename TCG specific tests Alex Bennée
2021-06-07 13:44   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 11/99] qtest/bios-tables-test: Make test build-independent from accelerator Alex Bennée
2021-06-04 21:14   ` Richard Henderson
2021-06-07 13:47   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 12/99] qtest: Do not restrict bios-tables-test to Aarch64 hosts anymore Alex Bennée
2021-06-04 21:15   ` Richard Henderson
2021-06-07 13:48   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 13/99] meson: add target_user_arch Alex Bennée
2021-06-04 18:01   ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 14/99] accel: add cpu_reset Alex Bennée
2021-06-04 15:51   ` Alex Bennée
2021-06-04 21:23   ` Richard Henderson
2021-06-04 21:23     ` Richard Henderson
2021-06-04 15:51 ` [PATCH v16 15/99] target/arm: move translate modules to tcg/ Alex Bennée
2021-06-04 15:51 ` [PATCH v16 16/99] target/arm: move helpers " Alex Bennée
2021-06-04 15:51 ` [PATCH v16 17/99] arm: tcg: only build under CONFIG_TCG Alex Bennée
2021-06-04 15:51 ` [PATCH v16 18/99] target/arm: tcg: add sysemu and user subdirs Alex Bennée
2021-06-04 15:51 ` [PATCH v16 19/99] target/arm: tcg: split mte_helper user-only and sysemu code Alex Bennée
2021-06-04 15:51 ` [PATCH v16 20/99] target/arm: tcg: move sysemu-only parts of debug_helper Alex Bennée
2021-06-04 15:51 ` Alex Bennée [this message]
2021-06-04 15:51 ` [PATCH v16 22/99] target/arm: tcg: split m_helper user-only and sysemu-only parts Alex Bennée
2021-06-04 15:51 ` [PATCH v16 23/99] target/arm: only build psci for TCG Alex Bennée
2021-06-04 15:51 ` [PATCH v16 24/99] target/arm: split off cpu-sysemu.c Alex Bennée
2021-06-04 15:51 ` [PATCH v16 25/99] target/arm: tcg: fix comment style before move to cpu-mmu Alex Bennée
2021-06-04 15:51 ` [PATCH v16 26/99] target/arm: move physical address translation " Alex Bennée
2021-06-04 15:52 ` [PATCH v16 27/99] target/arm: fix style in preparation of new cpregs module Alex Bennée
2021-06-04 15:52 ` [PATCH v16 28/99] target/arm: split cpregs from tcg/helper.c Alex Bennée
2021-06-04 15:52 ` [PATCH v16 29/99] target/arm: move cpu definitions to common cpu module Alex Bennée
2021-06-04 15:52 ` [PATCH v16 30/99] target/arm: only perform TCG cpu and machine inits if TCG enabled Alex Bennée
2021-06-04 15:52   ` Alex Bennée
2021-06-04 15:52 ` [PATCH v16 31/99] target/arm: tcg: add stubs for some helpers for non-tcg builds Alex Bennée
2021-06-04 15:52 ` [PATCH v16 32/99] target/arm: move cpsr_read, cpsr_write to cpu_common Alex Bennée
2021-06-04 15:52 ` [PATCH v16 33/99] target/arm: add temporary stub for arm_rebuild_hflags Alex Bennée
2021-06-04 15:52 ` [PATCH v16 34/99] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Alex Bennée
2021-06-04 15:52 ` [PATCH v16 35/99] target/arm: split vfp state setting from tcg helpers Alex Bennée
2021-06-04 15:52 ` [PATCH v16 36/99] target/arm: move arm_mmu_idx* to cpu-mmu Alex Bennée
2021-06-04 15:52 ` [PATCH v16 37/99] target/arm: move sve_zcr_len_for_el to common_cpu Alex Bennée
2021-06-04 22:22   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 38/99] target/arm: move arm_sctlr away from tcg helpers Alex Bennée
2021-06-04 22:27   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 39/99] target/arm: move arm_cpu_list to common_cpu Alex Bennée
2021-06-04 15:52 ` [PATCH v16 40/99] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Alex Bennée
2021-06-04 15:52 ` [PATCH v16 41/99] target/arm: new cpu32 ARM 32 bit CPU Class Alex Bennée
2021-06-04 22:53   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 42/99] target/arm: split 32bit and 64bit arm dump state Alex Bennée
2021-06-04 22:59   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 43/99] target/arm: move a15 cpu model away from the TCG-only models Alex Bennée
2021-06-05  0:27   ` Richard Henderson
2021-06-17 18:01     ` Alex Bennée
2021-06-17 20:35       ` Claudio Fontana
2021-06-04 15:52 ` [PATCH v16 44/99] target/arm: fixup sve_exception_el code style before move Alex Bennée
2021-06-04 15:52 ` [PATCH v16 45/99] target/arm: move sve_exception_el out of TCG helpers Alex Bennée
2021-06-04 15:52 ` [PATCH v16 46/99] target/arm: fix comments style of fp_exception_el before moving it Alex Bennée
2021-06-05  0:32   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 47/99] target/arm: move fp_exception_el out of TCG helpers Alex Bennée
2021-06-05  0:35   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 48/99] target/arm: remove now useless ifndef from fp_exception_el Alex Bennée
2021-06-05  0:35   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 49/99] target/arm: make further preparation for the exception code to move Alex Bennée
2021-06-05  1:34   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt functions before move Alex Bennée
2021-06-04 15:52 ` [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c Alex Bennée
2021-06-05  2:19   ` Richard Henderson
2021-06-05  5:56   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 52/99] target/arm: rename handle_semihosting to tcg_handle_semihosting Alex Bennée
2021-06-05  2:22   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 53/99] target/arm: replace CONFIG_TCG with tcg_enabled Alex Bennée
2021-06-05  2:24   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 54/99] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Alex Bennée
2021-06-05  3:39   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 55/99] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Alex Bennée
2021-06-04 15:52 ` [PATCH v16 56/99] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Alex Bennée
2021-06-04 15:52 ` [PATCH v16 57/99] target/arm: remove kvm include file for PSCI and arm-powerctl Alex Bennée
2021-06-04 15:52 ` [PATCH v16 58/99] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Alex Bennée
2021-06-04 15:52 ` [PATCH v16 59/99] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Alex Bennée
2021-06-05  3:52   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 60/99] target/arm: cleanup cpu includes Alex Bennée
2021-06-04 15:52 ` [PATCH v16 61/99] target/arm: remove broad "else" statements when checking accels Alex Bennée
2021-06-05 16:13   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 62/99] target/arm: remove kvm-stub.c Alex Bennée
2021-06-04 15:52 ` [PATCH v16 63/99] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Alex Bennée
2021-06-05 16:24   ` Richard Henderson
2021-06-18 15:25     ` Alex Bennée
2021-06-04 15:52 ` [PATCH v16 64/99] tests: do not run test-hmp on all machines for ARM KVM-only Alex Bennée
2021-06-05 16:28   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 65/99] tests: device-introspect-test: cope with ARM TCG-only devices Alex Bennée
2021-06-05 16:31   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 66/99] tests: do not run qom-test on all machines for ARM KVM-only Alex Bennée
2021-06-05 16:32   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 67/99] target/arm: create kvm cpu accel class Alex Bennée
2021-06-04 15:52 ` [PATCH v16 68/99] target/arm: move kvm post init initialization to kvm cpu accel Alex Bennée
2021-06-04 15:52 ` [PATCH v16 69/99] target/arm: add tcg cpu accel class Alex Bennée
2021-06-05 16:54   ` Richard Henderson
2021-06-24 10:52     ` Alex Bennée
2021-06-04 15:52 ` [PATCH v16 70/99] target/arm: move TCG gt timer creation code in tcg/ Alex Bennée
2021-06-04 15:52 ` [PATCH v16 71/99] target/arm: cpu-sve: new module Alex Bennée
2021-06-05 18:13   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 72/99] target/arm: cpu-sve: rename functions according to module prefix Alex Bennée
2021-06-05 18:39   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 73/99] target/arm: cpu-sve: split TCG and KVM functionality Alex Bennée
2021-06-05 19:31   ` Richard Henderson
2021-06-05 19:52   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 74/99] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Alex Bennée
2021-06-05 18:57   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 75/99] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Alex Bennée
2021-06-05 20:00   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 76/99] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Alex Bennée
2021-06-05 20:06   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 77/99] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Alex Bennée
2021-06-05 20:30   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 78/99] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Alex Bennée
2021-06-05 20:50   ` Richard Henderson
2021-06-10  8:45     ` Claudio Fontana
2021-06-10  9:01       ` Peter Maydell
2021-06-10  9:24         ` Claudio Fontana
2021-06-05 20:57   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 79/99] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Alex Bennée
2021-06-05 20:59   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 80/99] target/arm: tcg-sve: import narrow_vq and change_el functions Alex Bennée
2021-06-05 21:10   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 81/99] target/arm: tcg-sve: rename the " Alex Bennée
2021-06-04 15:52 ` [PATCH v16 82/99] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Alex Bennée
2021-06-05 21:37   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 83/99] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Alex Bennée
2021-06-04 15:52 ` [PATCH v16 84/99] target/arm: cpu-common: wrap a64-only check with is_a64 Alex Bennée
2021-06-05 21:55   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 85/99] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Alex Bennée
2021-06-05 22:06   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 86/99] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Alex Bennée
2021-06-05 22:09   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 87/99] target/arm: move arm_cpu_finalize_features into cpu64 Alex Bennée
2021-06-05 22:14   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 88/99] target/arm: cpu64: rename arm_cpu_finalize_features Alex Bennée
2021-06-05 22:14   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 89/99] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Alex Bennée
2021-06-05 22:20   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 90/99] XXX target/arm: experiment refactoring cpu "max" Alex Bennée
2021-06-04 15:53 ` [PATCH v16 91/99] target/arm: tcg: remove superfluous CONFIG_TCG check Alex Bennée
2021-06-04 15:53 ` [PATCH v16 92/99] target/arm: remove v7m stub function for !CONFIG_TCG Alex Bennée
2021-06-05 22:26   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 93/99] meson: Introduce target-specific Kconfig Alex Bennée
2021-06-05 22:33   ` Richard Henderson
2021-06-18 16:31     ` Alex Bennée
2021-06-04 15:53 ` [PATCH v16 94/99] target/arm: move CONFIG_V7M out of default-devices Alex Bennée
2021-06-05 22:41   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 95/99] hw/arm: add dependency on OR_IRQ for XLNX_VERSAL Alex Bennée
2021-06-05 22:43   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 96/99] tests/qtest: split the cdrom-test into arm/aarch64 Alex Bennée
2021-06-05 22:47   ` Richard Henderson
2021-06-08 14:27     ` Alex Bennée
2021-06-08 14:42       ` Thomas Huth
2021-06-08 14:57       ` Richard Henderson
2021-06-08 15:01       ` Thomas Huth
2021-06-08 15:35         ` Alex Bennée
2021-06-08 17:23           ` Thomas Huth
2021-06-08 15:36         ` John Snow
2021-06-08 13:42   ` John Snow
2021-06-08 14:36     ` Thomas Huth
2021-06-08 14:41       ` Alex Bennée
2021-06-08 14:45         ` Thomas Huth
2021-06-04 15:53 ` [PATCH v16 97/99] tests/qtest: make xlnx-can-test conditional on being configured Alex Bennée
2021-06-05 22:48   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 98/99] configure: allow the overriding of default-config in the build Alex Bennée
2021-06-05 23:01   ` Richard Henderson
2021-06-08 13:03   ` Philippe Mathieu-Daudé
2021-06-04 15:53 ` [PATCH v16 99/99] gitlab: defend the new stripped down arm64 configs Alex Bennée
2021-06-05 23:03   ` Richard Henderson
2021-06-08  8:44 ` [PATCH v16 00/99] arm tcg/kvm refactor and split with kvm only support Philippe Mathieu-Daudé
2021-06-08  8:50   ` Philippe Mathieu-Daudé
2021-09-20 16:24 ` Liang Yan
2021-09-20 16:27   ` Alex Bennée

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