* [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding
@ 2021-06-07 6:10 Jacky Bai
2021-06-07 6:10 ` [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Jacky Bai @ 2021-06-07 6:10 UTC (permalink / raw)
To: linus.walleij, shawnguo, aisheng.dong, stefan, robh+dt
Cc: linux-imx, festevam, kernel, linux-gpio, devicetree
Add pinctrl binding doc for i.MX8ULP
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
update the compatible string to align with driver side.
fix a typo in title
---
.../bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml
new file mode 100644
index 000000000000..86622c4f374b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale IMX8ULP IOMUX Controller
+
+maintainers:
+ - Jacky Bai <ping.bai@nxp.com>
+
+description:
+ Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+ for common binding part and usage.
+
+properties:
+ compatible:
+ const: fsl,imx8ulp-iomuxc1
+
+ reg:
+ maxItems: 1
+
+# Client device subnode's properties
+patternProperties:
+ 'grp$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ properties:
+ fsl,pins:
+ description:
+ each entry consists of 5 integers and represents the mux and config
+ setting for one pin. The first 4 integers <mux_config_reg input_reg
+ mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
+ be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
+ integer CONFIG is the pad setting value like pull-up on this pin. Please
+ refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "mux_config_reg" indicates the offset of mux register.
+ - description: |
+ "input_reg" indicates the offset of select input register.
+ - description: |
+ "mux_mode" indicates the mux value to be applied.
+ - description: |
+ "input_val" indicates the select input value to be applied.
+ - description: |
+ "pad_setting" indicates the pad configuration value to be applied.
+
+ required:
+ - fsl,pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Pinmux controller node
+ - |
+ iomuxc: pinctrl@298c0000 {
+ compatible = "fsl,imx8ulp-iomuxc1";
+ reg = <0x298c0000 0x10000>;
+
+ pinctrl_lpuart5: lpuart5grp {
+ fsl,pins =
+ <0x0138 0x08F0 0x4 0x3 0x3>,
+ <0x013C 0x08EC 0x4 0x3 0x3>;
+ };
+ };
+
+...
--
2.26.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
2021-06-07 6:10 [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Jacky Bai
@ 2021-06-07 6:10 ` Jacky Bai
2021-07-07 9:40 ` Aisheng Dong
2021-07-23 16:05 ` Linus Walleij
2021-07-07 9:47 ` [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Aisheng Dong
2021-07-23 16:04 ` Linus Walleij
2 siblings, 2 replies; 8+ messages in thread
From: Jacky Bai @ 2021-06-07 6:10 UTC (permalink / raw)
To: linus.walleij, shawnguo, aisheng.dong, stefan, robh+dt
Cc: linux-imx, festevam, kernel, linux-gpio, devicetree
From: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8ULP pinctrl driver support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
- v2 changes:
remove the an useless 'if' condition check
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8ulp.c | 274 ++++++++++++++++++++
3 files changed, 282 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8ulp.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index f294336430cc..21fa21c6547b 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -166,6 +166,13 @@ config PINCTRL_IMX8DXL
help
Say Y here to enable the imx8dxl pinctrl driver
+config PINCTRL_IMX8ULP
+ tristate "IMX8ULP pinctrl driver"
+ depends on ARCH_MXC
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx8ulp pinctrl driver
+
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index e476cb671037..c44930b1b362 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
+obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
new file mode 100644
index 000000000000..c5db5dfcfcce
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx8ulp_pads {
+ IMX8ULP_PAD_PTD0 = 0,
+ IMX8ULP_PAD_PTD1,
+ IMX8ULP_PAD_PTD2,
+ IMX8ULP_PAD_PTD3,
+ IMX8ULP_PAD_PTD4,
+ IMX8ULP_PAD_PTD5,
+ IMX8ULP_PAD_PTD6,
+ IMX8ULP_PAD_PTD7,
+ IMX8ULP_PAD_PTD8,
+ IMX8ULP_PAD_PTD9,
+ IMX8ULP_PAD_PTD10,
+ IMX8ULP_PAD_PTD11,
+ IMX8ULP_PAD_PTD12,
+ IMX8ULP_PAD_PTD13,
+ IMX8ULP_PAD_PTD14,
+ IMX8ULP_PAD_PTD15,
+ IMX8ULP_PAD_PTD16,
+ IMX8ULP_PAD_PTD17,
+ IMX8ULP_PAD_PTD18,
+ IMX8ULP_PAD_PTD19,
+ IMX8ULP_PAD_PTD20,
+ IMX8ULP_PAD_PTD21,
+ IMX8ULP_PAD_PTD22,
+ IMX8ULP_PAD_PTD23,
+ IMX8ULP_PAD_RESERVE0,
+ IMX8ULP_PAD_RESERVE1,
+ IMX8ULP_PAD_RESERVE2,
+ IMX8ULP_PAD_RESERVE3,
+ IMX8ULP_PAD_RESERVE4,
+ IMX8ULP_PAD_RESERVE5,
+ IMX8ULP_PAD_RESERVE6,
+ IMX8ULP_PAD_RESERVE7,
+ IMX8ULP_PAD_PTE0,
+ IMX8ULP_PAD_PTE1,
+ IMX8ULP_PAD_PTE2,
+ IMX8ULP_PAD_PTE3,
+ IMX8ULP_PAD_PTE4,
+ IMX8ULP_PAD_PTE5,
+ IMX8ULP_PAD_PTE6,
+ IMX8ULP_PAD_PTE7,
+ IMX8ULP_PAD_PTE8,
+ IMX8ULP_PAD_PTE9,
+ IMX8ULP_PAD_PTE10,
+ IMX8ULP_PAD_PTE11,
+ IMX8ULP_PAD_PTE12,
+ IMX8ULP_PAD_PTE13,
+ IMX8ULP_PAD_PTE14,
+ IMX8ULP_PAD_PTE15,
+ IMX8ULP_PAD_PTE16,
+ IMX8ULP_PAD_PTE17,
+ IMX8ULP_PAD_PTE18,
+ IMX8ULP_PAD_PTE19,
+ IMX8ULP_PAD_PTE20,
+ IMX8ULP_PAD_PTE21,
+ IMX8ULP_PAD_PTE22,
+ IMX8ULP_PAD_PTE23,
+ IMX8ULP_PAD_RESERVE8,
+ IMX8ULP_PAD_RESERVE9,
+ IMX8ULP_PAD_RESERVE10,
+ IMX8ULP_PAD_RESERVE11,
+ IMX8ULP_PAD_RESERVE12,
+ IMX8ULP_PAD_RESERVE13,
+ IMX8ULP_PAD_RESERVE14,
+ IMX8ULP_PAD_RESERVE15,
+ IMX8ULP_PAD_PTF0,
+ IMX8ULP_PAD_PTF1,
+ IMX8ULP_PAD_PTF2,
+ IMX8ULP_PAD_PTF3,
+ IMX8ULP_PAD_PTF4,
+ IMX8ULP_PAD_PTF5,
+ IMX8ULP_PAD_PTF6,
+ IMX8ULP_PAD_PTF7,
+ IMX8ULP_PAD_PTF8,
+ IMX8ULP_PAD_PTF9,
+ IMX8ULP_PAD_PTF10,
+ IMX8ULP_PAD_PTF11,
+ IMX8ULP_PAD_PTF12,
+ IMX8ULP_PAD_PTF13,
+ IMX8ULP_PAD_PTF14,
+ IMX8ULP_PAD_PTF15,
+ IMX8ULP_PAD_PTF16,
+ IMX8ULP_PAD_PTF17,
+ IMX8ULP_PAD_PTF18,
+ IMX8ULP_PAD_PTF19,
+ IMX8ULP_PAD_PTF20,
+ IMX8ULP_PAD_PTF21,
+ IMX8ULP_PAD_PTF22,
+ IMX8ULP_PAD_PTF23,
+ IMX8ULP_PAD_PTF24,
+ IMX8ULP_PAD_PTF25,
+ IMX8ULP_PAD_PTF26,
+ IMX8ULP_PAD_PTF27,
+ IMX8ULP_PAD_PTF28,
+ IMX8ULP_PAD_PTF29,
+ IMX8ULP_PAD_PTF30,
+ IMX8ULP_PAD_PTF31,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
+ IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
+};
+
+#define BM_OBE_ENABLED BIT(17)
+#define BM_IBE_ENABLED BIT(16)
+#define BM_MUX_MODE 0xf00
+#define BP_MUX_MODE 8
+
+static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned offset, bool input)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pin_reg *pin_reg;
+ u32 reg;
+
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ if (input)
+ reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
+ else
+ reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+
+ return 0;
+}
+
+static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
+ .pins = imx8ulp_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
+ .gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
+ .mux_mask = BM_MUX_MODE,
+ .mux_shift = BP_MUX_MODE,
+};
+
+static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx8ulp-iomuxc1", },
+ { /* sentinel */ }
+};
+
+static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info);
+}
+
+static struct platform_driver imx8ulp_pinctrl_driver = {
+ .driver = {
+ .name = "imx8ulp-pinctrl",
+ .of_match_table = imx8ulp_pinctrl_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8ulp_pinctrl_probe,
+};
+
+static int __init imx8ulp_pinctrl_init(void)
+{
+ return platform_driver_register(&imx8ulp_pinctrl_driver);
+}
+arch_initcall(imx8ulp_pinctrl_init);
+
+MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
2.26.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* RE: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
2021-06-07 6:10 ` [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
@ 2021-07-07 9:40 ` Aisheng Dong
2021-07-23 16:05 ` Linus Walleij
1 sibling, 0 replies; 8+ messages in thread
From: Aisheng Dong @ 2021-07-07 9:40 UTC (permalink / raw)
To: Jacky Bai, linus.walleij, shawnguo, stefan, robh+dt
Cc: dl-linux-imx, festevam, kernel, linux-gpio, devicetree
> From: Jacky Bai <ping.bai@nxp.com>
> Sent: Monday, June 7, 2021 2:11 PM
> Subject: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
>
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Add i.MX8ULP pinctrl driver support.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Aisheng
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding
2021-06-07 6:10 [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Jacky Bai
2021-06-07 6:10 ` [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
@ 2021-07-07 9:47 ` Aisheng Dong
2021-07-23 16:04 ` Linus Walleij
2 siblings, 0 replies; 8+ messages in thread
From: Aisheng Dong @ 2021-07-07 9:47 UTC (permalink / raw)
To: Jacky Bai, linus.walleij, shawnguo, stefan, robh+dt
Cc: dl-linux-imx, festevam, kernel, linux-gpio, devicetree
> From: Jacky Bai <ping.bai@nxp.com>
> Sent: Monday, June 7, 2021 2:11 PM
>
> Add pinctrl binding doc for i.MX8ULP
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Aisheng
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding
2021-06-07 6:10 [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Jacky Bai
2021-06-07 6:10 ` [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
2021-07-07 9:47 ` [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Aisheng Dong
@ 2021-07-23 16:04 ` Linus Walleij
2 siblings, 0 replies; 8+ messages in thread
From: Linus Walleij @ 2021-07-23 16:04 UTC (permalink / raw)
To: Jacky Bai
Cc: Shawn Guo, Dong Aisheng, Stefan Agner, Rob Herring,
NXP Linux Team, Fabio Estevam, Sascha Hauer,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Mon, Jun 7, 2021 at 8:00 AM Jacky Bai <ping.bai@nxp.com> wrote:
> Add pinctrl binding doc for i.MX8ULP
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
Patch applied!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
2021-06-07 6:10 ` [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
2021-07-07 9:40 ` Aisheng Dong
@ 2021-07-23 16:05 ` Linus Walleij
2021-07-23 16:07 ` Fabio Estevam
1 sibling, 1 reply; 8+ messages in thread
From: Linus Walleij @ 2021-07-23 16:05 UTC (permalink / raw)
To: Jacky Bai
Cc: Shawn Guo, Dong Aisheng, Stefan Agner, Rob Herring,
NXP Linux Team, Fabio Estevam, Sascha Hauer,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Mon, Jun 7, 2021 at 8:00 AM Jacky Bai <ping.bai@nxp.com> wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Add i.MX8ULP pinctrl driver support.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Patch applied!
BTW does "ULP" in the name mean "ultra low power" as usual?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
2021-07-23 16:05 ` Linus Walleij
@ 2021-07-23 16:07 ` Fabio Estevam
0 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2021-07-23 16:07 UTC (permalink / raw)
To: Linus Walleij
Cc: Jacky Bai, Shawn Guo, Dong Aisheng, Stefan Agner, Rob Herring,
NXP Linux Team, Sascha Hauer, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
Hi Linus,
On Fri, Jul 23, 2021 at 1:05 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> Patch applied!
>
> BTW does "ULP" in the name mean "ultra low power" as usual?
Yes, this is correct:
https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8ulp-applications-processor-family:i.MX8ULP
Thanks
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
@ 2021-07-07 1:02 Jacky Bai
0 siblings, 0 replies; 8+ messages in thread
From: Jacky Bai @ 2021-07-07 1:02 UTC (permalink / raw)
To: Jacky Bai, linus.walleij, shawnguo, Aisheng Dong, stefan, robh+dt
Cc: dl-linux-imx, festevam, kernel, linux-gpio, devicetree
Gental ping...
BR
Jacky Bai
> Subject: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support
>
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Add i.MX8ULP pinctrl driver support.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
> - v2 changes:
> remove the an useless 'if' condition check
> ---
> drivers/pinctrl/freescale/Kconfig | 7 +
> drivers/pinctrl/freescale/Makefile | 1 +
> drivers/pinctrl/freescale/pinctrl-imx8ulp.c | 274 ++++++++++++++++++++
> 3 files changed, 282 insertions(+)
> create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8ulp.c
>
> diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
> index f294336430cc..21fa21c6547b 100644
> --- a/drivers/pinctrl/freescale/Kconfig
> +++ b/drivers/pinctrl/freescale/Kconfig
> @@ -166,6 +166,13 @@ config PINCTRL_IMX8DXL
> help
> Say Y here to enable the imx8dxl pinctrl driver
>
> +config PINCTRL_IMX8ULP
> + tristate "IMX8ULP pinctrl driver"
> + depends on ARCH_MXC
> + select PINCTRL_IMX
> + help
> + Say Y here to enable the imx8ulp pinctrl driver
> +
> config PINCTRL_VF610
> bool "Freescale Vybrid VF610 pinctrl driver"
> depends on SOC_VF610
> diff --git a/drivers/pinctrl/freescale/Makefile
> b/drivers/pinctrl/freescale/Makefile
> index e476cb671037..c44930b1b362 100644
> --- a/drivers/pinctrl/freescale/Makefile
> +++ b/drivers/pinctrl/freescale/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MQ) +=
> pinctrl-imx8mq.o
> obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
> obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
> obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
> +obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
> obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
> obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
> obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
> b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
> new file mode 100644
> index 000000000000..c5db5dfcfcce
> --- /dev/null
> +++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
> @@ -0,0 +1,274 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-imx.h"
> +
> +enum imx8ulp_pads {
> + IMX8ULP_PAD_PTD0 = 0,
> + IMX8ULP_PAD_PTD1,
> + IMX8ULP_PAD_PTD2,
> + IMX8ULP_PAD_PTD3,
> + IMX8ULP_PAD_PTD4,
> + IMX8ULP_PAD_PTD5,
> + IMX8ULP_PAD_PTD6,
> + IMX8ULP_PAD_PTD7,
> + IMX8ULP_PAD_PTD8,
> + IMX8ULP_PAD_PTD9,
> + IMX8ULP_PAD_PTD10,
> + IMX8ULP_PAD_PTD11,
> + IMX8ULP_PAD_PTD12,
> + IMX8ULP_PAD_PTD13,
> + IMX8ULP_PAD_PTD14,
> + IMX8ULP_PAD_PTD15,
> + IMX8ULP_PAD_PTD16,
> + IMX8ULP_PAD_PTD17,
> + IMX8ULP_PAD_PTD18,
> + IMX8ULP_PAD_PTD19,
> + IMX8ULP_PAD_PTD20,
> + IMX8ULP_PAD_PTD21,
> + IMX8ULP_PAD_PTD22,
> + IMX8ULP_PAD_PTD23,
> + IMX8ULP_PAD_RESERVE0,
> + IMX8ULP_PAD_RESERVE1,
> + IMX8ULP_PAD_RESERVE2,
> + IMX8ULP_PAD_RESERVE3,
> + IMX8ULP_PAD_RESERVE4,
> + IMX8ULP_PAD_RESERVE5,
> + IMX8ULP_PAD_RESERVE6,
> + IMX8ULP_PAD_RESERVE7,
> + IMX8ULP_PAD_PTE0,
> + IMX8ULP_PAD_PTE1,
> + IMX8ULP_PAD_PTE2,
> + IMX8ULP_PAD_PTE3,
> + IMX8ULP_PAD_PTE4,
> + IMX8ULP_PAD_PTE5,
> + IMX8ULP_PAD_PTE6,
> + IMX8ULP_PAD_PTE7,
> + IMX8ULP_PAD_PTE8,
> + IMX8ULP_PAD_PTE9,
> + IMX8ULP_PAD_PTE10,
> + IMX8ULP_PAD_PTE11,
> + IMX8ULP_PAD_PTE12,
> + IMX8ULP_PAD_PTE13,
> + IMX8ULP_PAD_PTE14,
> + IMX8ULP_PAD_PTE15,
> + IMX8ULP_PAD_PTE16,
> + IMX8ULP_PAD_PTE17,
> + IMX8ULP_PAD_PTE18,
> + IMX8ULP_PAD_PTE19,
> + IMX8ULP_PAD_PTE20,
> + IMX8ULP_PAD_PTE21,
> + IMX8ULP_PAD_PTE22,
> + IMX8ULP_PAD_PTE23,
> + IMX8ULP_PAD_RESERVE8,
> + IMX8ULP_PAD_RESERVE9,
> + IMX8ULP_PAD_RESERVE10,
> + IMX8ULP_PAD_RESERVE11,
> + IMX8ULP_PAD_RESERVE12,
> + IMX8ULP_PAD_RESERVE13,
> + IMX8ULP_PAD_RESERVE14,
> + IMX8ULP_PAD_RESERVE15,
> + IMX8ULP_PAD_PTF0,
> + IMX8ULP_PAD_PTF1,
> + IMX8ULP_PAD_PTF2,
> + IMX8ULP_PAD_PTF3,
> + IMX8ULP_PAD_PTF4,
> + IMX8ULP_PAD_PTF5,
> + IMX8ULP_PAD_PTF6,
> + IMX8ULP_PAD_PTF7,
> + IMX8ULP_PAD_PTF8,
> + IMX8ULP_PAD_PTF9,
> + IMX8ULP_PAD_PTF10,
> + IMX8ULP_PAD_PTF11,
> + IMX8ULP_PAD_PTF12,
> + IMX8ULP_PAD_PTF13,
> + IMX8ULP_PAD_PTF14,
> + IMX8ULP_PAD_PTF15,
> + IMX8ULP_PAD_PTF16,
> + IMX8ULP_PAD_PTF17,
> + IMX8ULP_PAD_PTF18,
> + IMX8ULP_PAD_PTF19,
> + IMX8ULP_PAD_PTF20,
> + IMX8ULP_PAD_PTF21,
> + IMX8ULP_PAD_PTF22,
> + IMX8ULP_PAD_PTF23,
> + IMX8ULP_PAD_PTF24,
> + IMX8ULP_PAD_PTF25,
> + IMX8ULP_PAD_PTF26,
> + IMX8ULP_PAD_PTF27,
> + IMX8ULP_PAD_PTF28,
> + IMX8ULP_PAD_PTF29,
> + IMX8ULP_PAD_PTF30,
> + IMX8ULP_PAD_PTF31,
> +};
> +
> +/* Pad names for the pinmux subsystem */ static const struct
> +pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
> + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
> +};
> +
> +#define BM_OBE_ENABLED BIT(17)
> +#define BM_IBE_ENABLED BIT(16)
> +#define BM_MUX_MODE 0xf00
> +#define BP_MUX_MODE 8
> +
> +static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned offset, bool input)
> +{
> + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
> + const struct imx_pin_reg *pin_reg;
> + u32 reg;
> +
> + reg = readl(ipctl->base + pin_reg->mux_reg);
> + if (input)
> + reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
> + else
> + reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
> + writel(reg, ipctl->base + pin_reg->mux_reg);
> +
> + return 0;
> +}
> +
> +static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
> + .pins = imx8ulp_pinctrl_pads,
> + .npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
> + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
> + .gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
> + .mux_mask = BM_MUX_MODE,
> + .mux_shift = BP_MUX_MODE,
> +};
> +
> +static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
> + { .compatible = "fsl,imx8ulp-iomuxc1", },
> + { /* sentinel */ }
> +};
> +
> +static int imx8ulp_pinctrl_probe(struct platform_device *pdev) {
> + return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info); }
> +
> +static struct platform_driver imx8ulp_pinctrl_driver = {
> + .driver = {
> + .name = "imx8ulp-pinctrl",
> + .of_match_table = imx8ulp_pinctrl_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = imx8ulp_pinctrl_probe,
> +};
> +
> +static int __init imx8ulp_pinctrl_init(void) {
> + return platform_driver_register(&imx8ulp_pinctrl_driver);
> +}
> +arch_initcall(imx8ulp_pinctrl_init);
> +
> +MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
> MODULE_DESCRIPTION("NXP
> +i.MX8ULP pinctrl driver"); MODULE_LICENSE("GPL v2");
> --
> 2.26.2
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-07-23 16:07 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-07 6:10 [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Jacky Bai
2021-06-07 6:10 ` [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
2021-07-07 9:40 ` Aisheng Dong
2021-07-23 16:05 ` Linus Walleij
2021-07-23 16:07 ` Fabio Estevam
2021-07-07 9:47 ` [PATCH v2 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Aisheng Dong
2021-07-23 16:04 ` Linus Walleij
2021-07-07 1:02 [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support Jacky Bai
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