* [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
@ 2021-06-07 14:19 Gwan-gyeong Mun
2021-06-07 14:19 ` [Intel-gfx] [PATCH v3 2/2] drm/i915: Disable PSR around cdclk changes Gwan-gyeong Mun
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Gwan-gyeong Mun @ 2021-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
- Remove unneeded changes around the intel_psr_enable().
- Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
v3: Address Jose's review comment.
- Rename intel_psr_post_exit() to intel_psr_wait_exit_locked().
- Move WA_1408330847 to intel_psr_disable_locked()
- If the PSR is paused by an explicit intel_psr_paused() call, make the
intel_psr_flush() not to activate PSR.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 94 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
3 files changed, 86 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b8d1f702d808..ee7cbdd7db87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1482,6 +1482,7 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+ bool paused;
enum pipe pipe;
enum transcoder transcoder;
bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 000e1ffe8c05..f547c80ed55c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
+ intel_dp->psr.paused = false;
intel_psr_activate(intel_dp);
}
@@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
intel_dp->psr.active = false;
}
-static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
- lockdep_assert_held(&intel_dp->psr.lock);
-
- if (!intel_dp->psr.enabled)
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
-
- intel_psr_exit(intel_dp);
-
if (intel_dp->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -1210,6 +1201,22 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
if (intel_de_wait_for_clear(dev_priv, psr_status,
psr_status_mask, 2000))
drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
+}
+
+static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(&intel_dp->psr.lock);
+
+ if (!intel_dp->psr.enabled)
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
+
+ intel_psr_exit(intel_dp);
+ intel_psr_wait_exit_locked(intel_dp);
/* WA 1408330847 */
if (intel_dp->psr.psr2_sel_fetch_enabled &&
@@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
}
+/**
+ * intel_psr_pause - Pause PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after enabling psr.
+ */
+void intel_psr_pause(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = &intel_dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (!psr->active) {
+ mutex_unlock(&psr->lock);
+ return;
+ }
+
+ intel_psr_exit(intel_dp);
+ intel_psr_wait_exit_locked(intel_dp);
+ psr->paused = true;
+
+ mutex_unlock(&psr->lock);
+
+ cancel_work_sync(&psr->work);
+ cancel_delayed_work_sync(&psr->dc3co_work);
+}
+
+/**
+ * intel_psr_resume - Resume PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after pausing psr.
+ */
+void intel_psr_resume(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = &intel_dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (!psr->paused)
+ goto unlock;
+
+ psr->paused = false;
+ intel_psr_activate(intel_dp);
+
+unlock:
+ mutex_unlock(&psr->lock);
+}
+
static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1908,6 +1970,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
+ /*
+ * If the PSR is paused by an explicit intel_psr_paused() call,
+ * we have to ensure that the PSR is not activated until
+ * intel_psr_resume() is called.
+ */
+ if (intel_dp->psr.paused) {
+ mutex_unlock(&intel_dp->psr.lock);
+ continue;
+ }
+
/* By definition flush = invalidate + flush */
if (pipe_frontbuffer_bits)
psr_force_hw_tracking_exit(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index e3db85e97f4c..641521b101c8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int color_plane);
+void intel_psr_pause(struct intel_dp *intel_dp);
+void intel_psr_resume(struct intel_dp *intel_dp);
#endif /* __INTEL_PSR_H__ */
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH v3 2/2] drm/i915: Disable PSR around cdclk changes
2021-06-07 14:19 [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Gwan-gyeong Mun
@ 2021-06-07 14:19 ` Gwan-gyeong Mun
2021-06-07 16:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Gwan-gyeong Mun @ 2021-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4656a6edc3be..618a9e1e2b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
#include "intel_cdclk.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_psr.h"
#include "intel_sideband.h"
/**
@@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ }
+
/*
* Lock aux/gmbus while we change cdclk in case those
* functions use cdclk. Not all platforms/ports do,
@@ -1930,6 +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
}
mutex_unlock(&dev_priv->gmbus_mutex);
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ }
+
if (drm_WARN(&dev_priv->drm,
intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
2021-06-07 14:19 [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Gwan-gyeong Mun
2021-06-07 14:19 ` [Intel-gfx] [PATCH v3 2/2] drm/i915: Disable PSR around cdclk changes Gwan-gyeong Mun
@ 2021-06-07 16:32 ` Patchwork
2021-06-07 17:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-06-07 16:32 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/91096/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
2021-06-07 14:19 [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Gwan-gyeong Mun
2021-06-07 14:19 ` [Intel-gfx] [PATCH v3 2/2] drm/i915: Disable PSR around cdclk changes Gwan-gyeong Mun
2021-06-07 16:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Patchwork
@ 2021-06-07 17:02 ` Patchwork
2021-06-07 17:02 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2021-06-07 22:11 ` [Intel-gfx] [PATCH v3 1/2] " Souza, Jose
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-06-07 17:02 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 8164 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/91096/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10187 -> Patchwork_20296
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20296 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20296, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20296:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium@vga-edid-read:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@kms_chamelium@vga-edid-read.html
Known issues
------------
Here are the changes found in Patchwork_20296 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_tiled_blits@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@gem_tiled_blits@basic.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][4] ([i915#2782] / [i915#3462] / [i915#794])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][6] -> [INCOMPLETE][7] ([i915#2782])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +7 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][10] ([i915#1436] / [i915#3363])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka: [INCOMPLETE][11] ([i915#155]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@gt_pm:
- fi-cml-s: [DMESG-FAIL][13] ([i915#2291]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@live@gt_pm.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-cml-s/igt@i915_selftest@live@gt_pm.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [DMESG-FAIL][15] ([i915#3462]) -> [INCOMPLETE][16] ([i915#2782] / [i915#3462])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-icl-u2/igt@i915_selftest@live@execlists.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-icl-u2/igt@i915_selftest@live@execlists.html
- fi-cml-s: [INCOMPLETE][17] ([i915#3462]) -> [DMESG-FAIL][18] ([i915#3462])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@live@execlists.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-cml-s/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][19] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][20] ([i915#2782] / [i915#3363])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-icl-u2/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-icl-u2/igt@runner@aborted.html
- fi-glk-dsi: [FAIL][21] ([i915#3363] / [k.org#202321]) -> [FAIL][22] ([i915#2426] / [i915#3363] / [k.org#202321])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-glk-dsi/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-glk-dsi/igt@runner@aborted.html
- fi-bxt-dsi: [FAIL][23] ([i915#3363]) -> [FAIL][24] ([i915#2426] / [i915#3363])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-bxt-dsi/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-bxt-dsi/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (49 -> 42)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10187 -> Patchwork_20296
CI-20190529: 20190529
CI_DRM_10187: 30bc4ca43fe0e01c64e5311342993f73a91eda64 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6099: adb9ee4ed7206725cfe3589bf49f47f9dcf661f2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20296: 36e8d3942997c643852f41274ceadc13f431ba38 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_20296/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
36e8d3942997 drm/i915: Disable PSR around cdclk changes
7504d3538f58 drm/i915/display: Introduce new intel_psr_pause/resume function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/index.html
[-- Attachment #1.2: Type: text/html, Size: 10873 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
2021-06-07 14:19 [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Gwan-gyeong Mun
` (2 preceding siblings ...)
2021-06-07 17:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-06-07 17:02 ` Patchwork
2021-06-07 22:11 ` [Intel-gfx] [PATCH v3 1/2] " Souza, Jose
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-06-07 17:02 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/91096/
State : warning
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/build_32bit.log
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
2021-06-07 14:19 [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Gwan-gyeong Mun
` (3 preceding siblings ...)
2021-06-07 17:02 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
@ 2021-06-07 22:11 ` Souza, Jose
4 siblings, 0 replies; 6+ messages in thread
From: Souza, Jose @ 2021-06-07 22:11 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Mon, 2021-06-07 at 17:19 +0300, Gwan-gyeong Mun wrote:
> This introduces the following function that can exit and activate a psr
> source when intel_psr is already enabled.
>
> - intel_psr_pause(): Pause current PSR. It deactivates current psr state.
> - intel_psr_resume(): Resume paused PSR. It activates paused psr state.
>
> v2: Address Jose's review comment.
> - Remove unneeded changes around the intel_psr_enable().
> - Add intel_psr_post_exit() which processes waiting until PSR is idle
> and WA for SelectiveFetch.
> v3: Address Jose's review comment.
> - Rename intel_psr_post_exit() to intel_psr_wait_exit_locked().
> - Move WA_1408330847 to intel_psr_disable_locked()
> - If the PSR is paused by an explicit intel_psr_paused() call, make the
> intel_psr_flush() not to activate PSR.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 94 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 86 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b8d1f702d808..ee7cbdd7db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1482,6 +1482,7 @@ struct intel_psr {
> bool sink_support;
> bool source_support;
> bool enabled;
> + bool paused;
> enum pipe pipe;
> enum transcoder transcoder;
> bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 000e1ffe8c05..f547c80ed55c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp);
> intel_dp->psr.enabled = true;
> + intel_dp->psr.paused = false;
>
> intel_psr_activate(intel_dp);
> }
> @@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
> intel_dp->psr.active = false;
> }
>
> -static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - lockdep_assert_held(&intel_dp->psr.lock);
> -
> - if (!intel_dp->psr.enabled)
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> - intel_dp->psr.psr2_enabled ? "2" : "1");
> -
> - intel_psr_exit(intel_dp);
> -
> if (intel_dp->psr.psr2_enabled) {
> psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> @@ -1210,6 +1201,22 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> if (intel_de_wait_for_clear(dev_priv, psr_status,
> psr_status_mask, 2000))
> drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
> +}
> +
> +static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(&intel_dp->psr.lock);
> +
> + if (!intel_dp->psr.enabled)
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> + intel_dp->psr.psr2_enabled ? "2" : "1");
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_wait_exit_locked(intel_dp);
>
> /* WA 1408330847 */
> if (intel_dp->psr.psr2_sel_fetch_enabled &&
> @@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> }
>
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (!psr->active) {
Hum just one more case came to mind.
PSR is not active but there is a scheduled psr->work that will execute after this call.
psr->active will be false, returning then a few msec later PSR will be activated.
So can you change this to psr->enabled?
intel_psr_exit() and intel_psr_wait_exit_locked() will handle the psr->active == false.
With that:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> + mutex_unlock(&psr->lock);
> + return;
> + }
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_wait_exit_locked(intel_dp);
> + psr->paused = true;
> +
> + mutex_unlock(&psr->lock);
> +
> + cancel_work_sync(&psr->work);
> + cancel_delayed_work_sync(&psr->dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (!psr->paused)
> + goto unlock;
> +
> + psr->paused = false;
> + intel_psr_activate(intel_dp);
> +
> +unlock:
> + mutex_unlock(&psr->lock);
> +}
> +
> static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1908,6 +1970,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
> intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
>
> + /*
> + * If the PSR is paused by an explicit intel_psr_paused() call,
> + * we have to ensure that the PSR is not activated until
> + * intel_psr_resume() is called.
> + */
> + if (intel_dp->psr.paused) {
> + mutex_unlock(&intel_dp->psr.lock);
> + continue;
> + }
> +
> /* By definition flush = invalidate + flush */
> if (pipe_frontbuffer_bits)
> psr_force_hw_tracking_exit(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index e3db85e97f4c..641521b101c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> int color_plane);
> +void intel_psr_pause(struct intel_dp *intel_dp);
> +void intel_psr_resume(struct intel_dp *intel_dp);
>
> #endif /* __INTEL_PSR_H__ */
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-06-07 22:11 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-07 14:19 [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Gwan-gyeong Mun
2021-06-07 14:19 ` [Intel-gfx] [PATCH v3 2/2] drm/i915: Disable PSR around cdclk changes Gwan-gyeong Mun
2021-06-07 16:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function Patchwork
2021-06-07 17:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-06-07 17:02 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2021-06-07 22:11 ` [Intel-gfx] [PATCH v3 1/2] " Souza, Jose
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