* [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
@ 2021-06-07 14:23 Rohit Khaire
2021-06-07 14:31 ` Christian König
0 siblings, 1 reply; 13+ messages in thread
From: Rohit Khaire @ 2021-06-07 14:23 UTC (permalink / raw)
To: amd-gfx, Alexander Deucher, Hawking Zhang, Emily Deng, Monk Liu,
Peng Ju Zhou, Horace Chen
Cc: Davis Ming, Rohit Khaire, Christian König
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_USED_INT_THRESHOLD, threshold);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) {
+ DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+ return;
+ }
+ } else {
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+ }
+
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
RB_USED_INT_THRESHOLD, threshold);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) {
+ DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+ return;
+ }
+ } else {
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+ }
+
WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 14:23 [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV Rohit Khaire
@ 2021-06-07 14:31 ` Christian König
2021-06-07 15:30 ` Khaire, Rohit
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2021-06-07 14:31 UTC (permalink / raw)
To: Rohit Khaire, amd-gfx, Alexander Deucher, Hawking Zhang,
Emily Deng, Monk Liu, Peng Ju Zhou, Horace Chen
Cc: Davis Ming
Why are the ring 1&2 enabled on SRIOV in the first place?
Christian.
Am 07.06.21 um 16:23 schrieb Rohit Khaire:
> This is similar to IH_RB_CNTL programming in
> navi10_ih_toggle_ring_interrupts
>
> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index eac564e8dd52..e41188c04846 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_USED_INT_THRESHOLD, threshold);
>
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> +
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_USED_INT_THRESHOLD, threshold);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> +
> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
> }
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 14:31 ` Christian König
@ 2021-06-07 15:30 ` Khaire, Rohit
2021-06-07 15:57 ` Christian König
0 siblings, 1 reply; 13+ messages in thread
From: Khaire, Rohit @ 2021-06-07 15:30 UTC (permalink / raw)
To: Koenig, Christian, amd-gfx, Deucher, Alexander, Zhang, Hawking,
Deng, Emily, Liu, Monk, Zhou, Peng Ju, Chen, Horace
Cc: Ming, Davis
[AMD Public Use]
We don't need RING1 and RING2 functionality for SRIOV afaik.
But looking at the description of the original commit message it affects RING0 too?
" drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)
outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the outstanding log
can't reach threshold so that driver can't get latest wptr info and
miss some interrupts."
Rohit
-----Original Message-----
From: Koenig, Christian <Christian.Koenig@amd.com>
Sent: June 7, 2021 10:31 AM
To: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
Cc: Ming, Davis <Davis.Ming@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
Why are the ring 1&2 enabled on SRIOV in the first place?
Christian.
Am 07.06.21 um 16:23 schrieb Rohit Khaire:
> This is similar to IH_RB_CNTL programming in
> navi10_ih_toggle_ring_interrupts
>
> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index eac564e8dd52..e41188c04846 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_USED_INT_THRESHOLD, threshold);
>
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> +
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_USED_INT_THRESHOLD, threshold);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> +
> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
> }
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 15:30 ` Khaire, Rohit
@ 2021-06-07 15:57 ` Christian König
2021-06-07 15:59 ` Khaire, Rohit
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2021-06-07 15:57 UTC (permalink / raw)
To: Khaire, Rohit, amd-gfx, Deucher, Alexander, Zhang, Hawking, Deng,
Emily, Liu, Monk, Zhou, Peng Ju, Chen, Horace
Cc: Ming, Davis
Do you have the hash for this commit?
Thanks,
Christian.
Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
> [AMD Public Use]
>
> We don't need RING1 and RING2 functionality for SRIOV afaik.
>
> But looking at the description of the original commit message it affects RING0 too?
>
> " drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)
>
> outstanding log reaches threshold will trigger IH ring1/2's wptr
> reported, that will avoid generating interrupts to ring0 too frequent.
> But if ring1/2's wptr hasn't been increased for a long time, the outstanding log
> can't reach threshold so that driver can't get latest wptr info and
> miss some interrupts."
>
> Rohit
>
> -----Original Message-----
> From: Koenig, Christian <Christian.Koenig@amd.com>
> Sent: June 7, 2021 10:31 AM
> To: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
> Cc: Ming, Davis <Davis.Ming@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
>
> Why are the ring 1&2 enabled on SRIOV in the first place?
>
> Christian.
>
> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>> This is similar to IH_RB_CNTL programming in
>> navi10_ih_toggle_ring_interrupts
>>
>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index eac564e8dd52..e41188c04846 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>> RB_USED_INT_THRESHOLD, threshold);
>>
>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) {
>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>> + return;
>> + }
>> + } else {
>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>> + }
>> +
>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>> RB_USED_INT_THRESHOLD, threshold);
>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) {
>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>> + return;
>> + }
>> + } else {
>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>> + }
>> +
>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>> }
>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 15:57 ` Christian König
@ 2021-06-07 15:59 ` Khaire, Rohit
2021-06-07 16:29 ` Christian König
0 siblings, 1 reply; 13+ messages in thread
From: Khaire, Rohit @ 2021-06-07 15:59 UTC (permalink / raw)
To: Koenig, Christian, amd-gfx, Deucher, Alexander, Zhang, Hawking,
Deng, Emily, Liu, Monk, Zhou, Peng Ju, Chen, Horace
Cc: Ming, Davis
[AMD Public Use]
The hash is 5ea6f9c
Rohit
-----Original Message-----
From: Koenig, Christian <Christian.Koenig@amd.com>
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
Cc: Ming, Davis <Davis.Ming@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
Do you have the hash for this commit?
Thanks,
Christian.
Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
> [AMD Public Use]
>
> We don't need RING1 and RING2 functionality for SRIOV afaik.
>
> But looking at the description of the original commit message it affects RING0 too?
>
> " drm/amdgpu: add timeout flush mechanism to update wptr for self
> interrupt (v2)
>
> outstanding log reaches threshold will trigger IH ring1/2's wptr
> reported, that will avoid generating interrupts to ring0 too frequent.
> But if ring1/2's wptr hasn't been increased for a long time, the
> outstanding log can't reach threshold so that driver can't get latest
> wptr info and miss some interrupts."
>
> Rohit
>
> -----Original Message-----
> From: Koenig, Christian <Christian.Koenig@amd.com>
> Sent: June 7, 2021 10:31 AM
> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
> amd-gfx@lists.freedesktop.org; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou,
> Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
> Cc: Ming, Davis <Davis.Ming@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
> on SRIOV
>
> Why are the ring 1&2 enabled on SRIOV in the first place?
>
> Christian.
>
> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>> This is similar to IH_RB_CNTL programming in
>> navi10_ih_toggle_ring_interrupts
>>
>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index eac564e8dd52..e41188c04846 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>> RB_USED_INT_THRESHOLD, threshold);
>>
>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) {
>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>> + return;
>> + }
>> + } else {
>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>> + }
>> +
>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>> RB_USED_INT_THRESHOLD, threshold);
>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) {
>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>> + return;
>> + }
>> + } else {
>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>> + }
>> +
>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>> }
>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 15:59 ` Khaire, Rohit
@ 2021-06-07 16:29 ` Christian König
2021-06-07 16:36 ` Felix Kuehling
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2021-06-07 16:29 UTC (permalink / raw)
To: Khaire, Rohit, amd-gfx, Deucher, Alexander, Zhang, Hawking, Deng,
Emily, Liu, Monk, Zhou, Peng Ju, Chen, Horace, Kuehling, Felix
Cc: Ming, Davis
That's a workaround for bare metal and as far as I know doesn't apply to
SRIOV.
We only need the additional IH rings for page fault handling or log
handling and as far as I know that is incompatible with SRIOV for the
moment. But Felix might have some more updates on this.
So as long as we don't support that under SRIOV we don't need this patch
either.
Christian.
Am 07.06.21 um 17:59 schrieb Khaire, Rohit:
> [AMD Public Use]
>
> The hash is 5ea6f9c
>
> Rohit
>
> -----Original Message-----
> From: Koenig, Christian <Christian.Koenig@amd.com>
> Sent: June 7, 2021 11:58 AM
> To: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
> Cc: Ming, Davis <Davis.Ming@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
>
> Do you have the hash for this commit?
>
> Thanks,
> Christian.
>
> Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
>> [AMD Public Use]
>>
>> We don't need RING1 and RING2 functionality for SRIOV afaik.
>>
>> But looking at the description of the original commit message it affects RING0 too?
>>
>> " drm/amdgpu: add timeout flush mechanism to update wptr for self
>> interrupt (v2)
>>
>> outstanding log reaches threshold will trigger IH ring1/2's wptr
>> reported, that will avoid generating interrupts to ring0 too frequent.
>> But if ring1/2's wptr hasn't been increased for a long time, the
>> outstanding log can't reach threshold so that driver can't get latest
>> wptr info and miss some interrupts."
>>
>> Rohit
>>
>> -----Original Message-----
>> From: Koenig, Christian <Christian.Koenig@amd.com>
>> Sent: June 7, 2021 10:31 AM
>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou,
>> Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
>> Cc: Ming, Davis <Davis.Ming@amd.com>
>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
>> on SRIOV
>>
>> Why are the ring 1&2 enabled on SRIOV in the first place?
>>
>> Christian.
>>
>> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>>> This is similar to IH_RB_CNTL programming in
>>> navi10_ih_toggle_ring_interrupts
>>>
>>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> index eac564e8dd52..e41188c04846 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>> RB_USED_INT_THRESHOLD, threshold);
>>>
>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) {
>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>>> + return;
>>> + }
>>> + } else {
>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>> + }
>>> +
>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>> RB_USED_INT_THRESHOLD, threshold);
>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) {
>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>>> + return;
>>> + }
>>> + } else {
>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>> + }
>>> +
>>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>>> }
>>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 16:29 ` Christian König
@ 2021-06-07 16:36 ` Felix Kuehling
2021-06-07 16:42 ` Christian König
0 siblings, 1 reply; 13+ messages in thread
From: Felix Kuehling @ 2021-06-07 16:36 UTC (permalink / raw)
To: Christian König, Khaire, Rohit, amd-gfx, Deucher, Alexander,
Zhang, Hawking, Deng, Emily, Liu, Monk, Zhou, Peng Ju, Chen,
Horace
Cc: Ming, Davis
With SRIOV, the interrupt routing is setup by the hypervisor driver. We
need the secondary IH rings in case the hypervisor enabled rerouting of
page fault interrupts. I'm not sure what the hypervisor driver does today.
Regards,
Felix
Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
> That's a workaround for bare metal and as far as I know doesn't apply
> to SRIOV.
>
> We only need the additional IH rings for page fault handling or log
> handling and as far as I know that is incompatible with SRIOV for the
> moment. But Felix might have some more updates on this.
>
> So as long as we don't support that under SRIOV we don't need this
> patch either.
>
> Christian.
>
> Am 07.06.21 um 17:59 schrieb Khaire, Rohit:
>> [AMD Public Use]
>>
>> The hash is 5ea6f9c
>>
>> Rohit
>>
>> -----Original Message-----
>> From: Koenig, Christian <Christian.Koenig@amd.com>
>> Sent: June 7, 2021 11:58 AM
>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou,
>> Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
>> Cc: Ming, Davis <Davis.Ming@amd.com>
>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>> IH_RB_CNTL_RING1/2 on SRIOV
>>
>> Do you have the hash for this commit?
>>
>> Thanks,
>> Christian.
>>
>> Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
>>> [AMD Public Use]
>>>
>>> We don't need RING1 and RING2 functionality for SRIOV afaik.
>>>
>>> But looking at the description of the original commit message it
>>> affects RING0 too?
>>>
>>> " drm/amdgpu: add timeout flush mechanism to update wptr for self
>>> interrupt (v2)
>>>
>>> outstanding log reaches threshold will trigger IH ring1/2's wptr
>>> reported, that will avoid generating interrupts to ring0 too frequent.
>>> But if ring1/2's wptr hasn't been increased for a long time, the
>>> outstanding log can't reach threshold so that driver can't get latest
>>> wptr info and miss some interrupts."
>>>
>>> Rohit
>>>
>>> -----Original Message-----
>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>> Sent: June 7, 2021 10:31 AM
>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou,
>>> Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
>>> on SRIOV
>>>
>>> Why are the ring 1&2 enabled on SRIOV in the first place?
>>>
>>> Christian.
>>>
>>> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>>>> This is similar to IH_RB_CNTL programming in
>>>> navi10_ih_toggle_ring_interrupts
>>>>
>>>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
>>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>> index eac564e8dd52..e41188c04846 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
>>>> amdgpu_device *adev,
>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>>> RB_USED_INT_THRESHOLD, threshold);
>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>> + if (amdgpu_sriov_vf(adev) &&
>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>>>> ih_rb_cntl)) {
>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>>>> + return;
>>>> + }
>>>> + } else {
>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>> + }
>>>> +
>>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>>> RB_USED_INT_THRESHOLD, threshold);
>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>> + if (amdgpu_sriov_vf(adev) &&
>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>>>> ih_rb_cntl)) {
>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>>>> + return;
>>>> + }
>>>> + } else {
>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>> + }
>>>> +
>>>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>>>> }
>>>>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 16:36 ` Felix Kuehling
@ 2021-06-07 16:42 ` Christian König
2021-06-07 17:33 ` Khaire, Rohit
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2021-06-07 16:42 UTC (permalink / raw)
To: Felix Kuehling, Khaire, Rohit, amd-gfx, Deucher, Alexander,
Zhang, Hawking, Deng, Emily, Liu, Monk, Zhou, Peng Ju, Chen,
Horace
Cc: Ming, Davis
Ah, good point. In this case we should probably rather save than sorry.
Then I suggest to clean up this patch, repeating the psp_reg_program()
and error message is pretty horrible coding style.
Christian.
Am 07.06.21 um 18:36 schrieb Felix Kuehling:
> With SRIOV, the interrupt routing is setup by the hypervisor driver. We
> need the secondary IH rings in case the hypervisor enabled rerouting of
> page fault interrupts. I'm not sure what the hypervisor driver does today.
>
> Regards,
> Felix
>
>
> Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
>> That's a workaround for bare metal and as far as I know doesn't apply
>> to SRIOV.
>>
>> We only need the additional IH rings for page fault handling or log
>> handling and as far as I know that is incompatible with SRIOV for the
>> moment. But Felix might have some more updates on this.
>>
>> So as long as we don't support that under SRIOV we don't need this
>> patch either.
>>
>> Christian.
>>
>> Am 07.06.21 um 17:59 schrieb Khaire, Rohit:
>>> [AMD Public Use]
>>>
>>> The hash is 5ea6f9c
>>>
>>> Rohit
>>>
>>> -----Original Message-----
>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>> Sent: June 7, 2021 11:58 AM
>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou,
>>> Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>>> IH_RB_CNTL_RING1/2 on SRIOV
>>>
>>> Do you have the hash for this commit?
>>>
>>> Thanks,
>>> Christian.
>>>
>>> Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
>>>> [AMD Public Use]
>>>>
>>>> We don't need RING1 and RING2 functionality for SRIOV afaik.
>>>>
>>>> But looking at the description of the original commit message it
>>>> affects RING0 too?
>>>>
>>>> " drm/amdgpu: add timeout flush mechanism to update wptr for self
>>>> interrupt (v2)
>>>>
>>>> outstanding log reaches threshold will trigger IH ring1/2's wptr
>>>> reported, that will avoid generating interrupts to ring0 too frequent.
>>>> But if ring1/2's wptr hasn't been increased for a long time, the
>>>> outstanding log can't reach threshold so that driver can't get latest
>>>> wptr info and miss some interrupts."
>>>>
>>>> Rohit
>>>>
>>>> -----Original Message-----
>>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>>> Sent: June 7, 2021 10:31 AM
>>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>>>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou,
>>>> Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
>>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
>>>> on SRIOV
>>>>
>>>> Why are the ring 1&2 enabled on SRIOV in the first place?
>>>>
>>>> Christian.
>>>>
>>>> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>>>>> This is similar to IH_RB_CNTL programming in
>>>>> navi10_ih_toggle_ring_interrupts
>>>>>
>>>>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++++++++++++++++++--
>>>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> index eac564e8dd52..e41188c04846 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
>>>>> amdgpu_device *adev,
>>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>>>> RB_USED_INT_THRESHOLD, threshold);
>>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>>> + if (amdgpu_sriov_vf(adev) &&
>>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>>>>> ih_rb_cntl)) {
>>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>>>>> + return;
>>>>> + }
>>>>> + } else {
>>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>>> + }
>>>>> +
>>>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>>>> RB_USED_INT_THRESHOLD, threshold);
>>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>>> + if (amdgpu_sriov_vf(adev) &&
>>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>>>>> ih_rb_cntl)) {
>>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>>>>> + return;
>>>>> + }
>>>>> + } else {
>>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>>> + }
>>>>> +
>>>>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>>>>> }
>>>>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 16:42 ` Christian König
@ 2021-06-07 17:33 ` Khaire, Rohit
2021-06-07 17:40 ` Christian König
0 siblings, 1 reply; 13+ messages in thread
From: Khaire, Rohit @ 2021-06-07 17:33 UTC (permalink / raw)
To: Koenig, Christian, Kuehling, Felix, amd-gfx, Deucher, Alexander,
Zhang, Hawking, Deng, Emily, Liu, Monk, Zhou, Peng Ju, Chen,
Horace
Cc: Ming, Davis
[AMD Public Use]
OK.
I will just skip the function call for SRIOV and resend.
Rohit
-----Original Message-----
From: Koenig, Christian <Christian.Koenig@amd.com>
Sent: June 7, 2021 12:42 PM
To: Kuehling, Felix <Felix.Kuehling@amd.com>; Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
Cc: Ming, Davis <Davis.Ming@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
Ah, good point. In this case we should probably rather save than sorry.
Then I suggest to clean up this patch, repeating the psp_reg_program() and error message is pretty horrible coding style.
Christian.
Am 07.06.21 um 18:36 schrieb Felix Kuehling:
> With SRIOV, the interrupt routing is setup by the hypervisor driver.
> We need the secondary IH rings in case the hypervisor enabled
> rerouting of page fault interrupts. I'm not sure what the hypervisor driver does today.
>
> Regards,
> Felix
>
>
> Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
>> That's a workaround for bare metal and as far as I know doesn't apply
>> to SRIOV.
>>
>> We only need the additional IH rings for page fault handling or log
>> handling and as far as I know that is incompatible with SRIOV for the
>> moment. But Felix might have some more updates on this.
>>
>> So as long as we don't support that under SRIOV we don't need this
>> patch either.
>>
>> Christian.
>>
>> Am 07.06.21 um 17:59 schrieb Khaire, Rohit:
>>> [AMD Public Use]
>>>
>>> The hash is 5ea6f9c
>>>
>>> Rohit
>>>
>>> -----Original Message-----
>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>> Sent: June 7, 2021 11:58 AM
>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>;
>>> Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace
>>> <Horace.Chen@amd.com>
>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>>> IH_RB_CNTL_RING1/2 on SRIOV
>>>
>>> Do you have the hash for this commit?
>>>
>>> Thanks,
>>> Christian.
>>>
>>> Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
>>>> [AMD Public Use]
>>>>
>>>> We don't need RING1 and RING2 functionality for SRIOV afaik.
>>>>
>>>> But looking at the description of the original commit message it
>>>> affects RING0 too?
>>>>
>>>> " drm/amdgpu: add timeout flush mechanism to update wptr for self
>>>> interrupt (v2)
>>>>
>>>> outstanding log reaches threshold will trigger IH ring1/2's wptr
>>>> reported, that will avoid generating interrupts to ring0 too frequent.
>>>> But if ring1/2's wptr hasn't been increased for a long time, the
>>>> outstanding log can't reach threshold so that driver can't get
>>>> latest wptr info and miss some interrupts."
>>>>
>>>> Rohit
>>>>
>>>> -----Original Message-----
>>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>>> Sent: June 7, 2021 10:31 AM
>>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>>> <Alexander.Deucher@amd.com>; Zhang, Hawking
>>>> <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu,
>>>> Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen,
>>>> Horace <Horace.Chen@amd.com>
>>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>>>> IH_RB_CNTL_RING1/2 on SRIOV
>>>>
>>>> Why are the ring 1&2 enabled on SRIOV in the first place?
>>>>
>>>> Christian.
>>>>
>>>> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>>>>> This is similar to IH_RB_CNTL programming in
>>>>> navi10_ih_toggle_ring_interrupts
>>>>>
>>>>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20
>>>>> ++++++++++++++++++--
>>>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> index eac564e8dd52..e41188c04846 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
>>>>> amdgpu_device *adev,
>>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>>>> RB_USED_INT_THRESHOLD, threshold);
>>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>>> + if (amdgpu_sriov_vf(adev) &&
>>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>>>>> ih_rb_cntl)) {
>>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>>>>> + return;
>>>>> + }
>>>>> + } else {
>>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>>> + }
>>>>> +
>>>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>>>> RB_USED_INT_THRESHOLD, threshold);
>>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>>> + if (amdgpu_sriov_vf(adev) &&
>>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>>>>> ih_rb_cntl)) {
>>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>>>>> + return;
>>>>> + }
>>>>> + } else {
>>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>>> + }
>>>>> +
>>>>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>>>>> }
>>>>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 17:33 ` Khaire, Rohit
@ 2021-06-07 17:40 ` Christian König
2021-06-07 19:39 ` Rohit Khaire
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2021-06-07 17:40 UTC (permalink / raw)
To: Khaire, Rohit, Koenig, Christian, Kuehling, Felix, amd-gfx,
Deucher, Alexander, Zhang, Hawking, Deng, Emily, Liu, Monk, Zhou,
Peng Ju, Chen, Horace
Cc: Ming, Davis
That won't work either.
We still need to initialize the control registers and tell the hardware
that we have properly setup the ring buffers.
Just add the error message to psp_reg_program() instead of duplicating
that over and over again.
Christian.
Am 07.06.21 um 19:33 schrieb Khaire, Rohit:
> [AMD Public Use]
>
> OK.
>
> I will just skip the function call for SRIOV and resend.
>
> Rohit
>
> -----Original Message-----
> From: Koenig, Christian <Christian.Koenig@amd.com>
> Sent: June 7, 2021 12:42 PM
> To: Kuehling, Felix <Felix.Kuehling@amd.com>; Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
> Cc: Ming, Davis <Davis.Ming@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
>
> Ah, good point. In this case we should probably rather save than sorry.
>
> Then I suggest to clean up this patch, repeating the psp_reg_program() and error message is pretty horrible coding style.
>
> Christian.
>
> Am 07.06.21 um 18:36 schrieb Felix Kuehling:
>> With SRIOV, the interrupt routing is setup by the hypervisor driver.
>> We need the secondary IH rings in case the hypervisor enabled
>> rerouting of page fault interrupts. I'm not sure what the hypervisor driver does today.
>>
>> Regards,
>> Felix
>>
>>
>> Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
>>> That's a workaround for bare metal and as far as I know doesn't apply
>>> to SRIOV.
>>>
>>> We only need the additional IH rings for page fault handling or log
>>> handling and as far as I know that is incompatible with SRIOV for the
>>> moment. But Felix might have some more updates on this.
>>>
>>> So as long as we don't support that under SRIOV we don't need this
>>> patch either.
>>>
>>> Christian.
>>>
>>> Am 07.06.21 um 17:59 schrieb Khaire, Rohit:
>>>> [AMD Public Use]
>>>>
>>>> The hash is 5ea6f9c
>>>>
>>>> Rohit
>>>>
>>>> -----Original Message-----
>>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>>> Sent: June 7, 2021 11:58 AM
>>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>>> <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>;
>>>> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>;
>>>> Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace
>>>> <Horace.Chen@amd.com>
>>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>>>> IH_RB_CNTL_RING1/2 on SRIOV
>>>>
>>>> Do you have the hash for this commit?
>>>>
>>>> Thanks,
>>>> Christian.
>>>>
>>>> Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
>>>>> [AMD Public Use]
>>>>>
>>>>> We don't need RING1 and RING2 functionality for SRIOV afaik.
>>>>>
>>>>> But looking at the description of the original commit message it
>>>>> affects RING0 too?
>>>>>
>>>>> " drm/amdgpu: add timeout flush mechanism to update wptr for self
>>>>> interrupt (v2)
>>>>>
>>>>> outstanding log reaches threshold will trigger IH ring1/2's wptr
>>>>> reported, that will avoid generating interrupts to ring0 too frequent.
>>>>> But if ring1/2's wptr hasn't been increased for a long time, the
>>>>> outstanding log can't reach threshold so that driver can't get
>>>>> latest wptr info and miss some interrupts."
>>>>>
>>>>> Rohit
>>>>>
>>>>> -----Original Message-----
>>>>> From: Koenig, Christian <Christian.Koenig@amd.com>
>>>>> Sent: June 7, 2021 10:31 AM
>>>>> To: Khaire, Rohit <Rohit.Khaire@amd.com>;
>>>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>>>> <Alexander.Deucher@amd.com>; Zhang, Hawking
>>>>> <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu,
>>>>> Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen,
>>>>> Horace <Horace.Chen@amd.com>
>>>>> Cc: Ming, Davis <Davis.Ming@amd.com>
>>>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>>>>> IH_RB_CNTL_RING1/2 on SRIOV
>>>>>
>>>>> Why are the ring 1&2 enabled on SRIOV in the first place?
>>>>>
>>>>> Christian.
>>>>>
>>>>> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>>>>>> This is similar to IH_RB_CNTL programming in
>>>>>> navi10_ih_toggle_ring_interrupts
>>>>>>
>>>>>> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20
>>>>>> ++++++++++++++++++--
>>>>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>>> index eac564e8dd52..e41188c04846 100644
>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>>>>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
>>>>>> amdgpu_device *adev,
>>>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>>>>> RB_USED_INT_THRESHOLD, threshold);
>>>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>>>> + if (amdgpu_sriov_vf(adev) &&
>>>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
>>>>>> ih_rb_cntl)) {
>>>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>>>>>> + return;
>>>>>> + }
>>>>>> + } else {
>>>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>>>>>> + }
>>>>>> +
>>>>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>>>>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>>>>> RB_USED_INT_THRESHOLD, threshold);
>>>>>> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>>>> + if (amdgpu_sriov_vf(adev) &&
>>>>>> amdgpu_sriov_reg_indirect_ih(adev)) {
>>>>>> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
>>>>>> ih_rb_cntl)) {
>>>>>> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>>>>>> + return;
>>>>>> + }
>>>>>> + } else {
>>>>>> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>>>>>> + }
>>>>>> +
>>>>>> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>>>>>> }
>>>>>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 17:40 ` Christian König
@ 2021-06-07 19:39 ` Rohit Khaire
2021-06-07 19:41 ` Christian König
0 siblings, 1 reply; 13+ messages in thread
From: Rohit Khaire @ 2021-06-07 19:39 UTC (permalink / raw)
To: amd-gfx, Christian König, Felix Kuehling, Alexander Deucher,
Hawking Zhang, Emily Deng, Monk Liu, Peng Ju Zhou, Horace Chen
Cc: Davis Ming, Rohit Khaire
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 +++++++++++++++-----
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 47ceb783e2a5..058b1b1271e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -683,6 +683,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
psp_prep_reg_prog_cmd_buf(cmd, reg, value);
ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+ if (ret)
+ DRM_ERROR("PSP failed to program reg id %d", reg);
kfree(cmd);
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..376ea281c4a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_USED_INT_THRESHOLD, threshold);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
+ return;
+ } else {
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+ }
+
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
RB_USED_INT_THRESHOLD, threshold);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
+ return;
+ } else {
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+ }
+
WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
}
@@ -153,10 +165,8 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
- if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
- DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
return -ETIMEDOUT;
- }
} else {
WREG32(ih_regs->ih_rb_cntl, tmp);
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 19:39 ` Rohit Khaire
@ 2021-06-07 19:41 ` Christian König
2021-06-08 14:08 ` 回复: " Chen, Horace
0 siblings, 1 reply; 13+ messages in thread
From: Christian König @ 2021-06-07 19:41 UTC (permalink / raw)
To: Rohit Khaire, amd-gfx, Felix Kuehling, Alexander Deucher,
Hawking Zhang, Emily Deng, Monk Liu, Peng Ju Zhou, Horace Chen
Cc: Davis Ming
Am 07.06.21 um 21:39 schrieb Rohit Khaire:
> This is similar to IH_RB_CNTL programming in
> navi10_ih_toggle_ring_interrupts
>
> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 +++++++++++++++-----
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 47ceb783e2a5..058b1b1271e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -683,6 +683,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
>
> psp_prep_reg_prog_cmd_buf(cmd, reg, value);
> ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
> + if (ret)
> + DRM_ERROR("PSP failed to program reg id %d", reg);
>
> kfree(cmd);
> return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index eac564e8dd52..376ea281c4a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_USED_INT_THRESHOLD, threshold);
>
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
> + return;
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> +
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_USED_INT_THRESHOLD, threshold);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
> + return;
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> +
> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
> }
>
> @@ -153,10 +165,8 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
>
> if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> - if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> - DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
> return -ETIMEDOUT;
> - }
> } else {
> WREG32(ih_regs->ih_rb_cntl, tmp);
> }
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* 回复: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
2021-06-07 19:41 ` Christian König
@ 2021-06-08 14:08 ` Chen, Horace
0 siblings, 0 replies; 13+ messages in thread
From: Chen, Horace @ 2021-06-08 14:08 UTC (permalink / raw)
To: Koenig, Christian, Khaire, Rohit, amd-gfx, Kuehling, Felix,
Deucher, Alexander, Zhang, Hawking, Deng, Emily, Liu, Monk, Zhou,
Peng Ju
Cc: Ming, Davis
[-- Attachment #1.1: Type: text/plain, Size: 3830 bytes --]
Reviewed-by: Horace Chen <horace.chen@amd.com>
________________________________
发件人: Koenig, Christian <Christian.Koenig@amd.com>
发送时间: 2021年6月8日 3:41
收件人: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Kuehling, Felix <Felix.Kuehling@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, Horace <Horace.Chen@amd.com>
抄送: Ming, Davis <Davis.Ming@amd.com>
主题: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV
Am 07.06.21 um 21:39 schrieb Rohit Khaire:
> This is similar to IH_RB_CNTL programming in
> navi10_ih_toggle_ring_interrupts
>
> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 +++++++++++++++-----
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 47ceb783e2a5..058b1b1271e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -683,6 +683,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
>
> psp_prep_reg_prog_cmd_buf(cmd, reg, value);
> ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
> + if (ret)
> + DRM_ERROR("PSP failed to program reg id %d", reg);
>
> kfree(cmd);
> return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index eac564e8dd52..376ea281c4a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_USED_INT_THRESHOLD, threshold);
>
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
> + return;
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> +
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_USED_INT_THRESHOLD, threshold);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
> + return;
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> +
> WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
> }
>
> @@ -153,10 +165,8 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
>
> if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> - if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> - DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
> return -ETIMEDOUT;
> - }
> } else {
> WREG32(ih_regs->ih_rb_cntl, tmp);
> }
[-- Attachment #1.2: Type: text/html, Size: 7536 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-06-08 14:08 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-07 14:23 [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV Rohit Khaire
2021-06-07 14:31 ` Christian König
2021-06-07 15:30 ` Khaire, Rohit
2021-06-07 15:57 ` Christian König
2021-06-07 15:59 ` Khaire, Rohit
2021-06-07 16:29 ` Christian König
2021-06-07 16:36 ` Felix Kuehling
2021-06-07 16:42 ` Christian König
2021-06-07 17:33 ` Khaire, Rohit
2021-06-07 17:40 ` Christian König
2021-06-07 19:39 ` Rohit Khaire
2021-06-07 19:41 ` Christian König
2021-06-08 14:08 ` 回复: " Chen, Horace
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.