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From: Luben Tuikov <luben.tuikov@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alexander Deucher <Alexander.Deucher@amd.com>,
	Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>,
	Luben Tuikov <luben.tuikov@amd.com>
Subject: [PATCH 35/40] drm/amdgpu: Simplify RAS EEPROM checksum calculations
Date: Tue,  8 Jun 2021 17:39:49 -0400	[thread overview]
Message-ID: <20210608213954.5517-36-luben.tuikov@amd.com> (raw)
In-Reply-To: <20210608213954.5517-1-luben.tuikov@amd.com>

Rename update_table_header() to
write_table_header() as this function is actually
writing it to EEPROM.

Use kernel types; use u8 to carry around the
checksum, in order to take advantage of arithmetic
modulo 8-bits (256).

Tidy up to 80 columns.

When updating the checksum, just recalculate the
whole thing.

Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
---
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c    | 98 +++++++++----------
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h    |  2 +-
 2 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 7d0f9e1e62dc4f..54ef31594accd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -141,8 +141,8 @@ static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_heade
 	hdr->checksum	      = le32_to_cpu(pp[4]);
 }
 
-static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
-				 unsigned char *buff)
+static int __write_table_header(struct amdgpu_ras_eeprom_control *control,
+				unsigned char *buff)
 {
 	int ret = 0;
 	struct amdgpu_device *adev = to_amdgpu_device(control);
@@ -162,69 +162,74 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
 	return ret;
 }
 
-static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
+static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
 {
 	int i;
-	uint32_t tbl_sum = 0;
+	u8 hdr_sum = 0;
+	u8  *p;
+	size_t sz;
 
 	/* Header checksum, skip checksum field in the calculation */
-	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
-		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
+	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
+	p = (u8 *) &control->tbl_hdr;
+	for (i = 0; i < sz; i++, p++)
+		hdr_sum += *p;
 
-	return tbl_sum;
+	return hdr_sum;
 }
 
-static uint32_t  __calc_recs_byte_sum(struct eeprom_table_record *records,
-				      int num)
+static u8 __calc_recs_byte_sum(const struct eeprom_table_record *record,
+			       const int num)
 {
 	int i, j;
-	uint32_t tbl_sum = 0;
+	u8  tbl_sum = 0;
+
+	if (!record)
+		return 0;
 
 	/* Records checksum */
 	for (i = 0; i < num; i++) {
-		struct eeprom_table_record *record = &records[i];
+		u8 *p = (u8 *) &record[i];
 
-		for (j = 0; j < sizeof(*record); j++) {
-			tbl_sum += *(((unsigned char *)record) + j);
-		}
+		for (j = 0; j < sizeof(*record); j++, p++)
+			tbl_sum += *p;
 	}
 
 	return tbl_sum;
 }
 
-static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
-				  struct eeprom_table_record *records, int num)
+static inline u8
+__calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
+		    struct eeprom_table_record *records, int num)
 {
-	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
+	return __calc_hdr_byte_sum(control) +
+		__calc_recs_byte_sum(records, num);
 }
 
-/* Checksum = 256 -((sum of all table entries) mod 256) */
 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
-				  struct eeprom_table_record *records, int num,
-				  uint32_t old_hdr_byte_sum)
+				  struct eeprom_table_record *records, int num)
 {
-	/*
-	 * This will update the table sum with new records.
-	 *
-	 * TODO: What happens when the EEPROM table is to be wrapped around
-	 * and old records from start will get overridden.
-	 */
-
-	/* need to recalculate updated header byte sum */
-	control->tbl_byte_sum -= old_hdr_byte_sum;
-	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
+	u8 v;
 
-	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
+	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
+	/* Avoid 32-bit sign extension. */
+	v = -control->tbl_byte_sum;
+	control->tbl_hdr.checksum = v;
 }
 
-/* table sum mod 256 + checksum must equals 256 */
-static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
-			    struct eeprom_table_record *records, int num)
+static bool __verify_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
+				  struct eeprom_table_record *records,
+				  int num)
 {
+	u8 result;
+
 	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
 
-	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
-		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
+	result = (u8)control->tbl_hdr.checksum + control->tbl_byte_sum;
+	if (result) {
+		DRM_WARN("RAS table checksum mismatch: stored:0x%02X wants:0x%02hhX",
+			 control->tbl_hdr.checksum,
+			 -control->tbl_byte_sum);
 		return false;
 	}
 
@@ -232,8 +237,8 @@ static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
 }
 
 static int amdgpu_ras_eeprom_correct_header_tag(
-				struct amdgpu_ras_eeprom_control *control,
-				uint32_t header)
+	struct amdgpu_ras_eeprom_control *control,
+	uint32_t header)
 {
 	unsigned char buff[RAS_TABLE_HEADER_SIZE];
 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
@@ -243,7 +248,7 @@ static int amdgpu_ras_eeprom_correct_header_tag(
 
 	mutex_lock(&control->tbl_mutex);
 	hdr->header = header;
-	ret = __update_table_header(control, buff);
+	ret = __write_table_header(control, buff);
 	mutex_unlock(&control->tbl_mutex);
 
 	return ret;
@@ -262,11 +267,9 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
 	hdr->first_rec_offset = RAS_RECORD_START;
 	hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
 
-	control->tbl_byte_sum = 0;
-	__update_tbl_checksum(control, NULL, 0, 0);
+	__update_tbl_checksum(control, NULL, 0);
 	control->next_addr = RAS_RECORD_START;
-
-	ret = __update_table_header(control, buff);
+	ret = __write_table_header(control, buff);
 
 	mutex_unlock(&control->tbl_mutex);
 
@@ -521,8 +524,6 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
 	}
 
 	if (write) {
-		uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
-
 		/*
 		 * Update table header with size and CRC and account for table
 		 * wrap around where the assumption is that we treat it as empty
@@ -537,10 +538,9 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
 			control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
 			control->num_recs * RAS_TABLE_RECORD_SIZE;
 
-		__update_tbl_checksum(control, records, num, old_hdr_byte_sum);
-
-		__update_table_header(control, buffs);
-	} else if (!__validate_tbl_checksum(control, records, num)) {
+		__update_tbl_checksum(control, records, num);
+		__write_table_header(control, buffs);
+	} else if (!__verify_tbl_checksum(control, records, num)) {
 		DRM_WARN("EEPROM Table checksum mismatch!");
 		/* TODO Uncomment when EEPROM read/write is relliable */
 		/* ret = -EIO; */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
index fa9c509a8e2f2b..4906ed9fb8cdd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
@@ -48,7 +48,7 @@ struct amdgpu_ras_eeprom_control {
 	uint32_t next_addr;
 	unsigned int num_recs;
 	struct mutex tbl_mutex;
-	uint32_t tbl_byte_sum;
+	u8 tbl_byte_sum;
 };
 
 /*
-- 
2.32.0

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  parent reply	other threads:[~2021-06-08 21:41 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-08 21:39 [PATCH 00/40] I2C fixes Luben Tuikov
2021-06-08 21:39 ` [PATCH 01/40] drm/amdgpu: add a mutex for the smu11 i2c bus (v2) Luben Tuikov
2021-06-08 21:39 ` [PATCH 02/40] drm/amdgpu/pm: rework i2c xfers on sienna cichlid (v3) Luben Tuikov
2021-06-08 21:39 ` [PATCH 03/40] drm/amdgpu/pm: rework i2c xfers on arcturus (v3) Luben Tuikov
2021-06-08 21:39 ` [PATCH 04/40] drm/amdgpu/pm: add smu i2c implementation for navi1x (v3) Luben Tuikov
2021-06-08 21:39 ` [PATCH 05/40] drm/amdgpu: add new helper for handling EEPROM i2c transfers Luben Tuikov
2021-06-08 21:39 ` [PATCH 06/40] drm/amdgpu/ras: switch ras eeprom handling to use generic helper Luben Tuikov
2021-06-08 21:39 ` [PATCH 07/40] drm/amdgpu/ras: switch fru eeprom handling to use generic helper (v2) Luben Tuikov
2021-06-08 21:39 ` [PATCH 08/40] drm/amdgpu: i2c subsystem uses 7 bit addresses Luben Tuikov
2021-06-08 21:39 ` [PATCH 09/40] drm/amdgpu: add I2C_CLASS_HWMON to SMU i2c buses Luben Tuikov
2021-06-08 21:39 ` [PATCH 10/40] drm/amdgpu: rework smu11 i2c for generic operation Luben Tuikov
2021-06-08 21:39 ` [PATCH 11/40] drm/amdgpu: only set restart on first cmd of the smu i2c transaction Luben Tuikov
2021-06-08 21:39 ` [PATCH 12/40] drm/amdgpu: Remember to wait 10ms for write buffer flush v2 Luben Tuikov
2021-06-08 21:39 ` [PATCH 13/40] dmr/amdgpu: Add RESTART handling also to smu_v11_0_i2c (VG20) Luben Tuikov
2021-06-10 20:18   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 14/40] drm/amdgpu: Drop i > 0 restriction for issuing RESTART Luben Tuikov
2021-06-10 20:21   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 15/40] drm/amdgpu: Send STOP for the last byte of msg only Luben Tuikov
2021-06-10 20:22   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 16/40] drm/amd/pm: SMU I2C: Return number of messages processed Luben Tuikov
2021-06-10 20:25   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 17/40] drm/amdgpu/pm: ADD I2C quirk adapter table Luben Tuikov
2021-06-10 20:26   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 18/40] drm/amdgpu: Fix Vega20 I2C to be agnostic (v2) Luben Tuikov
2021-06-10 20:43   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 19/40] drm/amdgpu: Fixes to the AMDGPU EEPROM driver Luben Tuikov
2021-06-10 20:53   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 20/40] drm/amdgpu: EEPROM respects I2C quirks Luben Tuikov
2021-06-11 17:01   ` Alex Deucher
2021-06-11 17:17     ` Luben Tuikov
2021-06-11 17:37       ` Luben Tuikov
2021-06-08 21:39 ` [PATCH 21/40] drm/amdgpu: I2C EEPROM full memory addressing Luben Tuikov
2021-06-10 20:57   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 22/40] drm/amdgpu: RAS and FRU now use 19-bit I2C address Luben Tuikov
2021-06-10 20:59   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 23/40] drm/amdgpu: Fix wrap-around bugs in RAS Luben Tuikov
2021-06-10 21:00   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 24/40] drm/amdgpu: I2C class is HWMON Luben Tuikov
2021-06-10 21:02   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 25/40] drm/amdgpu: RAS: EEPROM --> RAS Luben Tuikov
2021-06-10 21:03   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 26/40] drm/amdgpu: Rename misspelled function Luben Tuikov
2021-06-10 21:04   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 27/40] drm/amdgpu: RAS xfer to read/write Luben Tuikov
2021-06-10 21:05   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 28/40] drm/amdgpu: EEPROM: add explicit read and write Luben Tuikov
2021-06-10 21:06   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 29/40] drm/amd/pm: Extend the I2C quirk table Luben Tuikov
2021-06-10 21:07   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 30/40] drm/amd/pm: Simplify managed I2C transfer functions Luben Tuikov
2021-06-10 21:08   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 31/40] drm/amdgpu: Fix width of I2C address Luben Tuikov
2021-06-10 21:09   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 32/40] drm/amdgpu: Return result fix in RAS Luben Tuikov
2021-06-10 21:11   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 33/40] drm/amd/pm: Fix a bug in i2c_xfer Luben Tuikov
2021-06-10 21:12   ` Alex Deucher
2021-06-10 22:26     ` Luben Tuikov
2021-06-08 21:39 ` [PATCH 34/40] drm/amdgpu: Fix amdgpu_ras_eeprom_init() Luben Tuikov
2021-06-10 21:12   ` Alex Deucher
2021-06-08 21:39 ` Luben Tuikov [this message]
2021-06-11 17:07   ` [PATCH 35/40] drm/amdgpu: Simplify RAS EEPROM checksum calculations Alex Deucher
2021-06-08 21:39 ` [PATCH 36/40] drm/amdgpu: Use explicit cardinality for clarity Luben Tuikov
2021-06-10 21:17   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 37/40] drm/amdgpu: Optimizations to EEPROM RAS table I/O Luben Tuikov
2021-06-08 21:39 ` [PATCH 38/40] drm/amdgpu: RAS EEPROM table is now in debugfs Luben Tuikov
2021-06-11 17:16   ` Alex Deucher
2021-06-11 17:30     ` Luben Tuikov
2021-06-11 17:51       ` Alex Deucher
2021-06-11 18:06         ` Luben Tuikov
2021-06-08 21:39 ` [PATCH 39/40] drm/amdgpu: Fix koops when accessing RAS EEPROM Luben Tuikov
2021-06-10 21:23   ` Alex Deucher
2021-06-08 21:39 ` [PATCH 40/40] drm/amdgpu: Use a single loop Luben Tuikov
2021-06-10 21:25   ` Alex Deucher

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