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From: Chris Morgan <macroalpha82@gmail.com>
To: Jon Lin <jon.lin@rock-chips.com>
Cc: linux-spi@vger.kernel.org, broonie@kernel.org,
	robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com,
	hjc@rock-chips.com, yifeng.zhao@rock-chips.com,
	sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-clk@vger.kernel.org,
	Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance
Date: Thu, 10 Jun 2021 12:36:57 -0500	[thread overview]
Message-ID: <20210610173657.GA20228@wintermute.localdomain> (raw)
In-Reply-To: <20210609141348.19178-5-jon.lin@rock-chips.com>

On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
> 
>  .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;

Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX.  When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)

The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.

Thank you.

> +	};
> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
> 

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: Jon Lin <jon.lin@rock-chips.com>
Cc: linux-spi@vger.kernel.org, broonie@kernel.org,
	robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com,
	hjc@rock-chips.com, yifeng.zhao@rock-chips.com,
	sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-clk@vger.kernel.org,
	Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance
Date: Thu, 10 Jun 2021 12:36:57 -0500	[thread overview]
Message-ID: <20210610173657.GA20228@wintermute.localdomain> (raw)
In-Reply-To: <20210609141348.19178-5-jon.lin@rock-chips.com>

On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
> 
>  .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;

Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX.  When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)

The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.

Thank you.

> +	};
> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
> 

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: Jon Lin <jon.lin@rock-chips.com>
Cc: linux-spi@vger.kernel.org, broonie@kernel.org,
	robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com,
	hjc@rock-chips.com, yifeng.zhao@rock-chips.com,
	sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-clk@vger.kernel.org,
	Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance
Date: Thu, 10 Jun 2021 12:36:57 -0500	[thread overview]
Message-ID: <20210610173657.GA20228@wintermute.localdomain> (raw)
In-Reply-To: <20210609141348.19178-5-jon.lin@rock-chips.com>

On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
> 
>  .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;

Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX.  When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)

The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.

Thank you.

> +	};
> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
> 

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Chris Morgan <macroalpha82@gmail.com>
To: Jon Lin <jon.lin@rock-chips.com>
Cc: linux-spi@vger.kernel.org, broonie@kernel.org,
	robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com,
	hjc@rock-chips.com, yifeng.zhao@rock-chips.com,
	sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-clk@vger.kernel.org,
	Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance
Date: Thu, 10 Jun 2021 12:36:57 -0500	[thread overview]
Message-ID: <20210610173657.GA20228@wintermute.localdomain> (raw)
In-Reply-To: <20210609141348.19178-5-jon.lin@rock-chips.com>

On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
> 
>  .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;

Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX.  When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)

The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.

Thank you.

> +	};
> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-06-10 17:37 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-09 14:04 [PATCH v7 0/9] Add Rockchip SFC(serial flash controller) support Jon Lin
2021-06-09 14:04 ` Jon Lin
2021-06-09 14:04 ` Jon Lin
2021-06-09 14:04 ` Jon Lin
2021-06-09 14:04 ` [PATCH v7 1/9] dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash controller Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 16:16   ` Rob Herring
2021-06-09 16:16     ` Rob Herring
2021-06-09 16:16     ` Rob Herring
2021-06-09 16:16     ` Rob Herring
2021-06-10  2:43   ` Rob Herring
2021-06-10  2:43     ` Rob Herring
2021-06-10  2:43     ` Rob Herring
2021-06-10  2:43     ` Rob Herring
2021-06-10  3:02     ` Kever Yang
2021-06-10  3:02       ` Kever Yang
2021-06-10  3:02       ` Kever Yang
2021-06-10  3:02       ` Kever Yang
2021-06-11 16:32       ` Ezequiel Garcia
2021-06-11 16:32         ` Ezequiel Garcia
2021-06-11 16:32         ` Ezequiel Garcia
2021-06-11 16:32         ` Ezequiel Garcia
2021-06-16 15:38         ` Rob Herring
2021-06-16 15:38           ` Rob Herring
2021-06-16 15:38           ` Rob Herring
2021-06-16 15:38           ` Rob Herring
2021-06-17  1:51           ` Kever Yang
2021-06-17  1:51             ` Kever Yang
2021-06-17  1:51             ` Kever Yang
2021-06-17  1:51             ` Kever Yang
2021-06-09 14:04 ` [PATCH v7 2/9] spi: rockchip-sfc: add rockchip " Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 18:45   ` Chris Morgan
2021-06-09 18:45     ` Chris Morgan
2021-06-09 18:45     ` Chris Morgan
2021-06-09 18:45     ` Chris Morgan
2021-06-09 14:04 ` [PATCH v7 3/9] arm64: dts: rockchip: Add SFC to PX30 Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04 ` [PATCH v7 4/9] clk: rockchip: rk3036: fix up the sclk_sfc parent error Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:04   ` Jon Lin
2021-06-09 14:13 ` [PATCH v7 5/9] clk: rockchip: Add support for hclk_sfc on rk3036 Jon Lin
2021-06-09 14:13   ` Jon Lin
2021-06-09 14:13   ` Jon Lin
2021-06-09 14:13   ` Jon Lin
2021-06-09 14:13   ` [PATCH v7 6/9] arm: dts: rockchip: Add SFC to RK3036 Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13   ` [PATCH v7 7/9] arm: dts: rockchip: Add SFC to RV1108 Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13   ` [PATCH v7 8/9] arm64: dts: rockchip: Add SFC to RK3308 Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13   ` [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-09 14:13     ` Jon Lin
2021-06-10 17:36     ` Chris Morgan [this message]
2021-06-10 17:36       ` Chris Morgan
2021-06-10 17:36       ` Chris Morgan
2021-06-10 17:36       ` Chris Morgan
2021-06-11  2:26       ` Jon Lin
2021-06-11  2:26         ` Jon Lin
2021-06-11  2:26         ` Jon Lin
2021-06-11  2:26         ` Jon Lin
2021-06-11  3:38         ` Chris Morgan
2021-06-11  3:38           ` Chris Morgan
2021-06-11  3:38           ` Chris Morgan
2021-06-11  3:54           ` Jon Lin
2021-06-11  3:54             ` Jon Lin
2021-06-11  3:54             ` Jon Lin
2021-06-11  3:54             ` Jon Lin
2021-06-11 14:08             ` Chris Morgan
2021-06-11 14:08               ` Chris Morgan
2021-06-11 14:08               ` Chris Morgan

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