* [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator
@ 2021-06-09 13:15 Andrzej Turko
2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Andrzej Turko @ 2021-06-09 13:15 UTC (permalink / raw)
To: igt-dev
In the multiprocess mode all requests to the allocator are
processed in the parent. However, in certain scenarios
(for example gem_exec_capture@pi), a child process may want
to create an allocator instance using its own private file
desriptor. Thus all ioctls used to determine available gtt size
must be called in the child process and not in the parent.
This patch implements the above change.
v2: Test allocators for private and shared contexts in
multiprocess mode.
v3: Prepare all allocator implementations for supporting
region-based memory management.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Andrzej Turko (3):
tests/i915/api_intel_allocator: Exercise allocator in multiprocess
mode
lib/intel_allocator: Move the ioctl calls to client processes
lib/intel_allocator: Add support for regions of allocation
lib/intel_allocator.c | 54 +++++++++++++++++++++++---------
lib/intel_allocator_random.c | 44 +++++++++++++-------------
lib/intel_allocator_reloc.c | 35 +++++++++------------
lib/intel_allocator_simple.c | 45 +++-----------------------
tests/i915/api_intel_allocator.c | 47 +++++++++++++++++++++++++++
5 files changed, 129 insertions(+), 96 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 11+ messages in thread* [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode 2021-06-09 13:15 [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko @ 2021-06-09 13:15 ` Andrzej Turko 2021-06-11 8:15 ` Zbigniew Kempczyński 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_allocator: Move the ioctl calls to client processes Andrzej Turko ` (3 subsequent siblings) 4 siblings, 1 reply; 11+ messages in thread From: Andrzej Turko @ 2021-06-09 13:15 UTC (permalink / raw) To: igt-dev Test creation and usage of allocators in multiprocess mode for contexts shared with the parent process as well as private for the child. This new test discovers a bug in the allocator implementation: allocator is not correctly initialized if it is opened by a child process using its private file descriptor. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/api_intel_allocator.c | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c index ea4ba8bb1..b43467a33 100644 --- a/tests/i915/api_intel_allocator.c +++ b/tests/i915/api_intel_allocator.c @@ -621,6 +621,50 @@ static void execbuf_with_allocator(int fd) igt_assert(intel_allocator_close(ahnd) == true); } +static void multiprocess(int fd, uint8_t type) { + uint64_t p_ahnd, sh_ahnd, fd_ahnd, ctx_ahnd; + uint64_t sh_left, sh_right, fd_left, fd_right; + uint64_t offset; + + intel_allocator_multiprocess_start(); + + p_ahnd = intel_allocator_open(fd, 0, type); + offset = intel_allocator_alloc(p_ahnd, 1, 123, 0); + if (type == INTEL_ALLOCATOR_SIMPLE) + igt_assert(intel_allocator_is_allocated(p_ahnd, 1, 123, offset)); + + igt_fork(child, 1) { + + sh_ahnd = intel_allocator_open(fd, 0, type); + if (type == INTEL_ALLOCATOR_SIMPLE) + igt_assert(intel_allocator_is_allocated(sh_ahnd, 1, 123, offset)); + + ctx_ahnd = intel_allocator_open(fd, 1, type); + igt_assert(!intel_allocator_is_allocated(ctx_ahnd, 1, 123, offset)); + intel_allocator_alloc(ctx_ahnd, 2, 123, 0); + + fd = gem_reopen_driver(fd); + fd_ahnd = intel_allocator_open(fd, 0, type); + igt_assert(!intel_allocator_is_allocated(fd_ahnd, 1, 123, offset)); + intel_allocator_alloc(fd_ahnd, 2, 123, 0); + + + intel_allocator_get_address_range(sh_ahnd, &sh_left, &sh_right); + intel_allocator_get_address_range(fd_ahnd, &fd_left, &fd_right); + igt_assert(sh_left == fd_left && sh_right == fd_right); + + intel_allocator_close(sh_ahnd); + intel_allocator_close(ctx_ahnd); + intel_allocator_close(fd_ahnd); + + } + + igt_waitchildren(); + intel_allocator_close(p_ahnd); + + intel_allocator_multiprocess_stop(); +} + struct allocators { const char *name; uint8_t type; @@ -672,6 +716,9 @@ igt_main igt_dynamic("reserve") reserve(fd, a->type); } + + igt_dynamic("multiprocess") + multiprocess(fd, a->type); } } -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko @ 2021-06-11 8:15 ` Zbigniew Kempczyński 0 siblings, 0 replies; 11+ messages in thread From: Zbigniew Kempczyński @ 2021-06-11 8:15 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev On Wed, Jun 09, 2021 at 03:15:20PM +0200, Andrzej Turko wrote: > Test creation and usage of allocators in multiprocess mode > for contexts shared with the parent process as well as > private for the child. > > This new test discovers a bug in the allocator implementation: > allocator is not correctly initialized if it is opened by > a child process using its private file descriptor. > > Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > tests/i915/api_intel_allocator.c | 47 ++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c > index ea4ba8bb1..b43467a33 100644 > --- a/tests/i915/api_intel_allocator.c > +++ b/tests/i915/api_intel_allocator.c > @@ -621,6 +621,50 @@ static void execbuf_with_allocator(int fd) > igt_assert(intel_allocator_close(ahnd) == true); > } > > +static void multiprocess(int fd, uint8_t type) { Call this test fork-reopen. It will suggest what test is really doing. > + uint64_t p_ahnd, sh_ahnd, fd_ahnd, ctx_ahnd; > + uint64_t sh_left, sh_right, fd_left, fd_right; > + uint64_t offset; > + > + intel_allocator_multiprocess_start(); > + > + p_ahnd = intel_allocator_open(fd, 0, type); > + offset = intel_allocator_alloc(p_ahnd, 1, 123, 0); > + if (type == INTEL_ALLOCATOR_SIMPLE) > + igt_assert(intel_allocator_is_allocated(p_ahnd, 1, 123, offset)); > + > + igt_fork(child, 1) { > + Unnecessary empty line. > + sh_ahnd = intel_allocator_open(fd, 0, type); > + if (type == INTEL_ALLOCATOR_SIMPLE) > + igt_assert(intel_allocator_is_allocated(sh_ahnd, 1, 123, offset)); > + > + ctx_ahnd = intel_allocator_open(fd, 1, type); > + igt_assert(!intel_allocator_is_allocated(ctx_ahnd, 1, 123, offset)); > + intel_allocator_alloc(ctx_ahnd, 2, 123, 0); > + > + fd = gem_reopen_driver(fd); > + fd_ahnd = intel_allocator_open(fd, 0, type); > + igt_assert(!intel_allocator_is_allocated(fd_ahnd, 1, 123, offset)); > + intel_allocator_alloc(fd_ahnd, 2, 123, 0); > + > + Same. > + intel_allocator_get_address_range(sh_ahnd, &sh_left, &sh_right); > + intel_allocator_get_address_range(fd_ahnd, &fd_left, &fd_right); > + igt_assert(sh_left == fd_left && sh_right == fd_right); On the beginning I wondered why we just haven't crashed on allocator thread but quick dig shows gem_aperture_size() allows running on not opened i915 fd. We definitely want to blow allocator thread if underlying fd is not valid opened i915. So series should be prepended with patch which checks on intel_allocator_open do fd is valid or not. For not valid just asserts and see how it explodes. In this case above 3 lines won't be necessary, we got an assert on open. -- Zbigniew > + > + intel_allocator_close(sh_ahnd); > + intel_allocator_close(ctx_ahnd); > + intel_allocator_close(fd_ahnd); > + > + } > + > + igt_waitchildren(); > + intel_allocator_close(p_ahnd); > + > + intel_allocator_multiprocess_stop(); > +} > + > struct allocators { > const char *name; > uint8_t type; > @@ -672,6 +716,9 @@ igt_main > igt_dynamic("reserve") > reserve(fd, a->type); > } > + > + igt_dynamic("multiprocess") > + multiprocess(fd, a->type); > } > } > > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t 2/3] lib/intel_allocator: Move the ioctl calls to client processes 2021-06-09 13:15 [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko @ 2021-06-09 13:15 ` Andrzej Turko 2021-06-11 8:24 ` Zbigniew Kempczyński 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 3/3] lib/intel_allocator: Add support for regions of allocation Andrzej Turko ` (2 subsequent siblings) 4 siblings, 1 reply; 11+ messages in thread From: Andrzej Turko @ 2021-06-09 13:15 UTC (permalink / raw) To: igt-dev When allocator is running in multiprocess mode, all queries are processed in a designated thread in the parent process. However, a child process may request opening the allocator for a gpu using a file descriptor absent in the parent process. Hence, querying available gtt size must be done in the child instead of the parent process. This modification has triggered slight changes to the creation of random and reloc allocators. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- lib/intel_allocator.c | 48 ++++++++++++++++++++++++++---------- lib/intel_allocator_random.c | 26 +++++++------------ lib/intel_allocator_reloc.c | 21 ++++------------ lib/intel_allocator_simple.c | 44 ++++----------------------------- 4 files changed, 54 insertions(+), 85 deletions(-) diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c index 96f839d4b..a78a661b1 100644 --- a/lib/intel_allocator.c +++ b/lib/intel_allocator.c @@ -45,6 +45,12 @@ static inline const char *reqstr(enum reqtype request_type) #define alloc_debug(...) {} #endif +/* + * We limit allocator space to avoid hang when batch would be + * pinned in the last page. + */ +#define RESERVED 4096 + struct allocator { int fd; uint32_t ctx; @@ -58,12 +64,11 @@ struct handle_entry { struct allocator *al; }; -struct intel_allocator *intel_allocator_reloc_create(int fd); -struct intel_allocator *intel_allocator_random_create(int fd); -struct intel_allocator *intel_allocator_simple_create(int fd); +struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); +struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); struct intel_allocator * -intel_allocator_simple_create_full(int fd, uint64_t start, uint64_t end, - enum allocator_strategy strategy); +intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, + enum allocator_strategy strategy); /* * Instead of trying to find first empty handle just get new one. Assuming @@ -286,17 +291,14 @@ static struct intel_allocator *intel_allocator_create(int fd, "We cannot use NONE allocator\n"); break; case INTEL_ALLOCATOR_RELOC: - ial = intel_allocator_reloc_create(fd); + ial = intel_allocator_reloc_create(fd, end); break; case INTEL_ALLOCATOR_RANDOM: - ial = intel_allocator_random_create(fd); + ial = intel_allocator_random_create(fd, end); break; case INTEL_ALLOCATOR_SIMPLE: - if (!start && !end) - ial = intel_allocator_simple_create(fd); - else - ial = intel_allocator_simple_create_full(fd, start, end, - allocator_strategy); + ial = intel_allocator_simple_create(fd, start, end, + allocator_strategy); break; default: igt_assert_f(ial, "Allocator type %d not implemented\n", @@ -877,6 +879,23 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, .open.allocator_type = allocator_type, .open.allocator_strategy = strategy }; struct alloc_resp resp; + uint64_t gtt_size = gem_aperture_size(fd); + + if (!start && !end) { + if (!gem_uses_full_ppgtt(fd)) + gtt_size /= 2; + else + gtt_size -= RESERVED; + + req.open.end = gtt_size; + } else { + + igt_assert(end <= gtt_size); + if (!gem_uses_full_ppgtt(fd)) + gtt_size /= 2; + igt_assert(end - start <= gtt_size); + } + /* Get child_tid only once at open() */ if (child_tid == -1) @@ -907,6 +926,9 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, * Returns: unique handle to the currently opened allocator. * * Notes: + * + * If start = end = 0, the allocator is opened for the whole available gtt. + * * Strategy is generally used internally by the underlying allocator: * * For SIMPLE allocator: @@ -915,7 +937,7 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, * addresses. * * For RANDOM allocator: - * - none of strategy is currently implemented. + * - no strategy is currently implemented. */ uint64_t intel_allocator_open_full(int fd, uint32_t ctx, uint64_t start, uint64_t end, diff --git a/lib/intel_allocator_random.c b/lib/intel_allocator_random.c index 3d9a78f17..85ac2cf4e 100644 --- a/lib/intel_allocator_random.c +++ b/lib/intel_allocator_random.c @@ -10,12 +10,12 @@ #include "igt_rand.h" #include "intel_allocator.h" -struct intel_allocator *intel_allocator_random_create(int fd); +struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); struct intel_allocator_random { uint64_t bias; uint32_t prng; - uint64_t gtt_size; + uint64_t address_mask; uint64_t start; uint64_t end; @@ -23,12 +23,7 @@ struct intel_allocator_random { uint64_t allocated_objects; }; -static uint64_t get_bias(int fd) -{ - (void) fd; - - return 256 << 10; -} +#define BIAS 256 << 10 static void intel_allocator_random_get_address_range(struct intel_allocator *ial, uint64_t *startp, @@ -58,7 +53,7 @@ static uint64_t intel_allocator_random_alloc(struct intel_allocator *ial, do { offset = hars_petruska_f54_1_random64(&ialr->prng); offset += ialr->bias; /* Keep the low 256k clear, for negative deltas */ - offset &= ialr->gtt_size - 1; + offset &= ialr->address_mask; offset &= ~(alignment - 1); } while (offset + size > ialr->end); @@ -150,8 +145,7 @@ static bool intel_allocator_random_is_empty(struct intel_allocator *ial) return !ialr->allocated_objects; } -#define RESERVED 4096 -struct intel_allocator *intel_allocator_random_create(int fd) +struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end) { struct intel_allocator *ial; struct intel_allocator_random *ialr; @@ -175,14 +169,12 @@ struct intel_allocator *intel_allocator_random_create(int fd) ialr = ial->priv = calloc(1, sizeof(*ialr)); igt_assert(ial->priv); ialr->prng = (uint32_t) to_user_pointer(ial); - ialr->gtt_size = gem_aperture_size(fd); - igt_debug("Gtt size: %" PRId64 "\n", ialr->gtt_size); - if (!gem_uses_full_ppgtt(fd)) - ialr->gtt_size /= 2; - ialr->bias = get_bias(fd); + igt_assert(BIAS < end); + ialr->address_mask = (1ULL << (igt_fls(end) - 1)) - 1; + ialr->bias = BIAS; ialr->start = ialr->bias; - ialr->end = ialr->gtt_size - RESERVED; + ialr->end = end; ialr->allocated_objects = 0; diff --git a/lib/intel_allocator_reloc.c b/lib/intel_allocator_reloc.c index e8af787b0..703d054c6 100644 --- a/lib/intel_allocator_reloc.c +++ b/lib/intel_allocator_reloc.c @@ -10,12 +10,11 @@ #include "igt_rand.h" #include "intel_allocator.h" -struct intel_allocator *intel_allocator_reloc_create(int fd); +struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); struct intel_allocator_reloc { uint64_t bias; uint32_t prng; - uint64_t gtt_size; uint64_t start; uint64_t end; uint64_t offset; @@ -24,12 +23,7 @@ struct intel_allocator_reloc { uint64_t allocated_objects; }; -static uint64_t get_bias(int fd) -{ - (void) fd; - - return 256 << 10; -} +#define BIAS 256 << 10 static void intel_allocator_reloc_get_address_range(struct intel_allocator *ial, uint64_t *startp, @@ -152,8 +146,7 @@ static bool intel_allocator_reloc_is_empty(struct intel_allocator *ial) return !ialr->allocated_objects; } -#define RESERVED 4096 -struct intel_allocator *intel_allocator_reloc_create(int fd) +struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end) { struct intel_allocator *ial; struct intel_allocator_reloc *ialr; @@ -177,14 +170,10 @@ struct intel_allocator *intel_allocator_reloc_create(int fd) ialr = ial->priv = calloc(1, sizeof(*ialr)); igt_assert(ial->priv); ialr->prng = (uint32_t) to_user_pointer(ial); - ialr->gtt_size = gem_aperture_size(fd); - igt_debug("Gtt size: %" PRId64 "\n", ialr->gtt_size); - if (!gem_uses_full_ppgtt(fd)) - ialr->gtt_size /= 2; - ialr->bias = ialr->offset = get_bias(fd); + ialr->bias = ialr->offset = BIAS; ialr->start = ialr->bias; - ialr->end = ialr->gtt_size - RESERVED; + ialr->end = end; ialr->allocated_objects = 0; diff --git a/lib/intel_allocator_simple.c b/lib/intel_allocator_simple.c index 963d8d257..6022e832b 100644 --- a/lib/intel_allocator_simple.c +++ b/lib/intel_allocator_simple.c @@ -11,17 +11,11 @@ #include "intel_bufops.h" #include "igt_map.h" -/* - * We limit allocator space to avoid hang when batch would be - * pinned in the last page. - */ -#define RESERVED 4096 /* Avoid compilation warning */ -struct intel_allocator *intel_allocator_simple_create(int fd); struct intel_allocator * -intel_allocator_simple_create_full(int fd, uint64_t start, uint64_t end, - enum allocator_strategy strategy); +intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, + enum allocator_strategy strategy); struct simple_vma_heap { struct igt_list_head holes; @@ -734,9 +728,9 @@ static void intel_allocator_simple_print(struct intel_allocator *ial, bool full) ials->allocated_objects, ials->reserved_areas); } -static struct intel_allocator * -__intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, - enum allocator_strategy strategy) +struct intel_allocator * +intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, + enum allocator_strategy strategy) { struct intel_allocator *ial; struct intel_allocator_simple *ials; @@ -777,31 +771,3 @@ __intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, return ial; } - -struct intel_allocator * -intel_allocator_simple_create(int fd) -{ - uint64_t gtt_size = gem_aperture_size(fd); - - if (!gem_uses_full_ppgtt(fd)) - gtt_size /= 2; - else - gtt_size -= RESERVED; - - return __intel_allocator_simple_create(fd, 0, gtt_size, - ALLOC_STRATEGY_HIGH_TO_LOW); -} - -struct intel_allocator * -intel_allocator_simple_create_full(int fd, uint64_t start, uint64_t end, - enum allocator_strategy strategy) -{ - uint64_t gtt_size = gem_aperture_size(fd); - - igt_assert(end <= gtt_size); - if (!gem_uses_full_ppgtt(fd)) - gtt_size /= 2; - igt_assert(end - start <= gtt_size); - - return __intel_allocator_simple_create(fd, start, end, strategy); -} -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] lib/intel_allocator: Move the ioctl calls to client processes 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_allocator: Move the ioctl calls to client processes Andrzej Turko @ 2021-06-11 8:24 ` Zbigniew Kempczyński 0 siblings, 0 replies; 11+ messages in thread From: Zbigniew Kempczyński @ 2021-06-11 8:24 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev On Wed, Jun 09, 2021 at 03:15:21PM +0200, Andrzej Turko wrote: > When allocator is running in multiprocess mode, all queries > are processed in a designated thread in the parent process. > However, a child process may request opening the allocator > for a gpu using a file descriptor absent in the parent process. > Hence, querying available gtt size must be done in the child > instead of the parent process. > > This modification has triggered slight changes to the > creation of random and reloc allocators. > > Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > lib/intel_allocator.c | 48 ++++++++++++++++++++++++++---------- > lib/intel_allocator_random.c | 26 +++++++------------ > lib/intel_allocator_reloc.c | 21 ++++------------ > lib/intel_allocator_simple.c | 44 ++++----------------------------- > 4 files changed, 54 insertions(+), 85 deletions(-) > > diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c > index 96f839d4b..a78a661b1 100644 > --- a/lib/intel_allocator.c > +++ b/lib/intel_allocator.c > @@ -45,6 +45,12 @@ static inline const char *reqstr(enum reqtype request_type) > #define alloc_debug(...) {} > #endif > > +/* > + * We limit allocator space to avoid hang when batch would be > + * pinned in the last page. > + */ > +#define RESERVED 4096 > + > struct allocator { > int fd; > uint32_t ctx; > @@ -58,12 +64,11 @@ struct handle_entry { > struct allocator *al; > }; > > -struct intel_allocator *intel_allocator_reloc_create(int fd); > -struct intel_allocator *intel_allocator_random_create(int fd); > -struct intel_allocator *intel_allocator_simple_create(int fd); > +struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); > +struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); > struct intel_allocator * > -intel_allocator_simple_create_full(int fd, uint64_t start, uint64_t end, > - enum allocator_strategy strategy); > +intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, > + enum allocator_strategy strategy); > > /* > * Instead of trying to find first empty handle just get new one. Assuming > @@ -286,17 +291,14 @@ static struct intel_allocator *intel_allocator_create(int fd, > "We cannot use NONE allocator\n"); > break; > case INTEL_ALLOCATOR_RELOC: > - ial = intel_allocator_reloc_create(fd); > + ial = intel_allocator_reloc_create(fd, end); > break; > case INTEL_ALLOCATOR_RANDOM: > - ial = intel_allocator_random_create(fd); > + ial = intel_allocator_random_create(fd, end); > break; > case INTEL_ALLOCATOR_SIMPLE: > - if (!start && !end) > - ial = intel_allocator_simple_create(fd); > - else > - ial = intel_allocator_simple_create_full(fd, start, end, > - allocator_strategy); > + ial = intel_allocator_simple_create(fd, start, end, > + allocator_strategy); > break; > default: > igt_assert_f(ial, "Allocator type %d not implemented\n", > @@ -877,6 +879,23 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > .open.allocator_type = allocator_type, > .open.allocator_strategy = strategy }; > struct alloc_resp resp; > + uint64_t gtt_size = gem_aperture_size(fd); We have to check fd is valid - we should do this only for !start && !end - in this case we can probe kernel aperture size. Second case (else) shouldn't call any ioctl(). In this case allocator should act for child having 0-knowledge about its fd and configure allocator address ranges according to passed start/end from client (child). -- Zbigniew > + > + if (!start && !end) { > + if (!gem_uses_full_ppgtt(fd)) > + gtt_size /= 2; > + else > + gtt_size -= RESERVED; > + > + req.open.end = gtt_size; > + } else { > + > + igt_assert(end <= gtt_size); > + if (!gem_uses_full_ppgtt(fd)) > + gtt_size /= 2; > + igt_assert(end - start <= gtt_size); > + } > + > > /* Get child_tid only once at open() */ > if (child_tid == -1) > @@ -907,6 +926,9 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > * Returns: unique handle to the currently opened allocator. > * > * Notes: > + * > + * If start = end = 0, the allocator is opened for the whole available gtt. > + * > * Strategy is generally used internally by the underlying allocator: > * > * For SIMPLE allocator: > @@ -915,7 +937,7 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > * addresses. > * > * For RANDOM allocator: > - * - none of strategy is currently implemented. > + * - no strategy is currently implemented. > */ > uint64_t intel_allocator_open_full(int fd, uint32_t ctx, > uint64_t start, uint64_t end, > diff --git a/lib/intel_allocator_random.c b/lib/intel_allocator_random.c > index 3d9a78f17..85ac2cf4e 100644 > --- a/lib/intel_allocator_random.c > +++ b/lib/intel_allocator_random.c > @@ -10,12 +10,12 @@ > #include "igt_rand.h" > #include "intel_allocator.h" > > -struct intel_allocator *intel_allocator_random_create(int fd); > +struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); > > struct intel_allocator_random { > uint64_t bias; > uint32_t prng; > - uint64_t gtt_size; > + uint64_t address_mask; > uint64_t start; > uint64_t end; > > @@ -23,12 +23,7 @@ struct intel_allocator_random { > uint64_t allocated_objects; > }; > > -static uint64_t get_bias(int fd) > -{ > - (void) fd; > - > - return 256 << 10; > -} > +#define BIAS 256 << 10 > > static void intel_allocator_random_get_address_range(struct intel_allocator *ial, > uint64_t *startp, > @@ -58,7 +53,7 @@ static uint64_t intel_allocator_random_alloc(struct intel_allocator *ial, > do { > offset = hars_petruska_f54_1_random64(&ialr->prng); > offset += ialr->bias; /* Keep the low 256k clear, for negative deltas */ > - offset &= ialr->gtt_size - 1; > + offset &= ialr->address_mask; > offset &= ~(alignment - 1); > } while (offset + size > ialr->end); > > @@ -150,8 +145,7 @@ static bool intel_allocator_random_is_empty(struct intel_allocator *ial) > return !ialr->allocated_objects; > } > > -#define RESERVED 4096 > -struct intel_allocator *intel_allocator_random_create(int fd) > +struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end) > { > struct intel_allocator *ial; > struct intel_allocator_random *ialr; > @@ -175,14 +169,12 @@ struct intel_allocator *intel_allocator_random_create(int fd) > ialr = ial->priv = calloc(1, sizeof(*ialr)); > igt_assert(ial->priv); > ialr->prng = (uint32_t) to_user_pointer(ial); > - ialr->gtt_size = gem_aperture_size(fd); > - igt_debug("Gtt size: %" PRId64 "\n", ialr->gtt_size); > - if (!gem_uses_full_ppgtt(fd)) > - ialr->gtt_size /= 2; > > - ialr->bias = get_bias(fd); > + igt_assert(BIAS < end); > + ialr->address_mask = (1ULL << (igt_fls(end) - 1)) - 1; > + ialr->bias = BIAS; > ialr->start = ialr->bias; > - ialr->end = ialr->gtt_size - RESERVED; > + ialr->end = end; > > ialr->allocated_objects = 0; > > diff --git a/lib/intel_allocator_reloc.c b/lib/intel_allocator_reloc.c > index e8af787b0..703d054c6 100644 > --- a/lib/intel_allocator_reloc.c > +++ b/lib/intel_allocator_reloc.c > @@ -10,12 +10,11 @@ > #include "igt_rand.h" > #include "intel_allocator.h" > > -struct intel_allocator *intel_allocator_reloc_create(int fd); > +struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); > > struct intel_allocator_reloc { > uint64_t bias; > uint32_t prng; > - uint64_t gtt_size; > uint64_t start; > uint64_t end; > uint64_t offset; > @@ -24,12 +23,7 @@ struct intel_allocator_reloc { > uint64_t allocated_objects; > }; > > -static uint64_t get_bias(int fd) > -{ > - (void) fd; > - > - return 256 << 10; > -} > +#define BIAS 256 << 10 > > static void intel_allocator_reloc_get_address_range(struct intel_allocator *ial, > uint64_t *startp, > @@ -152,8 +146,7 @@ static bool intel_allocator_reloc_is_empty(struct intel_allocator *ial) > return !ialr->allocated_objects; > } > > -#define RESERVED 4096 > -struct intel_allocator *intel_allocator_reloc_create(int fd) > +struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end) > { > struct intel_allocator *ial; > struct intel_allocator_reloc *ialr; > @@ -177,14 +170,10 @@ struct intel_allocator *intel_allocator_reloc_create(int fd) > ialr = ial->priv = calloc(1, sizeof(*ialr)); > igt_assert(ial->priv); > ialr->prng = (uint32_t) to_user_pointer(ial); > - ialr->gtt_size = gem_aperture_size(fd); > - igt_debug("Gtt size: %" PRId64 "\n", ialr->gtt_size); > - if (!gem_uses_full_ppgtt(fd)) > - ialr->gtt_size /= 2; > > - ialr->bias = ialr->offset = get_bias(fd); > + ialr->bias = ialr->offset = BIAS; > ialr->start = ialr->bias; > - ialr->end = ialr->gtt_size - RESERVED; > + ialr->end = end; > > ialr->allocated_objects = 0; > > diff --git a/lib/intel_allocator_simple.c b/lib/intel_allocator_simple.c > index 963d8d257..6022e832b 100644 > --- a/lib/intel_allocator_simple.c > +++ b/lib/intel_allocator_simple.c > @@ -11,17 +11,11 @@ > #include "intel_bufops.h" > #include "igt_map.h" > > -/* > - * We limit allocator space to avoid hang when batch would be > - * pinned in the last page. > - */ > -#define RESERVED 4096 > > /* Avoid compilation warning */ > -struct intel_allocator *intel_allocator_simple_create(int fd); > struct intel_allocator * > -intel_allocator_simple_create_full(int fd, uint64_t start, uint64_t end, > - enum allocator_strategy strategy); > +intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, > + enum allocator_strategy strategy); > > struct simple_vma_heap { > struct igt_list_head holes; > @@ -734,9 +728,9 @@ static void intel_allocator_simple_print(struct intel_allocator *ial, bool full) > ials->allocated_objects, ials->reserved_areas); > } > > -static struct intel_allocator * > -__intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, > - enum allocator_strategy strategy) > +struct intel_allocator * > +intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, > + enum allocator_strategy strategy) > { > struct intel_allocator *ial; > struct intel_allocator_simple *ials; > @@ -777,31 +771,3 @@ __intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, > > return ial; > } > - > -struct intel_allocator * > -intel_allocator_simple_create(int fd) > -{ > - uint64_t gtt_size = gem_aperture_size(fd); > - > - if (!gem_uses_full_ppgtt(fd)) > - gtt_size /= 2; > - else > - gtt_size -= RESERVED; > - > - return __intel_allocator_simple_create(fd, 0, gtt_size, > - ALLOC_STRATEGY_HIGH_TO_LOW); > -} > - > -struct intel_allocator * > -intel_allocator_simple_create_full(int fd, uint64_t start, uint64_t end, > - enum allocator_strategy strategy) > -{ > - uint64_t gtt_size = gem_aperture_size(fd); > - > - igt_assert(end <= gtt_size); > - if (!gem_uses_full_ppgtt(fd)) > - gtt_size /= 2; > - igt_assert(end - start <= gtt_size); > - > - return __intel_allocator_simple_create(fd, start, end, strategy); > -} > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t 3/3] lib/intel_allocator: Add support for regions of allocation 2021-06-09 13:15 [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_allocator: Move the ioctl calls to client processes Andrzej Turko @ 2021-06-09 13:15 ` Andrzej Turko 2021-06-11 8:57 ` Zbigniew Kempczyński 2021-06-09 14:22 ` [igt-dev] ✓ Fi.CI.BAT: success for Fix the multiprocess mode of intel allocator Patchwork 2021-06-09 16:10 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 1 reply; 11+ messages in thread From: Andrzej Turko @ 2021-06-09 13:15 UTC (permalink / raw) To: igt-dev Enable creating allocators managing only a given interval of available gtt for all implementations, not just the simple allocator. Additinally, set a universal lower bound on alignment to 4096. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- lib/intel_allocator.c | 14 +++++++++----- lib/intel_allocator_random.c | 30 +++++++++++++++++++----------- lib/intel_allocator_reloc.c | 18 ++++++++++++------ lib/intel_allocator_simple.c | 1 - 4 files changed, 40 insertions(+), 23 deletions(-) diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c index a78a661b1..82875224d 100644 --- a/lib/intel_allocator.c +++ b/lib/intel_allocator.c @@ -64,8 +64,10 @@ struct handle_entry { struct allocator *al; }; -struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); -struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); +struct intel_allocator * +intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); +struct intel_allocator * +intel_allocator_random_create(int fd, uint64_t start, uint64_t end); struct intel_allocator * intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, enum allocator_strategy strategy); @@ -291,10 +293,10 @@ static struct intel_allocator *intel_allocator_create(int fd, "We cannot use NONE allocator\n"); break; case INTEL_ALLOCATOR_RELOC: - ial = intel_allocator_reloc_create(fd, end); + ial = intel_allocator_reloc_create(fd, start, end); break; case INTEL_ALLOCATOR_RANDOM: - ial = intel_allocator_random_create(fd, end); + ial = intel_allocator_random_create(fd, start, end); break; case INTEL_ALLOCATOR_SIMPLE: ial = intel_allocator_simple_create(fd, start, end, @@ -1078,10 +1080,12 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, .allocator_handle = allocator_handle, .alloc.handle = handle, .alloc.size = size, - .alloc.alignment = alignment, .alloc.strategy = strategy }; struct alloc_resp resp; + igt_assert((alignment & (alignment-1)) == 0); + req.alloc.alignment = max(alignment, 1 << 12); + igt_assert(handle_request(&req, &resp) == 0); igt_assert(resp.response_type == RESP_ALLOC); diff --git a/lib/intel_allocator_random.c b/lib/intel_allocator_random.c index 85ac2cf4e..1d2969618 100644 --- a/lib/intel_allocator_random.c +++ b/lib/intel_allocator_random.c @@ -10,12 +10,12 @@ #include "igt_rand.h" #include "intel_allocator.h" -struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); +struct intel_allocator * +intel_allocator_random_create(int fd, uint64_t start, uint64_t end); struct intel_allocator_random { - uint64_t bias; uint32_t prng; - uint64_t address_mask; + uint64_t size_mask; uint64_t start; uint64_t end; @@ -23,6 +23,7 @@ struct intel_allocator_random { uint64_t allocated_objects; }; +/* Keep the low 256k clear, for negative deltas */ #define BIAS 256 << 10 static void intel_allocator_random_get_address_range(struct intel_allocator *ial, @@ -45,16 +46,22 @@ static uint64_t intel_allocator_random_alloc(struct intel_allocator *ial, { struct intel_allocator_random *ialr = ial->priv; uint64_t offset; + int cnt = 0; (void) handle; (void) strategy; /* randomize the address, we try to avoid relocations */ do { + /* the object won't fit in the address range */ + if (cnt > 3) return ALLOC_INVALID_ADDRESS; + offset = hars_petruska_f54_1_random64(&ialr->prng); - offset += ialr->bias; /* Keep the low 256k clear, for negative deltas */ - offset &= ialr->address_mask; - offset &= ~(alignment - 1); + if (cnt++ == 3) offset = 0; + + offset &= ialr->size_mask; + offset += ialr->start; + offset = ALIGN(offset, alignment); } while (offset + size > ialr->end); ialr->allocated_objects++; @@ -145,7 +152,8 @@ static bool intel_allocator_random_is_empty(struct intel_allocator *ial) return !ialr->allocated_objects; } -struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end) +struct intel_allocator * +intel_allocator_random_create(int fd, uint64_t start, uint64_t end) { struct intel_allocator *ial; struct intel_allocator_random *ialr; @@ -170,10 +178,10 @@ struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end) igt_assert(ial->priv); ialr->prng = (uint32_t) to_user_pointer(ial); - igt_assert(BIAS < end); - ialr->address_mask = (1ULL << (igt_fls(end) - 1)) - 1; - ialr->bias = BIAS; - ialr->start = ialr->bias; + start = max(start, BIAS); + igt_assert(start < end); + ialr->size_mask = (1ULL << (igt_fls(end - start) - 1)) - 1; + ialr->start = start; ialr->end = end; ialr->allocated_objects = 0; diff --git a/lib/intel_allocator_reloc.c b/lib/intel_allocator_reloc.c index 703d054c6..24b2aeebc 100644 --- a/lib/intel_allocator_reloc.c +++ b/lib/intel_allocator_reloc.c @@ -10,10 +10,10 @@ #include "igt_rand.h" #include "intel_allocator.h" -struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); +struct intel_allocator * +intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); struct intel_allocator_reloc { - uint64_t bias; uint32_t prng; uint64_t start; uint64_t end; @@ -23,6 +23,7 @@ struct intel_allocator_reloc { uint64_t allocated_objects; }; +/* Keep the low 256k clear, for negative deltas */ #define BIAS 256 << 10 static void intel_allocator_reloc_get_address_range(struct intel_allocator *ial, @@ -49,13 +50,16 @@ static uint64_t intel_allocator_reloc_alloc(struct intel_allocator *ial, (void) handle; (void) strategy; - alignment = max(alignment, 4096); aligned_offset = ALIGN(ialr->offset, alignment); /* Check we won't exceed end */ if (aligned_offset + size > ialr->end) aligned_offset = ALIGN(ialr->start, alignment); + /* Check that the object fits in the address range */ + if (aligned_offset + size > ialr->end) + return ALLOC_INVALID_ADDRESS; + offset = aligned_offset; ialr->offset = offset + size; ialr->allocated_objects++; @@ -146,7 +150,8 @@ static bool intel_allocator_reloc_is_empty(struct intel_allocator *ial) return !ialr->allocated_objects; } -struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end) +struct intel_allocator * +intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end) { struct intel_allocator *ial; struct intel_allocator_reloc *ialr; @@ -171,8 +176,9 @@ struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end) igt_assert(ial->priv); ialr->prng = (uint32_t) to_user_pointer(ial); - ialr->bias = ialr->offset = BIAS; - ialr->start = ialr->bias; + start = max(start, BIAS); + igt_assert(start < end); + ialr->offset = ialr->start = start; ialr->end = end; ialr->allocated_objects = 0; diff --git a/lib/intel_allocator_simple.c b/lib/intel_allocator_simple.c index 6022e832b..0e6763964 100644 --- a/lib/intel_allocator_simple.c +++ b/lib/intel_allocator_simple.c @@ -419,7 +419,6 @@ static uint64_t intel_allocator_simple_alloc(struct intel_allocator *ial, ials = (struct intel_allocator_simple *) ial->priv; igt_assert(ials); igt_assert(handle); - alignment = alignment > 0 ? alignment : 1; rec = igt_map_search(ials->objects, &handle); if (rec) { -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/3] lib/intel_allocator: Add support for regions of allocation 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 3/3] lib/intel_allocator: Add support for regions of allocation Andrzej Turko @ 2021-06-11 8:57 ` Zbigniew Kempczyński 0 siblings, 0 replies; 11+ messages in thread From: Zbigniew Kempczyński @ 2021-06-11 8:57 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev On Wed, Jun 09, 2021 at 03:15:22PM +0200, Andrzej Turko wrote: > Enable creating allocators managing only a given interval > of available gtt for all implementations, not just the > simple allocator. Additinally, set a universal lower > bound on alignment to 4096. > > Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > lib/intel_allocator.c | 14 +++++++++----- > lib/intel_allocator_random.c | 30 +++++++++++++++++++----------- > lib/intel_allocator_reloc.c | 18 ++++++++++++------ > lib/intel_allocator_simple.c | 1 - > 4 files changed, 40 insertions(+), 23 deletions(-) > > diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c > index a78a661b1..82875224d 100644 > --- a/lib/intel_allocator.c > +++ b/lib/intel_allocator.c > @@ -64,8 +64,10 @@ struct handle_entry { > struct allocator *al; > }; > > -struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); > -struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); > +struct intel_allocator * > +intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); > +struct intel_allocator * > +intel_allocator_random_create(int fd, uint64_t start, uint64_t end); > struct intel_allocator * > intel_allocator_simple_create(int fd, uint64_t start, uint64_t end, > enum allocator_strategy strategy); > @@ -291,10 +293,10 @@ static struct intel_allocator *intel_allocator_create(int fd, > "We cannot use NONE allocator\n"); > break; > case INTEL_ALLOCATOR_RELOC: > - ial = intel_allocator_reloc_create(fd, end); > + ial = intel_allocator_reloc_create(fd, start, end); > break; > case INTEL_ALLOCATOR_RANDOM: > - ial = intel_allocator_random_create(fd, end); > + ial = intel_allocator_random_create(fd, start, end); > break; > case INTEL_ALLOCATOR_SIMPLE: > ial = intel_allocator_simple_create(fd, start, end, > @@ -1078,10 +1080,12 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, > .allocator_handle = allocator_handle, > .alloc.handle = handle, > .alloc.size = size, > - .alloc.alignment = alignment, > .alloc.strategy = strategy }; > struct alloc_resp resp; > > + igt_assert((alignment & (alignment-1)) == 0); > + req.alloc.alignment = max(alignment, 1 << 12); > + > igt_assert(handle_request(&req, &resp) == 0); > igt_assert(resp.response_type == RESP_ALLOC); > > diff --git a/lib/intel_allocator_random.c b/lib/intel_allocator_random.c > index 85ac2cf4e..1d2969618 100644 > --- a/lib/intel_allocator_random.c > +++ b/lib/intel_allocator_random.c > @@ -10,12 +10,12 @@ > #include "igt_rand.h" > #include "intel_allocator.h" > > -struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end); > +struct intel_allocator * > +intel_allocator_random_create(int fd, uint64_t start, uint64_t end); > > struct intel_allocator_random { > - uint64_t bias; > uint32_t prng; > - uint64_t address_mask; > + uint64_t size_mask; > uint64_t start; > uint64_t end; > > @@ -23,6 +23,7 @@ struct intel_allocator_random { > uint64_t allocated_objects; > }; > > +/* Keep the low 256k clear, for negative deltas */ > #define BIAS 256 << 10 > #define RETRIES 8 > static void intel_allocator_random_get_address_range(struct intel_allocator *ial, > @@ -45,16 +46,22 @@ static uint64_t intel_allocator_random_alloc(struct intel_allocator *ial, > { > struct intel_allocator_random *ialr = ial->priv; > uint64_t offset; > + int cnt = 0; int cnt = RETRIES; > > (void) handle; > (void) strategy; > > /* randomize the address, we try to avoid relocations */ > do { > + /* the object won't fit in the address range */ > + if (cnt > 3) return ALLOC_INVALID_ADDRESS; > + > offset = hars_petruska_f54_1_random64(&ialr->prng); > - offset += ialr->bias; /* Keep the low 256k clear, for negative deltas */ > - offset &= ialr->address_mask; > - offset &= ~(alignment - 1); > + if (cnt++ == 3) offset = 0; > + > + offset &= ialr->size_mask; > + offset += ialr->start; > + offset = ALIGN(offset, alignment); > } while (offset + size > ialr->end); Maybe: /* We won't fit at all */ if (size > ialr->end - ialr->start) return ALLOC_INVALID_ADDRESS; do { offset = hars_petruska_f54_1_random64(&ialr->prng); offset &= ialr->size_mask; offset += ialr->start; offset = ALIGN(offset, alignment); } while (offset + size > ialr->end && cnt--); if (!cnt) return ALLOC_INVALID_ADDRESS; will be more readable? > > ialr->allocated_objects++; > @@ -145,7 +152,8 @@ static bool intel_allocator_random_is_empty(struct intel_allocator *ial) > return !ialr->allocated_objects; > } > > -struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end) > +struct intel_allocator * > +intel_allocator_random_create(int fd, uint64_t start, uint64_t end) > { > struct intel_allocator *ial; > struct intel_allocator_random *ialr; > @@ -170,10 +178,10 @@ struct intel_allocator *intel_allocator_random_create(int fd, uint64_t end) > igt_assert(ial->priv); > ialr->prng = (uint32_t) to_user_pointer(ial); > > - igt_assert(BIAS < end); > - ialr->address_mask = (1ULL << (igt_fls(end) - 1)) - 1; > - ialr->bias = BIAS; > - ialr->start = ialr->bias; > + start = max(start, BIAS); > + igt_assert(start < end); > + ialr->size_mask = (1ULL << (igt_fls(end - start) - 1)) - 1; > + ialr->start = start; > ialr->end = end; No, mask will be invalid in this case. -- Zbigniew > > ialr->allocated_objects = 0; > diff --git a/lib/intel_allocator_reloc.c b/lib/intel_allocator_reloc.c > index 703d054c6..24b2aeebc 100644 > --- a/lib/intel_allocator_reloc.c > +++ b/lib/intel_allocator_reloc.c > @@ -10,10 +10,10 @@ > #include "igt_rand.h" > #include "intel_allocator.h" > > -struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end); > +struct intel_allocator * > +intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); > > struct intel_allocator_reloc { > - uint64_t bias; > uint32_t prng; > uint64_t start; > uint64_t end; > @@ -23,6 +23,7 @@ struct intel_allocator_reloc { > uint64_t allocated_objects; > }; > > +/* Keep the low 256k clear, for negative deltas */ > #define BIAS 256 << 10 > > static void intel_allocator_reloc_get_address_range(struct intel_allocator *ial, > @@ -49,13 +50,16 @@ static uint64_t intel_allocator_reloc_alloc(struct intel_allocator *ial, > (void) handle; > (void) strategy; > > - alignment = max(alignment, 4096); > aligned_offset = ALIGN(ialr->offset, alignment); > > /* Check we won't exceed end */ > if (aligned_offset + size > ialr->end) > aligned_offset = ALIGN(ialr->start, alignment); > > + /* Check that the object fits in the address range */ > + if (aligned_offset + size > ialr->end) > + return ALLOC_INVALID_ADDRESS; > + > offset = aligned_offset; > ialr->offset = offset + size; > ialr->allocated_objects++; > @@ -146,7 +150,8 @@ static bool intel_allocator_reloc_is_empty(struct intel_allocator *ial) > return !ialr->allocated_objects; > } > > -struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end) > +struct intel_allocator * > +intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end) > { > struct intel_allocator *ial; > struct intel_allocator_reloc *ialr; > @@ -171,8 +176,9 @@ struct intel_allocator *intel_allocator_reloc_create(int fd, uint64_t end) > igt_assert(ial->priv); > ialr->prng = (uint32_t) to_user_pointer(ial); > > - ialr->bias = ialr->offset = BIAS; > - ialr->start = ialr->bias; > + start = max(start, BIAS); > + igt_assert(start < end); > + ialr->offset = ialr->start = start; > ialr->end = end; > > ialr->allocated_objects = 0; > diff --git a/lib/intel_allocator_simple.c b/lib/intel_allocator_simple.c > index 6022e832b..0e6763964 100644 > --- a/lib/intel_allocator_simple.c > +++ b/lib/intel_allocator_simple.c > @@ -419,7 +419,6 @@ static uint64_t intel_allocator_simple_alloc(struct intel_allocator *ial, > ials = (struct intel_allocator_simple *) ial->priv; > igt_assert(ials); > igt_assert(handle); > - alignment = alignment > 0 ? alignment : 1; > > rec = igt_map_search(ials->objects, &handle); > if (rec) { > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Fix the multiprocess mode of intel allocator 2021-06-09 13:15 [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko ` (2 preceding siblings ...) 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 3/3] lib/intel_allocator: Add support for regions of allocation Andrzej Turko @ 2021-06-09 14:22 ` Patchwork 2021-06-09 16:10 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-06-09 14:22 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 6030 bytes --] == Series Details == Series: Fix the multiprocess mode of intel allocator URL : https://patchwork.freedesktop.org/series/91250/ State : success == Summary == CI Bug Log - changes from CI_DRM_10196 -> IGTPW_5905 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/index.html Known issues ------------ Here are the changes found in IGTPW_5905 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][1] ([i915#1888]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [DMESG-WARN][3] ([i915#2868]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html #### Warnings #### * igt@i915_selftest@live@execlists: - fi-icl-u2: [DMESG-FAIL][5] ([i915#3462]) -> [INCOMPLETE][6] ([i915#2782] / [i915#3462]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-icl-u2/igt@i915_selftest@live@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-icl-u2/igt@i915_selftest@live@execlists.html - fi-tgl-u2: [INCOMPLETE][7] ([i915#3462]) -> [DMESG-FAIL][8] ([i915#3462]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-tgl-u2/igt@i915_selftest@live@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-tgl-u2/igt@i915_selftest@live@execlists.html * igt@runner@aborted: - fi-kbl-x1275: [FAIL][9] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][10] ([i915#1436] / [i915#3363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-kbl-x1275/igt@runner@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-kbl-x1275/igt@runner@aborted.html - fi-icl-u2: [FAIL][11] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][12] ([i915#2782] / [i915#3363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-icl-u2/igt@runner@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-icl-u2/igt@runner@aborted.html - fi-glk-dsi: [FAIL][13] ([i915#3363] / [k.org#202321]) -> [FAIL][14] ([i915#2426] / [i915#3363] / [k.org#202321]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-glk-dsi/igt@runner@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-glk-dsi/igt@runner@aborted.html - fi-bdw-5557u: [FAIL][15] ([i915#2426] / [i915#3462]) -> [FAIL][16] ([i915#3462]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-bdw-5557u/igt@runner@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-bdw-5557u/igt@runner@aborted.html - fi-kbl-soraka: [FAIL][17] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#3363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-kbl-soraka/igt@runner@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-kbl-soraka/igt@runner@aborted.html - fi-kbl-7500u: [FAIL][19] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][20] ([i915#1436] / [i915#3363]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-kbl-7500u/igt@runner@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/fi-kbl-7500u/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276 [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542 [i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (44 -> 41) ------------------------------ Additional (1): fi-rkl-11500t Missing (4): fi-ilk-m540 fi-dg1-1 fi-bdw-samus fi-hsw-4200u Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_6103 -> IGTPW_5905 CI-20190529: 20190529 CI_DRM_10196: 1588f8e61fe15d12826ca07d41c0a108a26006cc @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5905: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/index.html IGT_6103: 3aa79e55e73d4a49a5222e5dfde486b800a29fe7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/index.html [-- Attachment #1.2: Type: text/html, Size: 7686 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Fix the multiprocess mode of intel allocator 2021-06-09 13:15 [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko ` (3 preceding siblings ...) 2021-06-09 14:22 ` [igt-dev] ✓ Fi.CI.BAT: success for Fix the multiprocess mode of intel allocator Patchwork @ 2021-06-09 16:10 ` Patchwork 4 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-06-09 16:10 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 30261 bytes --] == Series Details == Series: Fix the multiprocess mode of intel allocator URL : https://patchwork.freedesktop.org/series/91250/ State : success == Summary == CI Bug Log - changes from CI_DRM_10196_full -> IGTPW_5905_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/index.html New tests --------- New tests have been introduced between CI_DRM_10196_full and IGTPW_5905_full: ### New IGT tests (3) ### * igt@api_intel_allocator@random-allocator@multiprocess: - Statuses : 5 pass(s) - Exec time: [0.01, 0.04] s * igt@api_intel_allocator@reloc-allocator@multiprocess: - Statuses : 4 pass(s) - Exec time: [0.01, 0.03] s * igt@api_intel_allocator@simple-allocator@multiprocess: - Statuses : 4 pass(s) - Exec time: [0.01, 0.04] s Known issues ------------ Here are the changes found in IGTPW_5905_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl8/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2410]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-tglb6/igt@gem_eio@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb1/igt@gem_eio@unwedge-stress.html - shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#2481] / [i915#3070]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb8/igt@gem_eio@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb7/igt@gem_eio@unwedge-stress.html - shard-snb: NOTRUN -> [FAIL][9] ([i915#3354]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-snb5/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html - shard-glk: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk1/igt@gem_exec_fair@basic-none-rrul@rcs0.html - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk8/igt@gem_exec_fair@basic-none-share@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][20] -> [SKIP][21] ([fdo#109271]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271]) +483 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-snb5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109283]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb1/igt@gem_exec_params@no-vebox.html * igt@gem_exec_params@rsvd2-dirt: - shard-tglb: NOTRUN -> [SKIP][24] ([fdo#109283]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb1/igt@gem_exec_params@rsvd2-dirt.html * igt@gem_exec_whisper@basic-fds: - shard-glk: NOTRUN -> [DMESG-WARN][25] ([i915#118] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk8/igt@gem_exec_whisper@basic-fds.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2190]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl1/igt@gem_huc_copy@huc-copy.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][27] ([i915#284]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb7/igt@gem_media_vme.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-glk: [PASS][28] -> [FAIL][29] ([i915#307]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk8/igt@gem_mmap_gtt@cpuset-big-copy-xy.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk8/igt@gem_mmap_gtt@cpuset-big-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][30] ([i915#2658]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb2/igt@gem_pwrite@basic-exhaustion.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-apl8/igt@gem_softpin@noreloc-s3.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl3/igt@gem_softpin@noreloc-s3.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][33] ([i915#3002]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-snb2/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@unsync-unmap-after-close: - shard-tglb: NOTRUN -> [SKIP][34] ([i915#3297]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb5/igt@gem_userptr_blits@unsync-unmap-after-close.html - shard-iclb: NOTRUN -> [SKIP][35] ([i915#3297]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb1/igt@gem_userptr_blits@unsync-unmap-after-close.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][36] ([i915#2724]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-snb6/igt@gem_userptr_blits@vma-merge.html - shard-apl: NOTRUN -> [FAIL][37] ([i915#3318]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl1/igt@gem_userptr_blits@vma-merge.html - shard-iclb: NOTRUN -> [FAIL][38] ([i915#3318]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb5/igt@gem_userptr_blits@vma-merge.html - shard-glk: NOTRUN -> [FAIL][39] ([i915#3318]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk4/igt@gem_userptr_blits@vma-merge.html - shard-kbl: NOTRUN -> [FAIL][40] ([i915#3318]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl1/igt@gem_userptr_blits@vma-merge.html - shard-tglb: NOTRUN -> [FAIL][41] ([i915#3318]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb2/igt@gem_userptr_blits@vma-merge.html * igt@gen7_exec_parse@bitmasks: - shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109289]) +6 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@gen7_exec_parse@bitmasks.html * igt@gen9_exec_parse@allowed-all: - shard-iclb: NOTRUN -> [SKIP][43] ([fdo#112306]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb7/igt@gen9_exec_parse@allowed-all.html * igt@gen9_exec_parse@bb-large: - shard-apl: NOTRUN -> [FAIL][44] ([i915#3296]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl6/igt@gen9_exec_parse@bb-large.html * igt@gen9_exec_parse@cmd-crossing-page: - shard-tglb: NOTRUN -> [SKIP][45] ([fdo#112306]) +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb6/igt@gen9_exec_parse@cmd-crossing-page.html * igt@i915_hangman@engine-error@vecs0: - shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271]) +202 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl6/igt@i915_hangman@engine-error@vecs0.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][47] ([i915#454]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_rc6_residency@media-rc6-accuracy: - shard-tglb: NOTRUN -> [SKIP][48] ([fdo#109289] / [fdo#111719]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb6/igt@i915_pm_rc6_residency@media-rc6-accuracy.html * igt@i915_pm_rpm@gem-mmap-type: - shard-iclb: NOTRUN -> [SKIP][49] ([i915#579]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@i915_pm_rpm@gem-mmap-type.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-iclb: NOTRUN -> [SKIP][50] ([fdo#110892]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@i915_pm_rpm@modeset-non-lpsp-stress.html * igt@i915_query@query-topology-known-pci-ids: - shard-tglb: NOTRUN -> [SKIP][51] ([fdo#109303]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb5/igt@i915_query@query-topology-known-pci-ids.html - shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109303]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb2/igt@i915_query@query-topology-known-pci-ids.html * igt@kms_big_fb@linear-32bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][53] ([fdo#110725] / [fdo#111614]) +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb5/igt@kms_big_fb@linear-32bpp-rotate-90.html - shard-tglb: NOTRUN -> [SKIP][54] ([fdo#111614]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb2/igt@kms_big_fb@linear-32bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-0: - shard-iclb: NOTRUN -> [SKIP][55] ([fdo#110723]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html * igt@kms_chamelium@dp-hpd-storm-disable: - shard-glk: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +6 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk5/igt@kms_chamelium@dp-hpd-storm-disable.html * igt@kms_chamelium@hdmi-hpd-for-each-pipe: - shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +17 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl3/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html * igt@kms_chamelium@vga-hpd-without-ddc: - shard-snb: NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +26 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-snb6/igt@kms_chamelium@vga-hpd-without-ddc.html * igt@kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +25 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl7/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue: - shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +8 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb1/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html * igt@kms_color_chamelium@pipe-d-ctm-limited-range: - shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb5/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue: - shard-tglb: NOTRUN -> [SKIP][62] ([fdo#109284] / [fdo#111827]) +6 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb5/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][63] ([i915#1319]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl8/igt@kms_content_protection@atomic-dpms.html - shard-kbl: NOTRUN -> [TIMEOUT][64] ([i915#1319]) +2 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl4/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@content_type_change: - shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109300] / [fdo#111066]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@kms_content_protection@content_type_change.html * igt@kms_content_protection@uevent: - shard-kbl: NOTRUN -> [FAIL][66] ([i915#2105]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl2/igt@kms_content_protection@uevent.html - shard-apl: NOTRUN -> [FAIL][67] ([i915#2105]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl6/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen: - shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109279] / [i915#3359]) +1 similar issue [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html - shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109278] / [fdo#109279]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen: - shard-tglb: NOTRUN -> [SKIP][70] ([i915#3319]) +2 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding: - shard-tglb: NOTRUN -> [SKIP][71] ([i915#3359]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-32x10-offscreen: - shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109278]) +21 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb4/igt@kms_cursor_crc@pipe-d-cursor-32x10-offscreen.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109274] / [fdo#109278]) +3 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109349]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html - shard-tglb: NOTRUN -> [CRASH][75] ([i915#3494]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html * igt@kms_flip@2x-nonexisting-fb: - shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109274]) +4 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb1/igt@kms_flip@2x-nonexisting-fb.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][77] -> [DMESG-WARN][78] ([i915#180]) +3 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2672]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2642]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][81] ([fdo#111615]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb3/igt@kms_flip_tiling@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff: - shard-tglb: NOTRUN -> [SKIP][82] ([fdo#111825]) +17 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt: - shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109280]) +19 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render: - shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271]) +44 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html * igt@kms_hdr@static-toggle-dpms: - shard-tglb: NOTRUN -> [SKIP][85] ([i915#1187]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb7/igt@kms_hdr@static-toggle-dpms.html - shard-iclb: NOTRUN -> [SKIP][86] ([i915#1187]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb4/igt@kms_hdr@static-toggle-dpms.html * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c: - shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109289]) +3 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb3/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html * igt@kms_pipe_crc_basic@read-crc-pipe-d: - shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#533]) +1 similar issue [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-apl: NOTRUN -> [FAIL][89] ([fdo#108145] / [i915#265]) +5 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-kbl: NOTRUN -> [FAIL][90] ([fdo#108145] / [i915#265]) +4 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html * igt@kms_plane_lowres@pipe-b-tiling-x: - shard-iclb: NOTRUN -> [SKIP][91] ([i915#3536]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb2/igt@kms_plane_lowres@pipe-b-tiling-x.html * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping: - shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2733]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658]) +5 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-3: - shard-iclb: NOTRUN -> [SKIP][94] ([i915#658]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html - shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#658]) +3 similar issues [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html - shard-glk: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#658]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk8/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html - shard-tglb: NOTRUN -> [SKIP][97] ([i915#2920]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html * igt@kms_psr2_su@page_flip: - shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109642] / [fdo#111068] / [i915#658]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb4/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][99] -> [SKIP][100] ([fdo#109441]) +4 similar issues [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: NOTRUN -> [FAIL][101] ([i915#132] / [i915#3467]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb5/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_sysfs_edid_timing: - shard-apl: NOTRUN -> [FAIL][102] ([IGT#2]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl1/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271]) +276 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl7/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@nouveau_crc@pipe-c-ctx-flip-detection: - shard-tglb: NOTRUN -> [SKIP][104] ([i915#2530]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb7/igt@nouveau_crc@pipe-c-ctx-flip-detection.html * igt@nouveau_crc@pipe-c-source-rg: - shard-iclb: NOTRUN -> [SKIP][105] ([i915#2530]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb4/igt@nouveau_crc@pipe-c-source-rg.html * igt@prime_nv_api@i915_nv_double_import: - shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109291]) +2 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb6/igt@prime_nv_api@i915_nv_double_import.html * igt@prime_nv_pcopy@test2: - shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109291]) +2 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb8/igt@prime_nv_pcopy@test2.html * igt@sysfs_clients@sema-25: - shard-iclb: NOTRUN -> [SKIP][108] ([i915#2994]) +1 similar issue [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb3/igt@sysfs_clients@sema-25.html * igt@sysfs_clients@sema-50: - shard-apl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994]) +3 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl1/igt@sysfs_clients@sema-50.html * igt@sysfs_clients@split-10: - shard-tglb: NOTRUN -> [SKIP][110] ([i915#2994]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb1/igt@sysfs_clients@split-10.html - shard-glk: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk5/igt@sysfs_clients@split-10.html * igt@sysfs_clients@split-50: - shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994]) +1 similar issue [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl3/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][113] ([i915#2846]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk6/igt@gem_exec_fair@basic-deadline.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk2/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [FAIL][115] ([i915#2842]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-glk: [FAIL][117] ([i915#2842]) -> [PASS][118] +2 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk5/igt@gem_exec_fair@basic-pace@vecs0.html - shard-tglb: [FAIL][119] ([i915#2842]) -> [PASS][120] [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-tglb1/igt@gem_exec_fair@basic-pace@vecs0.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-tglb3/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_whisper@basic-fds-all: - shard-glk: [DMESG-WARN][121] ([i915#118] / [i915#95]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk5/igt@gem_exec_whisper@basic-fds-all.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk1/igt@gem_exec_whisper@basic-fds-all.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-iclb: [INCOMPLETE][123] ([i915#1895]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb6/igt@gem_exec_whisper@basic-queues-forked-all.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb3/igt@gem_exec_whisper@basic-queues-forked-all.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-iclb: [FAIL][125] ([i915#307]) -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [FAIL][127] ([i915#2428]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-xy.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-xy.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [FAIL][129] ([i915#644]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [DMESG-WARN][131] ([i915#180]) -> [PASS][132] +6 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html - shard-apl: [DMESG-WARN][133] ([i915#180]) -> [PASS][134] +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-kbl: [FAIL][135] ([fdo#108145] / [i915#265]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][137] ([fdo#109441]) -> [PASS][138] +1 similar issue [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_vblank@pipe-a-accuracy-idle: - shard-glk: [FAIL][139] ([i915#43]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/shard-glk1/igt@kms_vblank@pipe-a-accuracy-idle.html == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5905/index.html [-- Attachment #1.2: Type: text/html, Size: 33943 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator
@ 2021-06-09 12:59 Andrzej Turko
2021-06-09 12:59 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko
0 siblings, 1 reply; 11+ messages in thread
From: Andrzej Turko @ 2021-06-09 12:59 UTC (permalink / raw)
To: igt-dev
In the multiprocess mode all requests to the allocator are
processed in the parent. However, in certain scenarios
(for example gem_exec_capture@pi), a child process may want
to create an allocator instance using its own private file
desriptor. Thus all ioctls used to determine available gtt size
must be called in the child process and not in the parent.
This patch implements the above change.
v2: Test allocators for private and shared contexts in
multiprocess mode.
v3: Prepare all allocator implementations for supporting
region-based memory management.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Andrzej Turko (3):
tests/i915/api_intel_allocator: Exercise allocator in multiprocess
mode
lib/intel_allocator: Move the ioctl calls to client processes
lib/intel_allocator: Add support for regions of allocation
lib/intel_allocator.c | 54 +++++++++++++++++++++++---------
lib/intel_allocator_random.c | 44 +++++++++++++-------------
lib/intel_allocator_reloc.c | 35 +++++++++------------
lib/intel_allocator_simple.c | 45 +++-----------------------
tests/i915/api_intel_allocator.c | 47 +++++++++++++++++++++++++++
5 files changed, 129 insertions(+), 96 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 11+ messages in thread* [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode 2021-06-09 12:59 [igt-dev] [PATCH v4 i-g-t 0/3] " Andrzej Turko @ 2021-06-09 12:59 ` Andrzej Turko 0 siblings, 0 replies; 11+ messages in thread From: Andrzej Turko @ 2021-06-09 12:59 UTC (permalink / raw) To: igt-dev Test creation and usage of allocators in multiprocess mode for contexts shared with the parent process as well as private for the child. This new test discovers a bug in the allocator implementation: allocator is not correctly initialized if it is opened by a child process using its private file descriptor. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/api_intel_allocator.c | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c index ea4ba8bb1..b43467a33 100644 --- a/tests/i915/api_intel_allocator.c +++ b/tests/i915/api_intel_allocator.c @@ -621,6 +621,50 @@ static void execbuf_with_allocator(int fd) igt_assert(intel_allocator_close(ahnd) == true); } +static void multiprocess(int fd, uint8_t type) { + uint64_t p_ahnd, sh_ahnd, fd_ahnd, ctx_ahnd; + uint64_t sh_left, sh_right, fd_left, fd_right; + uint64_t offset; + + intel_allocator_multiprocess_start(); + + p_ahnd = intel_allocator_open(fd, 0, type); + offset = intel_allocator_alloc(p_ahnd, 1, 123, 0); + if (type == INTEL_ALLOCATOR_SIMPLE) + igt_assert(intel_allocator_is_allocated(p_ahnd, 1, 123, offset)); + + igt_fork(child, 1) { + + sh_ahnd = intel_allocator_open(fd, 0, type); + if (type == INTEL_ALLOCATOR_SIMPLE) + igt_assert(intel_allocator_is_allocated(sh_ahnd, 1, 123, offset)); + + ctx_ahnd = intel_allocator_open(fd, 1, type); + igt_assert(!intel_allocator_is_allocated(ctx_ahnd, 1, 123, offset)); + intel_allocator_alloc(ctx_ahnd, 2, 123, 0); + + fd = gem_reopen_driver(fd); + fd_ahnd = intel_allocator_open(fd, 0, type); + igt_assert(!intel_allocator_is_allocated(fd_ahnd, 1, 123, offset)); + intel_allocator_alloc(fd_ahnd, 2, 123, 0); + + + intel_allocator_get_address_range(sh_ahnd, &sh_left, &sh_right); + intel_allocator_get_address_range(fd_ahnd, &fd_left, &fd_right); + igt_assert(sh_left == fd_left && sh_right == fd_right); + + intel_allocator_close(sh_ahnd); + intel_allocator_close(ctx_ahnd); + intel_allocator_close(fd_ahnd); + + } + + igt_waitchildren(); + intel_allocator_close(p_ahnd); + + intel_allocator_multiprocess_stop(); +} + struct allocators { const char *name; uint8_t type; @@ -672,6 +716,9 @@ igt_main igt_dynamic("reserve") reserve(fd, a->type); } + + igt_dynamic("multiprocess") + multiprocess(fd, a->type); } } -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t v3 0/3] Fix the multiprocess mode of intel allocator
@ 2021-05-27 19:27 Andrzej Turko
2021-05-27 19:27 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko
0 siblings, 1 reply; 11+ messages in thread
From: Andrzej Turko @ 2021-05-27 19:27 UTC (permalink / raw)
To: igt-dev
In the multiprocess mode all requests to the allocator are
processed in the parent. However, in certain scenarios
(for example gem_exec_capture@pi), a child process may want
to create an allocator instance using its own private file
desriptor. Thus all ioctls used to determine available gtt size
must be called in the child process and not in the parent.
This patch implements the above change.
v2: Test allocators for private and shared contexts in
multiprocess mode.
v3: Prepare all allocator implementations for supporting
region-based memory management.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Andrzej Turko (3):
tests/i915/api_intel_allocator: Exercise allocator in multiprocess
mode
lib/intel_allocator: Move the ioctl calls to client processes
lib/intel_allocator: Add support for regions of allocation
lib/intel_allocator.c | 54 +++++++++++++++++++++++---------
lib/intel_allocator_random.c | 44 +++++++++++++-------------
lib/intel_allocator_reloc.c | 35 +++++++++------------
lib/intel_allocator_simple.c | 45 +++-----------------------
tests/i915/api_intel_allocator.c | 47 +++++++++++++++++++++++++++
5 files changed, 129 insertions(+), 96 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 11+ messages in thread* [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode 2021-05-27 19:27 [igt-dev] [PATCH i-g-t v3 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko @ 2021-05-27 19:27 ` Andrzej Turko 0 siblings, 0 replies; 11+ messages in thread From: Andrzej Turko @ 2021-05-27 19:27 UTC (permalink / raw) To: igt-dev Test creation and usage of allocators in multiprocess mode for contexts shared with the parent process as well as private for the child. This new test discovers a bug in the allocator implementation: allocator is not correctly initialized if it is opened by a child process using its private file descriptor. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/api_intel_allocator.c | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c index 182d9ba79..b4f7799e7 100644 --- a/tests/i915/api_intel_allocator.c +++ b/tests/i915/api_intel_allocator.c @@ -620,6 +620,50 @@ static void execbuf_with_allocator(int fd) igt_assert(intel_allocator_close(ahnd) == true); } +static void multiprocess(int fd, uint8_t type) { + uint64_t p_ahnd, sh_ahnd, fd_ahnd, ctx_ahnd; + uint64_t sh_left, sh_right, fd_left, fd_right; + uint64_t offset; + + intel_allocator_multiprocess_start(); + + p_ahnd = intel_allocator_open(fd, 0, type); + offset = intel_allocator_alloc(p_ahnd, 1, 123, 0); + if (type == INTEL_ALLOCATOR_SIMPLE) + igt_assert(intel_allocator_is_allocated(p_ahnd, 1, 123, offset)); + + igt_fork(child, 1) { + + sh_ahnd = intel_allocator_open(fd, 0, type); + if (type == INTEL_ALLOCATOR_SIMPLE) + igt_assert(intel_allocator_is_allocated(sh_ahnd, 1, 123, offset)); + + ctx_ahnd = intel_allocator_open(fd, 1, type); + igt_assert(!intel_allocator_is_allocated(ctx_ahnd, 1, 123, offset)); + intel_allocator_alloc(ctx_ahnd, 2, 123, 0); + + fd = gem_reopen_driver(fd); + fd_ahnd = intel_allocator_open(fd, 0, type); + igt_assert(!intel_allocator_is_allocated(fd_ahnd, 1, 123, offset)); + intel_allocator_alloc(fd_ahnd, 2, 123, 0); + + + intel_allocator_get_address_range(sh_ahnd, &sh_left, &sh_right); + intel_allocator_get_address_range(fd_ahnd, &fd_left, &fd_right); + igt_assert(sh_left == fd_left && sh_right == fd_right); + + intel_allocator_close(sh_ahnd); + intel_allocator_close(ctx_ahnd); + intel_allocator_close(fd_ahnd); + + } + + igt_waitchildren(); + intel_allocator_close(p_ahnd); + + intel_allocator_multiprocess_stop(); +} + struct allocators { const char *name; uint8_t type; @@ -671,6 +715,9 @@ igt_main igt_dynamic("reserve") reserve(fd, a->type); } + + igt_dynamic("multiprocess") + multiprocess(fd, a->type); } } -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-06-11 8:57 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-09 13:15 [igt-dev] [PATCH v4 i-g-t 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko 2021-06-11 8:15 ` Zbigniew Kempczyński 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 2/3] lib/intel_allocator: Move the ioctl calls to client processes Andrzej Turko 2021-06-11 8:24 ` Zbigniew Kempczyński 2021-06-09 13:15 ` [igt-dev] [PATCH i-g-t 3/3] lib/intel_allocator: Add support for regions of allocation Andrzej Turko 2021-06-11 8:57 ` Zbigniew Kempczyński 2021-06-09 14:22 ` [igt-dev] ✓ Fi.CI.BAT: success for Fix the multiprocess mode of intel allocator Patchwork 2021-06-09 16:10 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2021-06-09 12:59 [igt-dev] [PATCH v4 i-g-t 0/3] " Andrzej Turko 2021-06-09 12:59 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko 2021-05-27 19:27 [igt-dev] [PATCH i-g-t v3 0/3] Fix the multiprocess mode of intel allocator Andrzej Turko 2021-05-27 19:27 ` [igt-dev] [PATCH i-g-t 1/3] tests/i915/api_intel_allocator: Exercise allocator in multiprocess mode Andrzej Turko
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