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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 12/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
Date: Mon, 14 Jun 2021 16:09:22 +0100	[thread overview]
Message-ID: <20210614151007.4545-13-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210614151007.4545-1-peter.maydell@linaro.org>

Implement the variants of MVE VLDR (encodings T1, T2) which perform
"widening" loads where bytes or halfwords are loaded from memory and
zero or sign-extended into halfword or word length vector elements,
and the narrowing MVE VSTR (encodings T1, T2) where bytes or
halfwords are stored from halfword or word elements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 25 +++++++++++++++++++++++--
 target/arm/mve_helper.c    | 11 +++++++++++
 target/arm/translate-mve.c | 14 ++++++++++++++
 4 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 9e3b0b09afd..e47d4164ae7 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -22,3 +22,13 @@ DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vldrh_sw, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vldrh_uw, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 858a161fd7e..3bc5f034531 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -21,12 +21,33 @@
 
 %qd 22:1 13:3
 
-&vldr_vstr rn qd imm p a w size l
+&vldr_vstr rn qd imm p a w size l u
 
-@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd
+@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
+# Note that both Rn and Qd are 3 bits only (no D bit)
+@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr
 
 # Vector loads and stores
 
+# Widening loads and narrowing stores:
+# for these P=0 W=0 is 'related encoding'; sz=11 is 'related encoding'
+# This means we need to expand out to multiple patterns for P, W, SZ.
+# For stores the U bit must be 0 but we catch that in the trans_ function.
+# The naming scheme here is "VLDSTB_H == in-memory byte load/store to/from
+# signed halfword element in register", etc.
+VLDSTB_H         111 . 110 0 a:1 0 1   . 0 ... ... 0 111 01 ....... @vldst_wn \
+                 p=0 w=1 size=1
+VLDSTB_H         111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst_wn \
+                 p=1 size=1
+VLDSTB_W         111 . 110 0 a:1 0 1   . 0 ... ... 0 111 10 ....... @vldst_wn \
+                 p=0 w=1 size=2
+VLDSTB_W         111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst_wn \
+                 p=1 size=2
+VLDSTH_W         111 . 110 0 a:1 0 1   . 1 ... ... 0 111 10 ....... @vldst_wn \
+                 p=0 w=1 size=2
+VLDSTH_W         111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst_wn \
+                 p=1 size=2
+
 # Non-widening loads/stores (P=0 W=0 is 'related encoding')
 VLDR_VSTR        1110110 0 a:1 . 1   . .... ... 111100 .......   @vldr_vstr \
                  size=0 p=0 w=1
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index c07110a145b..7282f56b18d 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -168,5 +168,16 @@ DO_VSTR(vstrb, stb, 1, uint8_t)
 DO_VSTR(vstrh, stw, 2, uint16_t)
 DO_VSTR(vstrw, stl, 4, uint32_t)
 
+DO_VLDR(vldrb_sh, ldsb, 2, int16_t)
+DO_VLDR(vldrb_sw, ldsb, 4, int32_t)
+DO_VLDR(vldrb_uh, ldub, 2, uint16_t)
+DO_VLDR(vldrb_uw, ldub, 4, uint32_t)
+DO_VLDR(vldrh_sw, ldsw, 4, int32_t)
+DO_VLDR(vldrh_uw, lduw, 4, uint32_t)
+
+DO_VSTR(vstrb_h, stb, 2, int16_t)
+DO_VSTR(vstrb_w, stb, 4, int32_t)
+DO_VSTR(vstrh_w, stw, 4, int32_t)
+
 #undef DO_VLDR
 #undef DO_VSTR
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index f98bd6d038d..4cabdf7a69b 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -146,3 +146,17 @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
     };
     return do_ldst(s, a, ldstfns[a->size][a->l]);
 }
+
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+    static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
+    {                                                           \
+        static MVEGenLdStFn * const ldstfns[2][2] = {           \
+            { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
+            { NULL, gen_helper_mve_##ULD },                     \
+        };                                                      \
+        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+    }
+
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
-- 
2.20.1



  parent reply	other threads:[~2021-06-14 15:17 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-14 15:09 [PATCH v2 00/57] target/arm: First slice of MVE implementation Peter Maydell
2021-06-14 15:09 ` [PATCH v2 01/57] target/arm: Provide and use H8 and H1_8 macros Peter Maydell
2021-06-14 15:09 ` [PATCH v2 02/57] target/arm: Enable FPSCR.QC bit for MVE Peter Maydell
2021-06-14 15:09 ` [PATCH v2 03/57] target/arm: Handle VPR semantics in existing code Peter Maydell
2021-06-14 15:09 ` [PATCH v2 04/57] target/arm: Add handling for PSR.ECI/ICI Peter Maydell
2021-06-14 19:15   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 05/57] target/arm: Let vfp_access_check() handle late NOCP checks Peter Maydell
2021-06-14 15:09 ` [PATCH v2 06/57] target/arm: Implement MVE LCTP Peter Maydell
2021-06-14 15:09 ` [PATCH v2 07/57] target/arm: Implement MVE WLSTP insn Peter Maydell
2021-06-14 19:20   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 08/57] target/arm: Implement MVE DLSTP Peter Maydell
2021-06-14 15:09 ` [PATCH v2 09/57] target/arm: Implement MVE LETP insn Peter Maydell
2021-06-14 15:09 ` [PATCH v2 10/57] target/arm: Add framework for MVE decode Peter Maydell
2021-06-14 15:09 ` [PATCH v2 11/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Peter Maydell
2021-06-14 19:29   ` Richard Henderson
2021-06-14 15:09 ` Peter Maydell [this message]
2021-06-14 19:39   ` [PATCH v2 12/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Richard Henderson
2021-06-14 15:09 ` [PATCH v2 13/57] target/arm: Move expand_pred_b() data to translate.c Peter Maydell
2021-06-14 19:41   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 14/57] target/arm: Implement MVE VCLZ Peter Maydell
2021-06-14 20:00   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 15/57] target/arm: Implement MVE VCLS Peter Maydell
2021-06-14 15:09 ` [PATCH v2 16/57] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Peter Maydell
2021-06-14 15:09 ` [PATCH v2 17/57] target/arm: Implement MVE VREV16, VREV32, VREV64 Peter Maydell
2021-06-14 20:03   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 18/57] target/arm: Implement MVE VMVN (register) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 19/57] target/arm: Implement MVE VABS Peter Maydell
2021-06-14 20:06   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 20/57] target/arm: Implement MVE VNEG Peter Maydell
2021-06-14 15:09 ` [PATCH v2 21/57] tcg: Make gen_dup_i32() public Peter Maydell
2021-06-14 20:12   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 22/57] target/arm: Implement MVE VDUP Peter Maydell
2021-06-14 20:15   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 23/57] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Peter Maydell
2021-06-14 15:09 ` [PATCH v2 24/57] target/arm: Implement MVE VADD, VSUB, VMUL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 25/57] target/arm: Implement MVE VMULH Peter Maydell
2021-06-14 15:09 ` [PATCH v2 26/57] target/arm: Implement MVE VRMULH Peter Maydell
2021-06-14 15:09 ` [PATCH v2 27/57] target/arm: Implement MVE VMAX, VMIN Peter Maydell
2021-06-14 15:09 ` [PATCH v2 28/57] target/arm: Implement MVE VABD Peter Maydell
2021-06-14 15:09 ` [PATCH v2 29/57] target/arm: Implement MVE VHADD, VHSUB Peter Maydell
2021-06-14 15:09 ` [PATCH v2 30/57] target/arm: Implement MVE VMULL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 31/57] target/arm: Implement MVE VMLALDAV Peter Maydell
2021-06-14 15:09 ` [PATCH v2 32/57] target/arm: Implement MVE VMLSLDAV Peter Maydell
2021-06-14 15:09 ` [PATCH v2 33/57] include/qemu/int128.h: Add function to create Int128 from int64_t Peter Maydell
2021-06-14 15:09 ` [PATCH v2 34/57] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-06-14 21:27   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 35/57] target/arm: Implement MVE VADD (scalar) Peter Maydell
2021-06-14 21:30   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 36/57] target/arm: Implement MVE VSUB, VMUL (scalar) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 37/57] target/arm: Implement MVE VHADD, VHSUB (scalar) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 38/57] target/arm: Implement MVE VBRSR Peter Maydell
2021-06-14 15:09 ` [PATCH v2 39/57] target/arm: Implement MVE VPST Peter Maydell
2021-06-14 15:09 ` [PATCH v2 40/57] target/arm: Implement MVE VQADD and VQSUB Peter Maydell
2021-06-14 15:09 ` [PATCH v2 41/57] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 42/57] target/arm: Implement MVE VQDMULL scalar Peter Maydell
2021-06-14 15:09 ` [PATCH v2 43/57] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 44/57] target/arm: Implement MVE VQADD, VQSUB (vector) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 45/57] target/arm: Implement MVE VQSHL (vector) Peter Maydell
2021-06-14 21:43   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 46/57] target/arm: Implement MVE VQRSHL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 47/57] target/arm: Implement MVE VSHL insn Peter Maydell
2021-06-14 15:09 ` [PATCH v2 48/57] target/arm: Implmement MVE VRSHL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 49/57] target/arm: Implement MVE VQDMLADH and VQRDMLADH Peter Maydell
2021-06-14 15:10 ` [PATCH v2 50/57] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH Peter Maydell
2021-06-14 15:10 ` [PATCH v2 51/57] target/arm: Implement MVE VQDMULL (vector) Peter Maydell
2021-06-14 15:10 ` [PATCH v2 52/57] target/arm: Implement MVE VRHADD Peter Maydell
2021-06-14 15:10 ` [PATCH v2 53/57] target/arm: Implement MVE VADC, VSBC Peter Maydell
2021-06-14 21:58   ` Richard Henderson
2021-06-14 15:10 ` [PATCH v2 54/57] target/arm: Implement MVE VCADD Peter Maydell
2021-06-14 15:10 ` [PATCH v2 55/57] target/arm: Implement MVE VHCADD Peter Maydell
2021-06-14 22:01   ` Richard Henderson
2021-06-14 15:10 ` [PATCH v2 56/57] target/arm: Implement MVE VADDV Peter Maydell
2021-06-14 15:10 ` [PATCH v2 57/57] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Peter Maydell
2021-06-14 22:20 ` [PATCH v2 00/57] target/arm: First slice of MVE implementation no-reply
2021-06-14 22:22 ` Richard Henderson
2021-06-21 16:37   ` Peter Maydell
2021-06-21 17:13     ` Richard Henderson

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