All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 16/57] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
Date: Mon, 14 Jun 2021 16:09:26 +0100	[thread overview]
Message-ID: <20210614151007.4545-17-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210614151007.4545-1-peter.maydell@linaro.org>

Currently the ARM SVE helper code defines locally some utility
functions for swapping 16-bit halfwords within 32-bit or 64-bit
values and for swapping 32-bit words within 64-bit values,
parallel to the byte-swapping bswap16/32/64 functions.

We want these also for the ARM MVE code, and they're potentially
generally useful for other targets, so move them to bitops.h.
(We don't put them in bswap.h with the bswap* functions because
they are implemented in terms of the rotate operations also
defined in bitops.h, and including bitops.h from bswap.h seems
better avoided.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/qemu/bitops.h   | 29 +++++++++++++++++++++++++++++
 target/arm/sve_helper.c | 20 --------------------
 2 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index a72f69fea85..03213ce952c 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -291,6 +291,35 @@ static inline uint64_t ror64(uint64_t word, unsigned int shift)
     return (word >> shift) | (word << ((64 - shift) & 63));
 }
 
+/**
+ * hswap32 - swap 16-bit halfwords within a 32-bit value
+ * @h: value to swap
+ */
+static inline uint32_t hswap32(uint32_t h)
+{
+    return rol32(h, 16);
+}
+
+/**
+ * hswap64 - swap 16-bit halfwords within a 64-bit value
+ * @h: value to swap
+ */
+static inline uint64_t hswap64(uint64_t h)
+{
+    uint64_t m = 0x0000ffff0000ffffull;
+    h = rol64(h, 32);
+    return ((h & m) << 16) | ((h >> 16) & m);
+}
+
+/**
+ * wswap64 - swap 32-bit words within a 64-bit value
+ * @h: value to swap
+ */
+static inline uint64_t wswap64(uint64_t h)
+{
+    return rol64(h, 32);
+}
+
 /**
  * extract32:
  * @value: the value to extract the bit field from
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 321098e2651..dab5f1d1cda 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -152,26 +152,6 @@ static inline uint64_t expand_pred_s(uint8_t byte)
     return word[byte & 0x11];
 }
 
-/* Swap 16-bit words within a 32-bit word.  */
-static inline uint32_t hswap32(uint32_t h)
-{
-    return rol32(h, 16);
-}
-
-/* Swap 16-bit words within a 64-bit word.  */
-static inline uint64_t hswap64(uint64_t h)
-{
-    uint64_t m = 0x0000ffff0000ffffull;
-    h = rol64(h, 32);
-    return ((h & m) << 16) | ((h >> 16) & m);
-}
-
-/* Swap 32-bit words within a 64-bit word.  */
-static inline uint64_t wswap64(uint64_t h)
-{
-    return rol64(h, 32);
-}
-
 #define LOGICAL_PPPP(NAME, FUNC) \
 void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc)  \
 {                                                                         \
-- 
2.20.1



  parent reply	other threads:[~2021-06-14 15:21 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-14 15:09 [PATCH v2 00/57] target/arm: First slice of MVE implementation Peter Maydell
2021-06-14 15:09 ` [PATCH v2 01/57] target/arm: Provide and use H8 and H1_8 macros Peter Maydell
2021-06-14 15:09 ` [PATCH v2 02/57] target/arm: Enable FPSCR.QC bit for MVE Peter Maydell
2021-06-14 15:09 ` [PATCH v2 03/57] target/arm: Handle VPR semantics in existing code Peter Maydell
2021-06-14 15:09 ` [PATCH v2 04/57] target/arm: Add handling for PSR.ECI/ICI Peter Maydell
2021-06-14 19:15   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 05/57] target/arm: Let vfp_access_check() handle late NOCP checks Peter Maydell
2021-06-14 15:09 ` [PATCH v2 06/57] target/arm: Implement MVE LCTP Peter Maydell
2021-06-14 15:09 ` [PATCH v2 07/57] target/arm: Implement MVE WLSTP insn Peter Maydell
2021-06-14 19:20   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 08/57] target/arm: Implement MVE DLSTP Peter Maydell
2021-06-14 15:09 ` [PATCH v2 09/57] target/arm: Implement MVE LETP insn Peter Maydell
2021-06-14 15:09 ` [PATCH v2 10/57] target/arm: Add framework for MVE decode Peter Maydell
2021-06-14 15:09 ` [PATCH v2 11/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Peter Maydell
2021-06-14 19:29   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 12/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Peter Maydell
2021-06-14 19:39   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 13/57] target/arm: Move expand_pred_b() data to translate.c Peter Maydell
2021-06-14 19:41   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 14/57] target/arm: Implement MVE VCLZ Peter Maydell
2021-06-14 20:00   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 15/57] target/arm: Implement MVE VCLS Peter Maydell
2021-06-14 15:09 ` Peter Maydell [this message]
2021-06-14 15:09 ` [PATCH v2 17/57] target/arm: Implement MVE VREV16, VREV32, VREV64 Peter Maydell
2021-06-14 20:03   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 18/57] target/arm: Implement MVE VMVN (register) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 19/57] target/arm: Implement MVE VABS Peter Maydell
2021-06-14 20:06   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 20/57] target/arm: Implement MVE VNEG Peter Maydell
2021-06-14 15:09 ` [PATCH v2 21/57] tcg: Make gen_dup_i32() public Peter Maydell
2021-06-14 20:12   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 22/57] target/arm: Implement MVE VDUP Peter Maydell
2021-06-14 20:15   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 23/57] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Peter Maydell
2021-06-14 15:09 ` [PATCH v2 24/57] target/arm: Implement MVE VADD, VSUB, VMUL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 25/57] target/arm: Implement MVE VMULH Peter Maydell
2021-06-14 15:09 ` [PATCH v2 26/57] target/arm: Implement MVE VRMULH Peter Maydell
2021-06-14 15:09 ` [PATCH v2 27/57] target/arm: Implement MVE VMAX, VMIN Peter Maydell
2021-06-14 15:09 ` [PATCH v2 28/57] target/arm: Implement MVE VABD Peter Maydell
2021-06-14 15:09 ` [PATCH v2 29/57] target/arm: Implement MVE VHADD, VHSUB Peter Maydell
2021-06-14 15:09 ` [PATCH v2 30/57] target/arm: Implement MVE VMULL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 31/57] target/arm: Implement MVE VMLALDAV Peter Maydell
2021-06-14 15:09 ` [PATCH v2 32/57] target/arm: Implement MVE VMLSLDAV Peter Maydell
2021-06-14 15:09 ` [PATCH v2 33/57] include/qemu/int128.h: Add function to create Int128 from int64_t Peter Maydell
2021-06-14 15:09 ` [PATCH v2 34/57] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-06-14 21:27   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 35/57] target/arm: Implement MVE VADD (scalar) Peter Maydell
2021-06-14 21:30   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 36/57] target/arm: Implement MVE VSUB, VMUL (scalar) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 37/57] target/arm: Implement MVE VHADD, VHSUB (scalar) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 38/57] target/arm: Implement MVE VBRSR Peter Maydell
2021-06-14 15:09 ` [PATCH v2 39/57] target/arm: Implement MVE VPST Peter Maydell
2021-06-14 15:09 ` [PATCH v2 40/57] target/arm: Implement MVE VQADD and VQSUB Peter Maydell
2021-06-14 15:09 ` [PATCH v2 41/57] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 42/57] target/arm: Implement MVE VQDMULL scalar Peter Maydell
2021-06-14 15:09 ` [PATCH v2 43/57] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 44/57] target/arm: Implement MVE VQADD, VQSUB (vector) Peter Maydell
2021-06-14 15:09 ` [PATCH v2 45/57] target/arm: Implement MVE VQSHL (vector) Peter Maydell
2021-06-14 21:43   ` Richard Henderson
2021-06-14 15:09 ` [PATCH v2 46/57] target/arm: Implement MVE VQRSHL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 47/57] target/arm: Implement MVE VSHL insn Peter Maydell
2021-06-14 15:09 ` [PATCH v2 48/57] target/arm: Implmement MVE VRSHL Peter Maydell
2021-06-14 15:09 ` [PATCH v2 49/57] target/arm: Implement MVE VQDMLADH and VQRDMLADH Peter Maydell
2021-06-14 15:10 ` [PATCH v2 50/57] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH Peter Maydell
2021-06-14 15:10 ` [PATCH v2 51/57] target/arm: Implement MVE VQDMULL (vector) Peter Maydell
2021-06-14 15:10 ` [PATCH v2 52/57] target/arm: Implement MVE VRHADD Peter Maydell
2021-06-14 15:10 ` [PATCH v2 53/57] target/arm: Implement MVE VADC, VSBC Peter Maydell
2021-06-14 21:58   ` Richard Henderson
2021-06-14 15:10 ` [PATCH v2 54/57] target/arm: Implement MVE VCADD Peter Maydell
2021-06-14 15:10 ` [PATCH v2 55/57] target/arm: Implement MVE VHCADD Peter Maydell
2021-06-14 22:01   ` Richard Henderson
2021-06-14 15:10 ` [PATCH v2 56/57] target/arm: Implement MVE VADDV Peter Maydell
2021-06-14 15:10 ` [PATCH v2 57/57] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Peter Maydell
2021-06-14 22:20 ` [PATCH v2 00/57] target/arm: First slice of MVE implementation no-reply
2021-06-14 22:22 ` Richard Henderson
2021-06-21 16:37   ` Peter Maydell
2021-06-21 17:13     ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210614151007.4545-17-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.