* [Intel-gfx] [PATCH i-g-t 0/2] Add tests for new hw info queries
@ 2021-06-10 21:52 John.C.Harrison
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: John.C.Harrison @ 2021-06-10 21:52 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs require hardware configuration information about the
current platform. New interfaces have been added to the KMD to return
this informatio. So, add some tests for the new interfaces.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (1):
tests/i915/query: Add test for L3 bank count
Rodrigo Vivi (1):
tests/i915/query: Query, parse and validate the hwconfig table
include/drm-uapi/i915_drm.h | 2 +
lib/intel_hwconfig_types.h | 102 ++++++++++++++++++++++
tests/i915/i915_query.c | 163 ++++++++++++++++++++++++++++++++++++
3 files changed, 267 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table
2021-06-10 21:52 [Intel-gfx] [PATCH i-g-t 0/2] Add tests for new hw info queries John.C.Harrison
@ 2021-06-10 21:52 ` John.C.Harrison
2021-06-14 21:43 ` Matthew Brost
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count John.C.Harrison
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: John.C.Harrison @ 2021-06-10 21:52 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX, Slawomir Milczarek
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
All the static platform configuration per SKU is moving to
this KVL table. User Space components can query and parse
it to find the proper hw configuration instead of having
to hardcode it.
Add a query as both an example of how to fetch the table and to
validate the KLV contents as much as possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
---
include/drm-uapi/i915_drm.h | 1 +
lib/intel_hwconfig_types.h | 102 ++++++++++++++++++++++++++++
tests/i915/i915_query.c | 128 ++++++++++++++++++++++++++++++++++++
3 files changed, 231 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c3..5c34ab759 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2233,6 +2233,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_TABLE 5
/* Must be kept compact -- no holes and well documented */
/**
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000..8aa875de9
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This header defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ __INTEL_HWCONFIG_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+};
+
+#define INTEL_HWCONFIG_CACHE_TYPE_L3 BIT(0)
+#define INTEL_HWCONFIG_CACHE_TYPE_LLC BIT(1)
+#define INTEL_HWCONFIG_CACHE_TYPE_EDRAM BIT(2)
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 29b938e9c..eef4afb05 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -724,6 +725,130 @@ static void engines(int fd)
free(engines);
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ uint32_t *data;
+ int i = 0;
+ int len, j, max_words;
+
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
+ };
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ igt_require(item.length > 0);
+
+ data = malloc(item.length);
+ igt_assert(data);
+ memset(data, 0, item.length);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_info("Table size = %d bytes\n", item.length);
+ igt_assert(item.length > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = item.length / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == item.length);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
+
+ len = data[i+1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s:", data[i], hwconfig_keys[data[i]]);
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info(" %d,", data[j]);
+ igt_info(" %d\n", data[j]);
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -783,6 +908,9 @@ igt_main
engines(fd);
}
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count
2021-06-10 21:52 [Intel-gfx] [PATCH i-g-t 0/2] Add tests for new hw info queries John.C.Harrison
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2021-06-10 21:52 ` John.C.Harrison
2021-06-14 19:44 ` [igt-dev] " Matthew Brost
2021-06-10 22:33 ` [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info queries Patchwork
2021-06-11 2:34 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 1 reply; 8+ messages in thread
From: John.C.Harrison @ 2021-06-10 21:52 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs need to know the L3 bank count. So a query API has been
added for it. Test that query.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
include/drm-uapi/i915_drm.h | 1 +
tests/i915/i915_query.c | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 5c34ab759..191820532 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
#define DRM_I915_QUERY_HWCONFIG_TABLE 5
+#define DRM_I915_QUERY_L3_BANK_COUNT 6
/* Must be kept compact -- no holes and well documented */
/**
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index eef4afb05..17948e0d8 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -849,6 +849,38 @@ static void query_parse_and_validate_hwconfig_table(int i915)
free(data);
}
+static int query_engine_l3_bank_count(int fd)
+{
+ uint32_t *banks;
+ struct drm_i915_query_item size = {
+ .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
+ };
+ struct drm_i915_query_item query = {
+ .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
+ };
+ int num_counts, i;
+
+ i915_query_items(fd, &size, 1);
+ igt_require(size.length > 0);
+
+ num_counts = size.length / sizeof(*banks);
+ igt_info("size = %d, count = %d => %ld\n", size.length, num_counts, num_counts * sizeof(*banks));
+ igt_assert(size.length == (num_counts * sizeof(*banks)));
+
+ banks = malloc(size.length);
+ igt_assert(banks);
+ query.data_ptr = to_user_pointer(banks);
+ query.length = size.length;
+
+ i915_query_items(fd, &query, 1);
+ igt_assert(query.length == size.length);
+ for (i = 0; i < num_counts; i++)
+ igt_info("Bank count #%d: %d\n", i, banks[i]);
+
+ free(banks);
+ return 0;
+}
+
igt_main
{
int fd = -1;
@@ -911,6 +943,9 @@ igt_main
igt_subtest("hwconfig_table")
query_parse_and_validate_hwconfig_table(fd);
+ igt_subtest("l3_banks")
+ query_engine_l3_bank_count(fd);
+
igt_fixture {
close(fd);
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info queries
2021-06-10 21:52 [Intel-gfx] [PATCH i-g-t 0/2] Add tests for new hw info queries John.C.Harrison
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count John.C.Harrison
@ 2021-06-10 22:33 ` Patchwork
2021-06-11 2:34 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-06-10 22:33 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 5537 bytes --]
== Series Details ==
Series: Add tests for new hw info queries
URL : https://patchwork.freedesktop.org/series/91360/
State : success
== Summary ==
CI Bug Log - changes from IGT_6104 -> IGTPW_5908
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/index.html
Known issues
------------
Here are the changes found in IGTPW_5908 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-guc/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@execlists:
- fi-skl-guc: NOTRUN -> [DMESG-FAIL][2] ([i915#3462])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-guc/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-guc/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#533])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@runner@aborted:
- fi-skl-guc: NOTRUN -> [FAIL][6] ([i915#1436] / [i915#3363])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-guc/igt@runner@aborted.html
#### Warnings ####
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][7] ([i915#1436] / [i915#3363]) -> [FAIL][8] ([i915#1436] / [i915#2426] / [i915#3363])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/fi-skl-6600u/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-6600u/igt@runner@aborted.html
- fi-kbl-guc: [FAIL][9] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][10] ([i915#1436] / [i915#3363])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/fi-kbl-guc/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-kbl-guc/igt@runner@aborted.html
- fi-cml-u2: [FAIL][11] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462]) -> [FAIL][12] ([i915#3363] / [i915#3462])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/fi-cml-u2/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-cml-u2/igt@runner@aborted.html
- fi-bxt-dsi: [FAIL][13] ([i915#3363]) -> [FAIL][14] ([i915#2426] / [i915#3363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/fi-bxt-dsi/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-bxt-dsi/igt@runner@aborted.html
- fi-cfl-guc: [FAIL][15] ([i915#2426] / [i915#3363]) -> [FAIL][16] ([i915#3363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/fi-cfl-guc/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-cfl-guc/igt@runner@aborted.html
- fi-skl-6700k2: [FAIL][17] ([i915#1436] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#2426] / [i915#3363])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/fi-skl-6700k2/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/fi-skl-6700k2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (43 -> 39)
------------------------------
Additional (1): fi-skl-guc
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-dg1-1 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6104 -> IGTPW_5908
CI-20190529: 20190529
CI_DRM_10205: e3375fd2aeeb2416a8e8c8b59d106adf9c0dd938 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5908: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/index.html
IGT_6104: f8f81bd3752f3126a47d9dbba2d0ab29f7c17a19 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@i915_query@hwconfig_table
+igt@i915_query@l3_banks
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/index.html
[-- Attachment #1.2: Type: text/html, Size: 7950 bytes --]
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add tests for new hw info queries
2021-06-10 21:52 [Intel-gfx] [PATCH i-g-t 0/2] Add tests for new hw info queries John.C.Harrison
` (2 preceding siblings ...)
2021-06-10 22:33 ` [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info queries Patchwork
@ 2021-06-11 2:34 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-06-11 2:34 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 30251 bytes --]
== Series Details ==
Series: Add tests for new hw info queries
URL : https://patchwork.freedesktop.org/series/91360/
State : failure
== Summary ==
CI Bug Log - changes from IGT_6104_full -> IGTPW_5908_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5908_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5908_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5908_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_query@hwconfig_table} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb8/igt@i915_query@hwconfig_table.html
* {igt@i915_query@l3_banks} (NEW):
- shard-iclb: NOTRUN -> [SKIP][2] +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb7/igt@i915_query@l3_banks.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
- shard-glk: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk4/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
New tests
---------
New tests have been introduced between IGT_6104_full and IGTPW_5908_full:
### New IGT tests (2) ###
* igt@i915_query@hwconfig_table:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@i915_query@l3_banks:
- Statuses : 4 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_5908_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +6 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-snb6/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#3063])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-tglb3/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: NOTRUN -> [FAIL][11] ([i915#2842] / [i915#3468])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][19] ([i915#2389]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-snb6/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#307])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk4/igt@gem_mmap_gtt@cpuset-big-copy.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk8/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-snb6/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-kbl: NOTRUN -> [FAIL][23] ([i915#3318])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][24] ([fdo#112306])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb6/igt@gen9_exec_parse@cmd-crossing-page.html
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#112306])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [PASS][26] -> [SKIP][27] ([fdo#109271])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-apl8/igt@i915_pm_dc@dc9-dpms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: NOTRUN -> [DMESG-WARN][28] ([i915#180])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#2705])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb7/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][30] ([i915#2705])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@common-hpd-after-suspend:
- shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk6/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +24 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl6/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +24 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +13 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-negative:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-negative.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-iclb: NOTRUN -> [SKIP][37] ([i915#3116])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb4/igt@kms_content_protection@dp-mst-lic-type-0.html
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3116])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb5/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109300] / [fdo#111066]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb5/igt@kms_content_protection@legacy.html
- shard-kbl: NOTRUN -> [TIMEOUT][40] ([i915#1319]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl4/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111828]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb6/igt@kms_content_protection@srm.html
- shard-apl: NOTRUN -> [TIMEOUT][42] ([i915#1319]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl2/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [PASS][43] -> [DMESG-WARN][44] ([i915#180])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3359]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#3319])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-offscreen:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109278]) +6 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-32x10-offscreen.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][50] ([fdo#109271]) +330 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-snb5/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274] / [fdo#109278]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl2/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][53] -> [INCOMPLETE][54] ([i915#155] / [i915#180] / [i915#636])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109274]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
- shard-glk: [PASS][56] -> [FAIL][57] ([i915#2122])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][58] ([i915#180]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109280]) +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#111825]) +9 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271]) +37 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][62] -> [INCOMPLETE][63] ([i915#2828])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#1187])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb6/igt@kms_hdr@static-toggle-suspend.html
- shard-iclb: NOTRUN -> [SKIP][65] ([i915#1187])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb2/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][69] ([i915#265])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-apl: NOTRUN -> [FAIL][70] ([i915#265])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl7/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][71] ([fdo#111615]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb3/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271]) +138 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl1/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#658]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][76] -> [SKIP][77] ([fdo#109642] / [fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][78] -> [SKIP][79] ([fdo#109441]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][80] -> [DMESG-WARN][81] ([i915#180] / [i915#295])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271]) +193 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl6/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][83] ([i915#2530]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb8/igt@nouveau_crc@pipe-a-source-rg.html
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#2530]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb1/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][85] -> [FAIL][86] ([i915#1542])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-tglb1/igt@perf@polling-parameterized.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb6/igt@perf@polling-parameterized.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109295])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb5/igt@prime_vgem@fence-flip-hang.html
- shard-tglb: NOTRUN -> [SKIP][88] ([fdo#109295])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb7/igt@prime_vgem@fence-flip-hang.html
* igt@sysfs_clients@create:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl2/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-apl3/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@recycle-many:
- shard-glk: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk4/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][92] ([i915#2410]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][94] ([i915#2846]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk3/igt@gem_exec_fair@basic-deadline.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [FAIL][98] ([i915#2842]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl6/igt@gem_exec_fair@basic-none@vcs1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl3/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_mmap_gtt@big-copy:
- shard-glk: [FAIL][100] ([i915#307]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk2/igt@gem_mmap_gtt@big-copy.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk5/igt@gem_mmap_gtt@big-copy.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][102] ([i915#2782]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-snb2/igt@i915_selftest@live@hangcheck.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
- shard-glk: [FAIL][104] ([i915#3444]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk4/igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-glk: [DMESG-FAIL][106] ([i915#118] / [i915#95]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled:
- shard-glk: [FAIL][108] -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk3/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html
* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk: [INCOMPLETE][110] -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk1/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk3/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-glk: [FAIL][112] ([i915#49]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][116] ([fdo#109441]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: [INCOMPLETE][118] ([i915#155]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][120] ([i915#1804] / [i915#2684]) -> [WARN][121] ([i915#2684])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@execlists:
- shard-kbl: [DMESG-FAIL][122] ([i915#3462]) -> [INCOMPLETE][123] ([i915#2782] / [i915#3462] / [i915#794])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl4/igt@i915_selftest@live@execlists.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl2/igt@i915_selftest@live@execlists.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][124] ([i915#658]) -> [SKIP][125] ([i915#2920])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][126] ([i915#2920]) -> [SKIP][127] ([i915#658]) +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl1/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl4/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-kbl3/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl3/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl2/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl1/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl1/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl7/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl7/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl6/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/shard-kbl4/igt@runner@aborted.html
- shard-iclb: ([FAIL][149], [FAIL][150], [FAIL][151]) ([i915#2426] / [i915#2782] / [i915#3002]) -> ([FAIL][152], [FAIL][153], [FAIL][154]) ([i915#2782] / [i915#3002])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb1/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6104/shard-iclb5/igt@runn
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5908/index.html
[-- Attachment #1.2: Type: text/html, Size: 34051 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count John.C.Harrison
@ 2021-06-14 19:44 ` Matthew Brost
0 siblings, 0 replies; 8+ messages in thread
From: Matthew Brost @ 2021-06-14 19:44 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX
On Thu, Jun 10, 2021 at 02:52:47PM -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Various UMDs need to know the L3 bank count. So a query API has been
> added for it. Test that query.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> tests/i915/i915_query.c | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 5c34ab759..191820532 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> #define DRM_I915_QUERY_HWCONFIG_TABLE 5
> +#define DRM_I915_QUERY_L3_BANK_COUNT 6
> /* Must be kept compact -- no holes and well documented */
>
> /**
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index eef4afb05..17948e0d8 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -849,6 +849,38 @@ static void query_parse_and_validate_hwconfig_table(int i915)
> free(data);
> }
>
> +static int query_engine_l3_bank_count(int fd)
> +{
> + uint32_t *banks;
> + struct drm_i915_query_item size = {
> + .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
> + };
> + struct drm_i915_query_item query = {
> + .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
> + };
I believe you could just one of the local variables, right? I see the
comparison for 'query.length == size.length' but you store the length a
u32 rather than a struct.
Just a suggestion but not a blocker, with that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> + int num_counts, i;
> +
> + i915_query_items(fd, &size, 1);
> + igt_require(size.length > 0);
> +
> + num_counts = size.length / sizeof(*banks);
> + igt_info("size = %d, count = %d => %ld\n", size.length, num_counts, num_counts * sizeof(*banks));
> + igt_assert(size.length == (num_counts * sizeof(*banks)));
> +
> + banks = malloc(size.length);
> + igt_assert(banks);
> + query.data_ptr = to_user_pointer(banks);
> + query.length = size.length;
> +
> + i915_query_items(fd, &query, 1);
> + igt_assert(query.length == size.length);
> + for (i = 0; i < num_counts; i++)
> + igt_info("Bank count #%d: %d\n", i, banks[i]);
> +
> + free(banks);
> + return 0;
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +943,9 @@ igt_main
> igt_subtest("hwconfig_table")
> query_parse_and_validate_hwconfig_table(fd);
>
> + igt_subtest("l3_banks")
> + query_engine_l3_bank_count(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count
@ 2021-06-14 19:44 ` Matthew Brost
0 siblings, 0 replies; 8+ messages in thread
From: Matthew Brost @ 2021-06-14 19:44 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX
On Thu, Jun 10, 2021 at 02:52:47PM -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Various UMDs need to know the L3 bank count. So a query API has been
> added for it. Test that query.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> tests/i915/i915_query.c | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 5c34ab759..191820532 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> #define DRM_I915_QUERY_HWCONFIG_TABLE 5
> +#define DRM_I915_QUERY_L3_BANK_COUNT 6
> /* Must be kept compact -- no holes and well documented */
>
> /**
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index eef4afb05..17948e0d8 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -849,6 +849,38 @@ static void query_parse_and_validate_hwconfig_table(int i915)
> free(data);
> }
>
> +static int query_engine_l3_bank_count(int fd)
> +{
> + uint32_t *banks;
> + struct drm_i915_query_item size = {
> + .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
> + };
> + struct drm_i915_query_item query = {
> + .query_id = DRM_I915_QUERY_L3_BANK_COUNT,
> + };
I believe you could just one of the local variables, right? I see the
comparison for 'query.length == size.length' but you store the length a
u32 rather than a struct.
Just a suggestion but not a blocker, with that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> + int num_counts, i;
> +
> + i915_query_items(fd, &size, 1);
> + igt_require(size.length > 0);
> +
> + num_counts = size.length / sizeof(*banks);
> + igt_info("size = %d, count = %d => %ld\n", size.length, num_counts, num_counts * sizeof(*banks));
> + igt_assert(size.length == (num_counts * sizeof(*banks)));
> +
> + banks = malloc(size.length);
> + igt_assert(banks);
> + query.data_ptr = to_user_pointer(banks);
> + query.length = size.length;
> +
> + i915_query_items(fd, &query, 1);
> + igt_assert(query.length == size.length);
> + for (i = 0; i < num_counts; i++)
> + igt_info("Bank count #%d: %d\n", i, banks[i]);
> +
> + free(banks);
> + return 0;
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +943,9 @@ igt_main
> igt_subtest("hwconfig_table")
> query_parse_and_validate_hwconfig_table(fd);
>
> + igt_subtest("l3_banks")
> + query_engine_l3_bank_count(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2021-06-14 21:43 ` Matthew Brost
0 siblings, 0 replies; 8+ messages in thread
From: Matthew Brost @ 2021-06-14 21:43 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX, Slawomir Milczarek
On Thu, Jun 10, 2021 at 02:52:46PM -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> All the static platform configuration per SKU is moving to
> this KVL table. User Space components can query and parse
> it to find the proper hw configuration instead of having
> to hardcode it.
>
> Add a query as both an example of how to fetch the table and to
> validate the KLV contents as much as possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> lib/intel_hwconfig_types.h | 102 ++++++++++++++++++++++++++++
> tests/i915/i915_query.c | 128 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 231 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index a1c0030c3..5c34ab759 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2233,6 +2233,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> /* Must be kept compact -- no holes and well documented */
>
> /**
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000..8aa875de9
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This header defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + __INTEL_HWCONFIG_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> +};
> +
> +#define INTEL_HWCONFIG_CACHE_TYPE_L3 BIT(0)
> +#define INTEL_HWCONFIG_CACHE_TYPE_LLC BIT(1)
> +#define INTEL_HWCONFIG_CACHE_TYPE_EDRAM BIT(2)
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 29b938e9c..eef4afb05 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -724,6 +725,130 @@ static void engines(int fd)
> free(engines);
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + uint32_t *data;
> + int i = 0;
> + int len, j, max_words;
> +
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
> + };
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + igt_require(item.length > 0);
> +
> + data = malloc(item.length);
> + igt_assert(data);
> + memset(data, 0, item.length);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_info("Table size = %d bytes\n", item.length);
> + igt_assert(item.length > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = item.length / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == item.length);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
> +
> + len = data[i+1];
Nit: space here?
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s:", data[i], hwconfig_keys[data[i]]);
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info(" %d,", data[j]);
Another nit, would hex be better?
With that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> + igt_info(" %d\n", data[j]);
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -783,6 +908,9 @@ igt_main
> engines(fd);
> }
>
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-06-14 21:50 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-10 21:52 [Intel-gfx] [PATCH i-g-t 0/2] Add tests for new hw info queries John.C.Harrison
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2021-06-14 21:43 ` Matthew Brost
2021-06-10 21:52 ` [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/query: Add test for L3 bank count John.C.Harrison
2021-06-14 19:44 ` Matthew Brost
2021-06-14 19:44 ` [igt-dev] " Matthew Brost
2021-06-10 22:33 ` [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info queries Patchwork
2021-06-11 2:34 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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