* [PATCH v2] riscv: andes_plic: Fix riscv_get_ipi() mask
@ 2021-06-15 5:45 Bin Meng
0 siblings, 0 replies; only message in thread
From: Bin Meng @ 2021-06-15 5:45 UTC (permalink / raw)
To: Rick Chen, Leo Liang, U-Boot Mailing List
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
---
Changes in v2:
- remove RFT tag
- update commit message with "Fixes" tag along with the commit id
arch/riscv/lib/andes_plic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 221a5fe324..5e113ee8c9 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
+ unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
- *pending = !!(*pending & SEND_IPI_TO_HART(hart));
+ *pending = !!(*pending & ipi);
return 0;
}
--
2.25.1
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2021-06-15 5:45 [PATCH v2] riscv: andes_plic: Fix riscv_get_ipi() mask Bin Meng
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