* [PATCH v4 1/5] spi: rockchip_sfc: add support for Rockchip SFC
2021-06-15 19:10 [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Chris Morgan
@ 2021-06-15 19:10 ` Chris Morgan
2021-06-15 19:10 ` [PATCH v4 2/5] rockchip: px30: Add support for using SFC Chris Morgan
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Chris Morgan @ 2021-06-15 19:10 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan
From: Chris Morgan <macromorgan@hotmail.com>
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/rockchip_sfc.c | 513 +++++++++++++++++++++++++++++++++++++
3 files changed, 522 insertions(+)
create mode 100644 drivers/spi/rockchip_sfc.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1494c91763..bef36f2931 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -312,6 +312,14 @@ config RENESAS_RPC_SPI
on Renesas RCar Gen3 SoCs. This uses driver model and requires a
device tree binding to operate.
+config ROCKCHIP_SFC
+ bool "Rockchip SFC Driver"
+ help
+ Enable the Rockchip SFC Driver for SPI NOR flash. This device is
+ a limited purpose SPI controller for driving NOR flash on certain
+ Rockchip SoCs. This uses driver model and requires a device tree
+ binding to operate.
+
config ROCKCHIP_SPI
bool "Rockchip SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cfe4fae1d4..f02e84b5f1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_PL022_SPI) += pl022_spi.o
obj-$(CONFIG_SPI_QUP) += spi-qup.o
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
+obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
new file mode 100644
index 0000000000..2114842b0f
--- /dev/null
+++ b/drivers/spi/rockchip_sfc.c
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip Serial Flash Controller Driver
+ *
+ * Copyright (c) 2017-2021, Rockchip Inc.
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ * Chris Morgan <macromorgan@hotmail.com>
+ * Jon Lin <Jon.lin@rock-chips.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* System control */
+#define SFC_CTRL 0x0
+#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
+#define SFC_CTRL_CMD_BITS_SHIFT 8
+#define SFC_CTRL_ADDR_BITS_SHIFT 10
+#define SFC_CTRL_DATA_BITS_SHIFT 12
+
+/* Interrupt mask */
+#define SFC_IMR 0x4
+#define SFC_IMR_RX_FULL BIT(0)
+#define SFC_IMR_RX_UFLOW BIT(1)
+#define SFC_IMR_TX_OFLOW BIT(2)
+#define SFC_IMR_TX_EMPTY BIT(3)
+#define SFC_IMR_TRAN_FINISH BIT(4)
+#define SFC_IMR_BUS_ERR BIT(5)
+#define SFC_IMR_NSPI_ERR BIT(6)
+#define SFC_IMR_DMA BIT(7)
+
+/* Interrupt clear */
+#define SFC_ICLR 0x8
+#define SFC_ICLR_RX_FULL BIT(0)
+#define SFC_ICLR_RX_UFLOW BIT(1)
+#define SFC_ICLR_TX_OFLOW BIT(2)
+#define SFC_ICLR_TX_EMPTY BIT(3)
+#define SFC_ICLR_TRAN_FINISH BIT(4)
+#define SFC_ICLR_BUS_ERR BIT(5)
+#define SFC_ICLR_NSPI_ERR BIT(6)
+#define SFC_ICLR_DMA BIT(7)
+
+/* FIFO threshold level */
+#define SFC_FTLR 0xc
+#define SFC_FTLR_TX_SHIFT 0
+#define SFC_FTLR_TX_MASK 0x1f
+#define SFC_FTLR_RX_SHIFT 8
+#define SFC_FTLR_RX_MASK 0x1f
+
+/* Reset FSM and FIFO */
+#define SFC_RCVR 0x10
+#define SFC_RCVR_RESET BIT(0)
+
+/* Enhanced mode */
+#define SFC_AX 0x14
+
+/* Address Bit number */
+#define SFC_ABIT 0x18
+
+/* Interrupt status */
+#define SFC_ISR 0x1c
+#define SFC_ISR_RX_FULL_SHIFT BIT(0)
+#define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
+#define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
+#define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
+#define SFC_ISR_TX_FINISH_SHIFT BIT(4)
+#define SFC_ISR_BUS_ERR_SHIFT BIT(5)
+#define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
+#define SFC_ISR_DMA_SHIFT BIT(7)
+
+/* FIFO status */
+#define SFC_FSR 0x20
+#define SFC_FSR_TX_IS_FULL BIT(0)
+#define SFC_FSR_TX_IS_EMPTY BIT(1)
+#define SFC_FSR_RX_IS_EMPTY BIT(2)
+#define SFC_FSR_RX_IS_FULL BIT(3)
+#define SFC_FSR_TXLV_MASK GENMASK(12, 8)
+#define SFC_FSR_TXLV_SHIFT 8
+#define SFC_FSR_RXLV_MASK GENMASK(20, 16)
+#define SFC_FSR_RXLV_SHIFT 16
+
+/* FSM status */
+#define SFC_SR 0x24
+#define SFC_SR_IS_IDLE 0x0
+#define SFC_SR_IS_BUSY 0x1
+
+/* Raw interrupt status */
+#define SFC_RISR 0x28
+#define SFC_RISR_RX_FULL BIT(0)
+#define SFC_RISR_RX_UNDERFLOW BIT(1)
+#define SFC_RISR_TX_OVERFLOW BIT(2)
+#define SFC_RISR_TX_EMPTY BIT(3)
+#define SFC_RISR_TRAN_FINISH BIT(4)
+#define SFC_RISR_BUS_ERR BIT(5)
+#define SFC_RISR_NSPI_ERR BIT(6)
+#define SFC_RISR_DMA BIT(7)
+
+/* Version */
+#define SFC_VER 0x2C
+#define SFC_VER_3 0x3
+#define SFC_VER_4 0x4
+#define SFC_VER_5 0x5
+
+/* Master trigger */
+#define SFC_DMA_TRIGGER 0x80
+
+/* Src or Dst addr for master */
+#define SFC_DMA_ADDR 0x84
+
+/* Length Control Register Extension 32GB */
+#define SFC_LEN_CTRL 0x88
+#define SFC_LEN_CTRL_TRB_SEL 1
+#define SFC_LEN_EXT 0x8C
+
+/* Command */
+#define SFC_CMD 0x100
+#define SFC_CMD_IDX_SHIFT 0
+#define SFC_CMD_DUMMY_SHIFT 8
+#define SFC_CMD_DIR_SHIFT 12
+#define SFC_CMD_DIR_RD 0
+#define SFC_CMD_DIR_WR 1
+#define SFC_CMD_ADDR_SHIFT 14
+#define SFC_CMD_ADDR_0BITS 0
+#define SFC_CMD_ADDR_24BITS 1
+#define SFC_CMD_ADDR_32BITS 2
+#define SFC_CMD_ADDR_XBITS 3
+#define SFC_CMD_TRAN_BYTES_SHIFT 16
+#define SFC_CMD_CS_SHIFT 30
+
+/* Address */
+#define SFC_ADDR 0x104
+
+/* Data */
+#define SFC_DATA 0x108
+
+/* The controller and documentation reports that it supports up to 4 CS
+ * devices (0-3), however I have only been able to test a single CS (CS 0)
+ * due to the configuration of my device.
+ */
+#define SFC_MAX_CHIPSELECT_NUM 4
+
+/* The SFC can transfer max 16KB - 1 at one time
+ * we set it to 15.5KB here for alignment.
+ */
+#define SFC_MAX_IOSIZE_VER3 (512 * 31)
+
+#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFF)
+
+/* DMA is only enabled for large data transmission */
+#define SFC_DMA_TRANS_THRETHOLD (0x40)
+
+/* Maximum clock values from datasheet suggest keeping clock value under
+ * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
+ * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
+ */
+#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
+#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
+#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
+
+struct rockchip_sfc {
+ void __iomem *regbase;
+ struct clk *hclk;
+ struct clk *clk;
+ u32 frequency;
+ u32 max_iosize;
+ u16 sfc_ver;
+};
+
+static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
+{
+ return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
+}
+
+static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
+{
+ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
+ return SFC_MAX_IOSIZE_VER4;
+ else
+ return SFC_MAX_IOSIZE_VER3;
+}
+
+static int rockchip_sfc_init(struct rockchip_sfc *sfc)
+{
+ writel(0, sfc->regbase + SFC_CTRL);
+ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
+ writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
+
+ return 0;
+}
+
+static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+ int ret;
+
+ sfc->regbase = dev_read_addr_ptr(bus);
+
+ ret = clk_get_by_name(bus, "hclk_sfc", sfc->hclk);
+ if (ret < 0) {
+ printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
+ return ret;
+ }
+
+ ret = clk_get_by_name(bus, "clk_sfc", sfc->clk);
+ if (ret < 0) {
+ printf("Could not get sfc clock for %s: %d\n", bus->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_sfc_probe(struct udevice *bus)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+ int ret;
+
+ ret = clk_prepare_enable(sfc->hclk);
+ if (ret) {
+ printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(sfc->clk);
+ if (ret) {
+ printf("Could not get sfc clock for %s: %d\n", bus->name, ret);
+ goto err_clk;
+ }
+
+ ret = clk_set_rate(sfc->clk, SFC_DEFAULT_SPEED_HZ);
+ if (ret) {
+ printf("Could not set sfc clock for %s: %d\n", bus->name, ret);
+ goto err_init;
+ }
+
+ ret = rockchip_sfc_init(sfc);
+ if (ret)
+ goto err_init;
+
+ sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
+ sfc->sfc_ver = rockchip_sfc_get_version(sfc);
+
+ return 0;
+
+err_init:
+ clk_disable_unprepare(sfc->clk);
+err_clk:
+ clk_disable_unprepare(sfc->hclk);
+ return ret;
+}
+
+static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
+{
+ if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
+ /*
+ * SFC not support output DUMMY cycles right after CMD cycles, so
+ * treat it as ADDR cycles.
+ */
+ op->addr.nbytes = op->dummy.nbytes;
+ op->addr.buswidth = op->dummy.buswidth;
+ op->addr.val = 0xFFFFFFFFF;
+
+ op->dummy.nbytes = 0;
+ }
+}
+
+static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
+{
+ u32 fsr = readl_relaxed(sfc->regbase + SFC_FSR);
+ int level;
+
+ if (wr)
+ level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
+ else
+ level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
+
+ return level;
+}
+
+static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
+{
+ unsigned long tbase = get_timer(0);
+ int level;
+
+ while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
+ if (get_timer(tbase) > timeout)
+ return -ETIMEDOUT;
+ udelay(1);
+ }
+
+ return level;
+}
+
+static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
+ struct spi_slave *mem,
+ const struct spi_mem_op *op,
+ u32 len)
+{
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
+ u32 ctrl = 0, cmd = 0;
+
+ /* set CMD */
+ cmd = op->cmd.opcode;
+ ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
+
+ /* set ADDR */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 4) {
+ cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
+ } else if (op->addr.nbytes == 3) {
+ cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
+ } else {
+ cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
+ writel_relaxed(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
+ }
+
+ ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
+ }
+
+ /* set DUMMY */
+ if (op->dummy.nbytes) {
+ if (op->dummy.buswidth == 4)
+ cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
+ else if (op->dummy.buswidth == 2)
+ cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
+ else
+ cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
+ }
+
+ /* set DATA */
+ if (sfc->sfc_ver >= SFC_VER_4) /* Clear it if no data to transfer */
+ writel(len, sfc->regbase + SFC_LEN_EXT);
+ else
+ cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
+ if (len) {
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
+
+ ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
+ }
+ if (!len && op->addr.nbytes)
+ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
+
+ /* set the Controller */
+ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
+ cmd |= plat->cs << SFC_CMD_CS_SHIFT;
+
+ writel(ctrl, sfc->regbase + SFC_CTRL);
+ writel(cmd, sfc->regbase + SFC_CMD);
+ if (op->addr.nbytes)
+ writel(op->addr.val, sfc->regbase + SFC_ADDR);
+
+ return 0;
+}
+
+static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
+{
+ u8 bytes = len & 0x3;
+ u32 dwords;
+ int tx_level;
+ u32 write_words;
+ u32 tmp = 0;
+
+ dwords = len >> 2;
+ while (dwords) {
+ tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ if (tx_level < 0)
+ return tx_level;
+ write_words = min_t(u32, tx_level, dwords);
+ writesl(sfc->regbase + SFC_DATA, buf, write_words);
+ buf += write_words << 2;
+ dwords -= write_words;
+ }
+
+ /* write the rest non word aligned bytes */
+ if (bytes) {
+ tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ if (tx_level < 0)
+ return tx_level;
+ memcpy(&tmp, buf, bytes);
+ writel(tmp, sfc->regbase + SFC_DATA);
+ }
+
+ return len;
+}
+
+static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
+{
+ u8 bytes = len & 0x3;
+ u32 dwords;
+ u8 read_words;
+ int rx_level;
+ int tmp;
+
+ /* word aligned access only */
+ dwords = len >> 2;
+ while (dwords) {
+ rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ if (rx_level < 0)
+ return rx_level;
+ read_words = min_t(u32, rx_level, dwords);
+ readsl(sfc->regbase + SFC_DATA, buf, read_words);
+ buf += read_words << 2;
+ dwords -= read_words;
+ }
+
+ /* read the rest non word aligned bytes */
+ if (bytes) {
+ rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ if (rx_level < 0)
+ return rx_level;
+ tmp = readl_relaxed(sfc->regbase + SFC_DATA);
+ memcpy(buf, &tmp, bytes);
+ }
+
+ return len;
+}
+
+static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
+ const struct spi_mem_op *op, u32 len)
+{
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
+ else
+ return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
+}
+
+static int rockchip_sfc_exec_mem_op(struct spi_slave *mem,
+ const struct spi_mem_op *op)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
+ u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
+ int ret;
+
+ if (unlikely(mem->max_hz != sfc->frequency)) {
+ ret = clk_set_rate(sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
+ (uint)SFC_MAX_SPEED_HZ));
+ if (ret < 0)
+ return ret;
+ sfc->frequency = mem->max_hz;
+ }
+
+ if (unlikely(plat->cs >= SFC_MAX_CHIPSELECT_NUM)) {
+ printf("CS Not Supported for %s: %u\n", mem->dev->parent->name, ret);
+ return -EINVAL;
+ }
+
+ rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
+
+ rockchip_sfc_xfer_setup(sfc, mem, op, len);
+
+ ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
+
+ if (ret != len) {
+ printf("Transfer of data for %s failed: %u\n", mem->dev->parent->name, ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
+
+ op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
+
+ return 0;
+}
+
+static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
+{
+ /* We set up speed later for each transmission.
+ */
+ return 0;
+}
+
+static int rockchip_sfc_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
+ .adjust_op_size = rockchip_sfc_adjust_op_size,
+ .exec_op = rockchip_sfc_exec_mem_op,
+};
+
+static const struct dm_spi_ops rockchip_sfc_ops = {
+ .mem_ops = &rockchip_sfc_mem_ops,
+ .set_speed = rockchip_sfc_set_speed,
+ .set_mode = rockchip_sfc_set_mode,
+};
+
+static const struct udevice_id rockchip_sfc_ids[] = {
+ { .compatible = "rockchip,sfc"},
+ {},
+};
+
+U_BOOT_DRIVER(rockchip_sfc_driver) = {
+ .name = "rockchip_sfc",
+ .id = UCLASS_SPI,
+ .of_match = rockchip_sfc_ids,
+ .ops = &rockchip_sfc_ops,
+ .of_to_plat = rockchip_sfc_ofdata_to_platdata,
+ .plat_auto = sizeof(struct rockchip_sfc),
+ .probe = rockchip_sfc_probe,
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 2/5] rockchip: px30: Add support for using SFC
2021-06-15 19:10 [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Chris Morgan
2021-06-15 19:10 ` [PATCH v4 1/5] spi: " Chris Morgan
@ 2021-06-15 19:10 ` Chris Morgan
2021-06-15 19:10 ` [PATCH v4 3/5] rockchip: px30: add the serial flash controller Chris Morgan
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Chris Morgan @ 2021-06-15 19:10 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan
From: Chris Morgan <macromorgan@hotmail.com>
This patch adds support for setting the correct pin configuration
for the Rockchip Serial Flash Controller found on the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/mach-rockchip/px30/px30.c | 64 ++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index 6fcef63c1b..be70d30cc8 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -51,6 +51,57 @@ struct mm_region *mem_map = px30_mem_map;
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
+/* GRF_GPIO1AL_IOMUX */
+enum {
+ GPIO1A3_SHIFT = 12,
+ GPIO1A3_MASK = 0xf << GPIO1A3_SHIFT,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_FLASH_D3,
+ GPIO1A3_EMMC_D3,
+ GPIO1A3_SFC_SIO3,
+
+ GPIO1A2_SHIFT = 8,
+ GPIO1A2_MASK = 0xf << GPIO1A2_SHIFT,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_FLASH_D2,
+ GPIO1A2_EMMC_D2,
+ GPIO1A2_SFC_SIO2,
+
+ GPIO1A1_SHIFT = 4,
+ GPIO1A1_MASK = 0xf << GPIO1A1_SHIFT,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_FLASH_D1,
+ GPIO1A1_EMMC_D1,
+ GPIO1A1_SFC_SIO1,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 0xf << GPIO1A0_SHIFT,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_FLASH_D0,
+ GPIO1A0_EMMC_D0,
+ GPIO1A0_SFC_SIO0,
+};
+
+/* GRF_GPIO1AH_IOMUX */
+enum {
+ GPIO1A4_SHIFT = 0,
+ GPIO1A4_MASK = 0xf << GPIO1A4_SHIFT,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_FLASH_D4,
+ GPIO1A4_EMMC_D4,
+ GPIO1A4_SFC_CSN0,
+};
+
+/* GRF_GPIO1BL_IOMUX */
+enum {
+ GPIO1B1_SHIFT = 4,
+ GPIO1B1_MASK = 0xf << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_FLASH_RDY,
+ GPIO1B1_EMMC_CLKOUT,
+ GPIO1B1_SFC_CLK,
+};
+
/* GRF_GPIO1BH_IOMUX */
enum {
GPIO1B7_SHIFT = 12,
@@ -193,6 +244,19 @@ int arch_cpu_init(void)
GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
#endif
+#ifdef CONFIG_ROCKCHIP_SFC
+ rk_clrsetreg(&grf->gpio1al_iomux,
+ GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK,
+ GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT |
+ GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT |
+ GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT |
+ GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT);
+ rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK,
+ GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT);
+ rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK,
+ GPIO1B1_SFC_CLK << GPIO1B1_SHIFT);
+#endif
+
#endif
/* Enable PD_VO (default disable at reset) */
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 3/5] rockchip: px30: add the serial flash controller
2021-06-15 19:10 [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Chris Morgan
2021-06-15 19:10 ` [PATCH v4 1/5] spi: " Chris Morgan
2021-06-15 19:10 ` [PATCH v4 2/5] rockchip: px30: Add support for using SFC Chris Morgan
@ 2021-06-15 19:10 ` Chris Morgan
2021-06-15 19:10 ` [PATCH v4 4/5] mtd: spi-nor-ids: Add XTX XT25F128B Chris Morgan
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Chris Morgan @ 2021-06-15 19:10 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan
From: Chris Morgan <macromorgan@hotmail.com>
Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/dts/px30.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index b6c79e7ed3..a85753d9ba 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -960,6 +960,18 @@
status = "disabled";
};
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
gpu: gpu@ff400000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
@@ -1926,6 +1938,32 @@
};
};
+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
lcdc {
lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
rockchip,pins =
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 4/5] mtd: spi-nor-ids: Add XTX XT25F128B
2021-06-15 19:10 [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Chris Morgan
` (2 preceding siblings ...)
2021-06-15 19:10 ` [PATCH v4 3/5] rockchip: px30: add the serial flash controller Chris Morgan
@ 2021-06-15 19:10 ` Chris Morgan
2021-06-15 19:10 ` [PATCH v4 5/5] rockchip: px30: add support for SFC for Odroid Go Advance Chris Morgan
2021-06-18 2:22 ` [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Kever Yang
5 siblings, 0 replies; 8+ messages in thread
From: Chris Morgan @ 2021-06-15 19:10 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan
From: Chris Morgan <macromorgan@hotmail.com>
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
drivers/mtd/spi/Kconfig | 6 ++++++
drivers/mtd/spi/spi-nor-ids.c | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index f8db8e5213..8c797d1e03 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -162,6 +162,12 @@ config SPI_FLASH_XMC
Add support for various XMC (Wuhan Xinxin Semiconductor
Manufacturing Corp.) SPI flash chips (XM25xxx)
+config SPI_FLASH_XTX
+ bool "XTX SPI flash support"
+ help
+ Add support for various XTX (XTX Technology Limited)
+ SPI flash chips (XT25xxx).
+
endif
config SPI_FLASH_USE_4K_SECTORS
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 2b57797954..29c16ff888 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -336,6 +336,10 @@ const struct flash_info spi_nor_ids[] = {
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+#endif
+#ifdef CONFIG_SPI_FLASH_XTX
+ /* XTX Technology (Shenzhen) Limited */
+ { INFO("XT25F128B", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 5/5] rockchip: px30: add support for SFC for Odroid Go Advance
2021-06-15 19:10 [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Chris Morgan
` (3 preceding siblings ...)
2021-06-15 19:10 ` [PATCH v4 4/5] mtd: spi-nor-ids: Add XTX XT25F128B Chris Morgan
@ 2021-06-15 19:10 ` Chris Morgan
2021-06-18 2:22 ` [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Kever Yang
5 siblings, 0 replies; 8+ messages in thread
From: Chris Morgan @ 2021-06-15 19:10 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan
From: Chris Morgan <macromorgan@hotmail.com>
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Additionally, a possible errata was found
while testing the Linux driver, in that setting the tx mode to 2
would cause erases and writes to sometimes fail. Setting the rx mode
to 2 and the tx mode to 1 for this reason, and to match the upcoming
changes to Linux.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 18 ++++++++++++++++++
arch/arm/dts/rk3326-odroid-go2.dts | 16 ++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 00767d2abd..d345f6a168 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -7,6 +7,16 @@
chosen {
u-boot,spl-boot-order = &sdmmc;
};
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdmmc;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ spi0 = &sfc;
+ spi_flash = "/spi@ff3a0000/flash@0";
+ };
};
&cru {
@@ -57,6 +67,14 @@
u-boot,spl-fifo-mode;
};
+&sfc {
+ u-boot,dm-pre-reloc;
+
+ flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&uart1 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 8cd4688c49..4e3dceecbe 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -617,6 +617,22 @@
status = "okay";
};
+&sfc {
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
&tsadc {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC
2021-06-15 19:10 [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Chris Morgan
` (4 preceding siblings ...)
2021-06-15 19:10 ` [PATCH v4 5/5] rockchip: px30: add support for SFC for Odroid Go Advance Chris Morgan
@ 2021-06-18 2:22 ` Kever Yang
2021-06-18 16:30 ` Chris Morgan
5 siblings, 1 reply; 8+ messages in thread
From: Kever Yang @ 2021-06-18 2:22 UTC (permalink / raw)
To: Chris Morgan, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
Hi Chris,
For this patch set, I would like waiting for kernel sfc driver
merge because there may have some update.
Thanks,
- Kever
On 2021/6/16 上午3:10, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Changes from v3:
> - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
> driver to fix potential issue on hardware. Note I never noticed
> this issue while testing, so I cannot test if it fixed any specific
> issue for me.
> - Updated of-compatible string back to "rockchip,sfc" to match what
> is currently proposed for upstream driver. The hardware itself
> has multiple versions but a register is present in the hardware that
> is read by the driver to set version specific functionality.
> - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
> sfc nodes match what is in upstream.
>
> Changes from v2:
> - Resending due to glitch with patch file truncating final two lines
> on patch 1/5 and incorrect patch version number on patch 5/5.
>
> Changes from v1:
> - Reworked code to utilize spi-mem framework, and based it closely
> off of work in progress code for mainline Linux.
> - Removed DMA, as it didn't offer much performance benefit for
> booting (in my test cases), added complexity to the code, and
> interfered with A-TF.
> - Updated the names of the bindings to match the work in progress
> Linux code.
> - Moved alias to u-boot specific device-tree for Odroid Go Advance.
> Alias is updated with the spi0 node pointing to the SFC to
> help the sf command as well as facilitate booting from the SFC.
> - Note 2 below no longer applies, as rebasing this off of upstream
> code should allow the device to work for NAND, and by utilizing
> the spi-mem framework it no longer has to extract the parameters
> from the dm_spi_ops.xfer.
>
> Known Issues Remaining with this Patch Series:
>
> 1) I don't know the best way to upstream the XTX25F128B flash chip.
> This chip should use a continuation code for the manufacturer ID,
> however I cannot seem to find any way to actually read the continuation
> code as one may not be present. There is a risk of this driver, used
> as-is, to collide with another chip which has the same manufacturer ID
> with a different continuation code.
>
> Additionally, it might be worth mentioning but I noticed the Rockchip
> BROM will only boot the TPL/SPL off of the SFC if I write it to address
> 0x10000. This is not documented and different than the address looked
> at for SD card booting (512 * 64 = 0x8000 for SD Card booting). Also,
> like the SD card driver I can confirm that if DMA is enabled at the SPL
> stage A-TF seems to fail silently, then when Linux loads it hangs. FIFO
> mode was removed from the driver to simplify it and for this reason.
>
> Tested: Read (works)
> Write (works)
> Erase (works)
> SPL Read (works if you edit the u-boot,spl-boot-order)
>
> Chris Morgan (5):
> spi: rockchip_sfc: add support for Rockchip SFC
> rockchip: px30: Add support for using SFC
> rockchip: px30: add the serial flash controller
> mtd: spi-nor-ids: Add XTX XT25F128B
> rockchip: px30: add support for SFC for Odroid Go Advance
>
> arch/arm/dts/px30.dtsi | 38 ++
> arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 18 +
> arch/arm/dts/rk3326-odroid-go2.dts | 16 +
> arch/arm/mach-rockchip/px30/px30.c | 64 +++
> drivers/mtd/spi/Kconfig | 6 +
> drivers/mtd/spi/spi-nor-ids.c | 4 +
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/rockchip_sfc.c | 513 +++++++++++++++++++++
> 9 files changed, 668 insertions(+)
> create mode 100644 drivers/spi/rockchip_sfc.c
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC
2021-06-18 2:22 ` [PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC Kever Yang
@ 2021-06-18 16:30 ` Chris Morgan
0 siblings, 0 replies; 8+ messages in thread
From: Chris Morgan @ 2021-06-18 16:30 UTC (permalink / raw)
To: Kever Yang
Cc: Chris Morgan, u-boot, heiko.stuebner, vigneshr, jagan,
philipp.tomsich, sjg
On Fri, Jun 18, 2021 at 10:22:33AM +0800, Kever Yang wrote:
> Hi Chris,
>
> For this patch set, I would like waiting for kernel sfc driver merge
> because there may have some update.
Agreed. I just want to get this out there though in case anyone wants
to test it. I'm okay with "pausing" the review for this one until the
Linux driver is accepted upstream.
On a related note, can you provide some additional docs regarding the
BROM and how it interacts with the SFC? I found out through trial and
error that it reads off of sector 0x10000 (instead of 0x08000 like the
SD Card), and that like the SD card the Arm Trusted Firmware hates DMA
reads in TPL/SPL modes. Is there anything else we should know if we
want to boot an upstream SPL from it (note that I can already do this
with this driver, just wanted to know if there were more "gotchas").
Thank you.
>
>
> Thanks,
>
> - Kever
>
> On 2021/6/16 上午3:10, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > Changes from v3:
> > - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
> > driver to fix potential issue on hardware. Note I never noticed
> > this issue while testing, so I cannot test if it fixed any specific
> > issue for me.
> > - Updated of-compatible string back to "rockchip,sfc" to match what
> > is currently proposed for upstream driver. The hardware itself
> > has multiple versions but a register is present in the hardware that
> > is read by the driver to set version specific functionality.
> > - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
> > sfc nodes match what is in upstream.
> >
> > Changes from v2:
> > - Resending due to glitch with patch file truncating final two lines
> > on patch 1/5 and incorrect patch version number on patch 5/5.
> >
> > Changes from v1:
> > - Reworked code to utilize spi-mem framework, and based it closely
> > off of work in progress code for mainline Linux.
> > - Removed DMA, as it didn't offer much performance benefit for
> > booting (in my test cases), added complexity to the code, and
> > interfered with A-TF.
> > - Updated the names of the bindings to match the work in progress
> > Linux code.
> > - Moved alias to u-boot specific device-tree for Odroid Go Advance.
> > Alias is updated with the spi0 node pointing to the SFC to
> > help the sf command as well as facilitate booting from the SFC.
> > - Note 2 below no longer applies, as rebasing this off of upstream
> > code should allow the device to work for NAND, and by utilizing
> > the spi-mem framework it no longer has to extract the parameters
> > from the dm_spi_ops.xfer.
> >
> > Known Issues Remaining with this Patch Series:
> >
> > 1) I don't know the best way to upstream the XTX25F128B flash chip.
> > This chip should use a continuation code for the manufacturer ID,
> > however I cannot seem to find any way to actually read the continuation
> > code as one may not be present. There is a risk of this driver, used
> > as-is, to collide with another chip which has the same manufacturer ID
> > with a different continuation code.
> >
> > Additionally, it might be worth mentioning but I noticed the Rockchip
> > BROM will only boot the TPL/SPL off of the SFC if I write it to address
> > 0x10000. This is not documented and different than the address looked
> > at for SD card booting (512 * 64 = 0x8000 for SD Card booting). Also,
> > like the SD card driver I can confirm that if DMA is enabled at the SPL
> > stage A-TF seems to fail silently, then when Linux loads it hangs. FIFO
> > mode was removed from the driver to simplify it and for this reason.
> >
> > Tested: Read (works)
> > Write (works)
> > Erase (works)
> > SPL Read (works if you edit the u-boot,spl-boot-order)
> >
> > Chris Morgan (5):
> > spi: rockchip_sfc: add support for Rockchip SFC
> > rockchip: px30: Add support for using SFC
> > rockchip: px30: add the serial flash controller
> > mtd: spi-nor-ids: Add XTX XT25F128B
> > rockchip: px30: add support for SFC for Odroid Go Advance
> >
> > arch/arm/dts/px30.dtsi | 38 ++
> > arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 18 +
> > arch/arm/dts/rk3326-odroid-go2.dts | 16 +
> > arch/arm/mach-rockchip/px30/px30.c | 64 +++
> > drivers/mtd/spi/Kconfig | 6 +
> > drivers/mtd/spi/spi-nor-ids.c | 4 +
> > drivers/spi/Kconfig | 8 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/rockchip_sfc.c | 513 +++++++++++++++++++++
> > 9 files changed, 668 insertions(+)
> > create mode 100644 drivers/spi/rockchip_sfc.c
> >
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread