From: Leo Liang <ycliang@andestech.com>
To: Sean Anderson <seanga2@gmail.com>
Cc: <u-boot@lists.denx.de>
Subject: Re: [PATCH v3 05/11] clk: k210: Re-add support for setting rate
Date: Wed, 16 Jun 2021 09:57:39 +0800 [thread overview]
Message-ID: <20210616015738.GE6791@andestech.com> (raw)
In-Reply-To: <20210611041617.1665833-6-seanga2@gmail.com>
On Fri, Jun 11, 2021 at 12:16:11PM +0800, Sean Anderson wrote:
> This adds support for setting clock rates, which was left out of the
> initial CCF expunging. There are several tricky bits here, mostly related
> to the PLLS:
>
> * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
> will be stopped.
> * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
> stopping the CPU while we configure PLL0's rate, ACLK is reparented
> to IN0 while PLL0 is disabled.
> * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
> so we instead just disallow changing PLL1's rate after relocation (when
> we are using the AISRAM).
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v3:
> - Fix inverted condition for setting defaults
> - Fix val not being set for K210_DIV_POWER
>
> Changes in v2:
> - Only force probe clocks pre-reloc
>
> drivers/clk/kendryte/clk.c | 89 +++++++++++++++++++++++++++++++++++---
> 1 file changed, 84 insertions(+), 5 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2021-06-16 1:58 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 4:16 [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF Sean Anderson
2021-06-11 4:16 ` [PATCH v3 01/11] clk: Allow force setting clock defaults before relocation Sean Anderson
2021-06-11 4:16 ` [PATCH v3 02/11] clk: k210: Rewrite to remove CCF Sean Anderson
2021-06-16 1:54 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 03/11] clk: k210: Move pll into the rest of the driver Sean Anderson
2021-06-16 1:55 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 04/11] clk: k210: Implement soc_clk_dump Sean Anderson
2021-06-16 1:56 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 05/11] clk: k210: Re-add support for setting rate Sean Anderson
2021-06-16 1:57 ` Leo Liang [this message]
2021-06-11 4:16 ` [PATCH v3 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate Sean Anderson
2021-06-16 1:58 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 07/11] clk: k210: Remove bypass driver Sean Anderson
2021-06-16 1:59 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 08/11] clk: k210: Move k210 clock out of its own subdirectory Sean Anderson
2021-06-16 2:01 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 09/11] k210: dts: Set PLL1 to the same rate as PLL0 Sean Anderson
2021-06-16 2:01 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 10/11] k210: Don't imply CCF Sean Anderson
2021-06-16 2:02 ` Leo Liang
2021-06-11 4:16 ` [PATCH v3 11/11] test: Add K210 PLL tests to sandbox defconfigs Sean Anderson
2021-06-11 8:21 ` [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF Lukasz Majewski
2021-06-11 13:57 ` Sean Anderson
2021-06-13 23:08 ` Damien Le Moal
2021-06-11 23:14 ` Sean Anderson
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