* [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
@ 2021-06-16 6:02 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-06-16 6:02 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
The "clock-frequency" property of cpu nodes isn't required. Drop it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b9819570a7d1..ee54878b3f89 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -17,7 +17,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -35,7 +34,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -62,7 +60,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -89,7 +86,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -116,7 +112,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
@ 2021-06-16 6:02 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-06-16 6:02 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
The "clock-frequency" property of cpu nodes isn't required. Drop it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b9819570a7d1..ee54878b3f89 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -17,7 +17,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -35,7 +34,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -62,7 +60,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -89,7 +86,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -116,7 +112,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] riscv: dts: microchip: Fix wrong interrupt numbers of DMA
2021-06-16 6:02 ` Bin Meng
@ 2021-06-16 6:02 ` Bin Meng
-1 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-06-16 6:02 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Per chapter 5.2.2, interrupt sources in the PolarFire MSS doc [1],
the correct interrupt numbers for DMA are <5,6,...,12>.
[1] https://www.microsemi.com/document-portal/doc_download/
1245725-polarfire-soc-fpga-mss-technical-reference-manual
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index ee54878b3f89..a00d9dc560d3 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -182,7 +182,7 @@ dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <5 6 7 8 9 10 11 12>;
#dma-cells = <1>;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] riscv: dts: microchip: Fix wrong interrupt numbers of DMA
@ 2021-06-16 6:02 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-06-16 6:02 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Per chapter 5.2.2, interrupt sources in the PolarFire MSS doc [1],
the correct interrupt numbers for DMA are <5,6,...,12>.
[1] https://www.microsemi.com/document-portal/doc_download/
1245725-polarfire-soc-fpga-mss-technical-reference-manual
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index ee54878b3f89..a00d9dc560d3 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -182,7 +182,7 @@ dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <5 6 7 8 9 10 11 12>;
#dma-cells = <1>;
};
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
2021-06-16 6:02 ` Bin Meng
@ 2021-07-08 13:39 ` Bin Meng
-1 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-07-08 13:39 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
On Wed, Jun 16, 2021 at 2:02 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
> 1 file changed, 5 deletions(-)
>
Ping?
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
@ 2021-07-08 13:39 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-07-08 13:39 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
On Wed, Jun 16, 2021 at 2:02 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
> 1 file changed, 5 deletions(-)
>
Ping?
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
2021-07-08 13:39 ` Bin Meng
@ 2021-07-09 8:42 ` Conor.Dooley
-1 siblings, 0 replies; 12+ messages in thread
From: Conor.Dooley @ 2021-07-09 8:42 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel,
linux-riscv, Daire.McNamara
Cc: bin.meng
On 08/07/2021 14:39, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, Jun 16, 2021 at 2:02 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>> From: Bin Meng <bin.meng@windriver.com>
>>
>> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>>
>> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>> ---
>>
>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
>> 1 file changed, 5 deletions(-)
>>
> Ping?
Daire can you have a look at this and the other hart/clock related change?
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
@ 2021-07-09 8:42 ` Conor.Dooley
0 siblings, 0 replies; 12+ messages in thread
From: Conor.Dooley @ 2021-07-09 8:42 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel,
linux-riscv, Daire.McNamara
Cc: bin.meng
On 08/07/2021 14:39, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, Jun 16, 2021 at 2:02 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>> From: Bin Meng <bin.meng@windriver.com>
>>
>> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>>
>> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>> ---
>>
>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
>> 1 file changed, 5 deletions(-)
>>
> Ping?
Daire can you have a look at this and the other hart/clock related change?
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
2021-06-16 6:02 ` Bin Meng
@ 2021-07-13 15:29 ` Conor.Dooley
-1 siblings, 0 replies; 12+ messages in thread
From: Conor.Dooley @ 2021-07-13 15:29 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel, linux-riscv
Cc: bin.meng
On 16/06/2021 07:02, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index b9819570a7d1..ee54878b3f89 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -17,7 +17,6 @@ cpus {
> #size-cells = <0>;
>
> cpu@0 {
> - clock-frequency = <0>;
> compatible = "sifive,e51", "sifive,rocket0", "riscv";
> device_type = "cpu";
> i-cache-block-size = <64>;
> @@ -35,7 +34,6 @@ cpu0_intc: interrupt-controller {
> };
>
> cpu@1 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -62,7 +60,6 @@ cpu1_intc: interrupt-controller {
> };
>
> cpu@2 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -89,7 +86,6 @@ cpu2_intc: interrupt-controller {
> };
>
> cpu@3 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -116,7 +112,6 @@ cpu3_intc: interrupt-controller {
> };
>
> cpu@4 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> --
> 2.25.1
>
Reviewed-by: conor dooley<conor.dooley@microchip.com>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes
@ 2021-07-13 15:29 ` Conor.Dooley
0 siblings, 0 replies; 12+ messages in thread
From: Conor.Dooley @ 2021-07-13 15:29 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel, linux-riscv
Cc: bin.meng
On 16/06/2021 07:02, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index b9819570a7d1..ee54878b3f89 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -17,7 +17,6 @@ cpus {
> #size-cells = <0>;
>
> cpu@0 {
> - clock-frequency = <0>;
> compatible = "sifive,e51", "sifive,rocket0", "riscv";
> device_type = "cpu";
> i-cache-block-size = <64>;
> @@ -35,7 +34,6 @@ cpu0_intc: interrupt-controller {
> };
>
> cpu@1 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -62,7 +60,6 @@ cpu1_intc: interrupt-controller {
> };
>
> cpu@2 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -89,7 +86,6 @@ cpu2_intc: interrupt-controller {
> };
>
> cpu@3 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -116,7 +112,6 @@ cpu3_intc: interrupt-controller {
> };
>
> cpu@4 {
> - clock-frequency = <0>;
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> --
> 2.25.1
>
Reviewed-by: conor dooley<conor.dooley@microchip.com>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] riscv: dts: microchip: Fix wrong interrupt numbers of DMA
2021-06-16 6:02 ` Bin Meng
@ 2021-07-13 15:29 ` Conor.Dooley
-1 siblings, 0 replies; 12+ messages in thread
From: Conor.Dooley @ 2021-07-13 15:29 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel, linux-riscv
Cc: bin.meng
On 16/06/2021 07:02, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Per chapter 5.2.2, interrupt sources in the PolarFire MSS doc [1],
> the correct interrupt numbers for DMA are <5,6,...,12>.
>
> [1] https://www.microsemi.com/document-portal/doc_download/
> 1245725-polarfire-soc-fpga-mss-technical-reference-manual
>
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index ee54878b3f89..a00d9dc560d3 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -182,7 +182,7 @@ dma@3000000 {
> compatible = "sifive,fu540-c000-pdma";
> reg = <0x0 0x3000000 0x0 0x8000>;
> interrupt-parent = <&plic>;
> - interrupts = <23 24 25 26 27 28 29 30>;
> + interrupts = <5 6 7 8 9 10 11 12>;
> #dma-cells = <1>;
> };
>
> --
> 2.25.1
Reviewed-by: conor dooley<conor.dooley@microchip.com>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] riscv: dts: microchip: Fix wrong interrupt numbers of DMA
@ 2021-07-13 15:29 ` Conor.Dooley
0 siblings, 0 replies; 12+ messages in thread
From: Conor.Dooley @ 2021-07-13 15:29 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel, linux-riscv
Cc: bin.meng
On 16/06/2021 07:02, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Per chapter 5.2.2, interrupt sources in the PolarFire MSS doc [1],
> the correct interrupt numbers for DMA are <5,6,...,12>.
>
> [1] https://www.microsemi.com/document-portal/doc_download/
> 1245725-polarfire-soc-fpga-mss-technical-reference-manual
>
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index ee54878b3f89..a00d9dc560d3 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -182,7 +182,7 @@ dma@3000000 {
> compatible = "sifive,fu540-c000-pdma";
> reg = <0x0 0x3000000 0x0 0x8000>;
> interrupt-parent = <&plic>;
> - interrupts = <23 24 25 26 27 28 29 30>;
> + interrupts = <5 6 7 8 9 10 11 12>;
> #dma-cells = <1>;
> };
>
> --
> 2.25.1
Reviewed-by: conor dooley<conor.dooley@microchip.com>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-07-13 15:29 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-16 6:02 [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes Bin Meng
2021-06-16 6:02 ` Bin Meng
2021-06-16 6:02 ` [PATCH 2/2] riscv: dts: microchip: Fix wrong interrupt numbers of DMA Bin Meng
2021-06-16 6:02 ` Bin Meng
2021-07-13 15:29 ` Conor.Dooley
2021-07-13 15:29 ` Conor.Dooley
2021-07-08 13:39 ` [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes Bin Meng
2021-07-08 13:39 ` Bin Meng
2021-07-09 8:42 ` Conor.Dooley
2021-07-09 8:42 ` Conor.Dooley
2021-07-13 15:29 ` Conor.Dooley
2021-07-13 15:29 ` Conor.Dooley
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.