From: Jonathan Marek <jonathan@marek.ca> To: freedreno@lists.freedesktop.org Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 1/3] dt-bindings: msm: dsi: add missing 7nm bindings Date: Thu, 17 Jun 2021 10:43:33 -0400 [thread overview] Message-ID: <20210617144349.28448-2-jonathan@marek.ca> (raw) In-Reply-To: <20210617144349.28448-1-jonathan@marek.ca> These got lost when going from .txt to .yaml bindings, add them back. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- .../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml new file mode 100644 index 000000000000..c0077ca7e9e7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 7nm PHY + +maintainers: + - Jonathan Marek <jonathan@marek.ca> + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-7nm + - const: qcom,dsi-phy-7nm-8150 + + reg: + items: + - description: dsi phy register set + - description: dsi phy lane register set + - description: dsi pll register set + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + vdds-supply: + description: | + Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150) + +required: + - compatible + - reg + - reg-names + - vdds-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdds-supply = <&vreg_l5a_0p88>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; -- 2.26.1
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Marek <jonathan@marek.ca> To: freedreno@lists.freedesktop.org Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, David Airlie <airlied@linux.ie>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <linux-arm-msm@vger.kernel.org>, open list <linux-kernel@vger.kernel.org>, "open list:DRM DRIVER FOR MSM ADRENO GPU" <dri-devel@lists.freedesktop.org>, Rob Clark <robdclark@gmail.com>, Rob Herring <robh+dt@kernel.org>, Sean Paul <sean@poorly.run> Subject: [PATCH v4 1/3] dt-bindings: msm: dsi: add missing 7nm bindings Date: Thu, 17 Jun 2021 10:43:33 -0400 [thread overview] Message-ID: <20210617144349.28448-2-jonathan@marek.ca> (raw) In-Reply-To: <20210617144349.28448-1-jonathan@marek.ca> These got lost when going from .txt to .yaml bindings, add them back. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- .../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml new file mode 100644 index 000000000000..c0077ca7e9e7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DSI 7nm PHY + +maintainers: + - Jonathan Marek <jonathan@marek.ca> + +allOf: + - $ref: dsi-phy-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,dsi-phy-7nm + - const: qcom,dsi-phy-7nm-8150 + + reg: + items: + - description: dsi phy register set + - description: dsi phy lane register set + - description: dsi pll register set + + reg-names: + items: + - const: dsi_phy + - const: dsi_phy_lane + - const: dsi_pll + + vdds-supply: + description: | + Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150) + +required: + - compatible + - reg + - reg-names + - vdds-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdds-supply = <&vreg_l5a_0p88>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; -- 2.26.1
next prev parent reply other threads:[~2021-06-17 15:09 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-17 14:43 [PATCH v4 0/3] drm/msm/dsi: support CPHY mode for 7nm pll/phy Jonathan Marek 2021-06-17 14:43 ` Jonathan Marek 2021-06-17 14:43 ` Jonathan Marek [this message] 2021-06-17 14:43 ` [PATCH v4 1/3] dt-bindings: msm: dsi: add missing 7nm bindings Jonathan Marek 2021-06-17 16:23 ` Rob Clark 2021-06-17 16:23 ` Rob Clark 2021-06-17 21:26 ` Rob Herring 2021-06-17 21:26 ` Rob Herring 2021-06-18 19:13 ` Rob Herring 2021-06-18 19:13 ` Rob Herring 2021-06-17 14:43 ` [PATCH v4 2/3] dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy Jonathan Marek 2021-06-17 14:43 ` Jonathan Marek 2021-06-24 21:31 ` Rob Herring 2021-06-24 21:31 ` Rob Herring 2021-06-17 14:43 ` [PATCH v4 3/3] drm/msm/dsi: support CPHY mode for 7nm pll/phy Jonathan Marek 2021-06-17 14:43 ` Jonathan Marek
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