* [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
@ 2021-06-18 16:13 Matthew Auld
2021-06-18 16:13 ` [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available Matthew Auld
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Matthew Auld @ 2021-06-18 16:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Clint Taylor <clinton.a.taylor@intel.com>
The PUNIT FW is currently returning 0 for all memory bandwidth
parameters. Read the values directly from MCHBAR offsets 0x5918 and
0x4000(4). This is a temporary WA until the PUNIT FW returns valid
values.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Saarinen <jani.saarinen@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 54 ++++++++++++++++++++++++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bfb398f0432e..f3d8ff4ee0db 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -23,6 +23,53 @@ struct intel_qgv_info {
u8 t_bl;
};
+#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
+#define DG1_QCLK_RATIO_MASK (0xFF << 2)
+#define DG1_QCLK_RATIO_SHIFT 2
+#define DG1_QCLK_REFERENCE (1 << 10)
+
+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4404)
+#define DG1_DRAM_T_RCD_MASK (0x7F << 9)
+#define DG1_DRAM_T_RCD_SHIFT 9
+#define DG1_DRAM_T_RDPRE_MASK (0x3F << 11)
+#define DG1_DRAM_T_RDPRE_SHIFT 11
+#define DG1_DRAM_T_RAS_MASK (0xFF << 1)
+#define DG1_DRAM_T_RAS_SHIFT 1
+#define DG1_DRAM_T_RP_MASK (0x7F << 0)
+#define DG1_DRAM_T_RP_SHIFT 0
+
+static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp,
+ int point)
+{
+ u32 val = 0;
+ u32 dclk_ratio = 0, dclk_reference = 0;
+
+ val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
+ dclk_ratio = (val & DG1_QCLK_RATIO_MASK) >> DG1_QCLK_RATIO_SHIFT;
+ if (val & DG1_QCLK_REFERENCE)
+ dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
+ else
+ dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
+ sp->dclk = dclk_ratio * dclk_reference;
+ if (sp->dclk == 0)
+ return -EINVAL;
+
+ val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
+ sp->t_rp = (val & DG1_DRAM_T_RP_MASK) >> DG1_DRAM_T_RP_SHIFT;
+ sp->t_rdpre = (val & DG1_DRAM_T_RDPRE_MASK) >> DG1_DRAM_T_RDPRE_SHIFT;
+
+ val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
+ sp->t_rcd = (val & DG1_DRAM_T_RCD_MASK) >> DG1_DRAM_T_RCD_SHIFT;
+ sp->t_ras = (val & DG1_DRAM_T_RAS_MASK) >> DG1_DRAM_T_RAS_SHIFT;
+
+ sp->t_rc = sp->t_rp + sp->t_ras;
+ return 0;
+}
+
static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp,
int point)
@@ -100,7 +147,12 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp = &qi->points[i];
ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
- if (ret)
+ if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
+ drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
+ ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
+ if (ret)
+ return ret;
+ } else if (ret)
return ret;
drm_dbg_kms(&dev_priv->drm,
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
@ 2021-06-18 16:13 ` Matthew Auld
2021-06-18 16:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2021-06-18 16:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Clint Taylor <clinton.a.taylor@intel.com>
Use MCHBAR Gear_type information to compute memory bandwidth available
during MCHBAR calculations.
Tested-by: Swati Sharma <swati2.sharma@intel.com>
Cc: Swati Sharma <swati2.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f3d8ff4ee0db..38bf24c437d8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -41,6 +41,9 @@ struct intel_qgv_info {
#define DG1_DRAM_T_RP_MASK (0x7F << 0)
#define DG1_DRAM_T_RP_SHIFT 0
+#define ICL_GEAR_TYPE_MASK (0x01 << 16)
+#define ICL_GEAR_TYPE_SHIFT 16
+
static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp,
int point)
@@ -55,6 +58,11 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
else
dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
sp->dclk = dclk_ratio * dclk_reference;
+
+ val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+ if ((val & ICL_GEAR_TYPE_MASK) >> ICL_GEAR_TYPE_SHIFT)
+ sp->dclk *= 2;
+
if (sp->dclk == 0)
return -EINVAL;
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2021-06-18 16:13 ` [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available Matthew Auld
@ 2021-06-18 16:18 ` Matthew Auld
2021-06-18 19:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2021-06-18 16:18 UTC (permalink / raw)
To: Matthew Auld
Cc: Jani Nikula, Thomas Hellström, Intel Graphics Development
On Fri, 18 Jun 2021 at 17:14, Matthew Auld <matthew.auld@intel.com> wrote:
>
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> The PUNIT FW is currently returning 0 for all memory bandwidth
> parameters. Read the values directly from MCHBAR offsets 0x5918 and
> 0x4000(4). This is a temporary WA until the PUNIT FW returns valid
> values.
Any takers for these two patches? They are confirmed to light up the
display for DG1 and get us an accelerated desktop on drm-tip.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Saarinen <jani.saarinen@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 54 ++++++++++++++++++++++++-
> 1 file changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index bfb398f0432e..f3d8ff4ee0db 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -23,6 +23,53 @@ struct intel_qgv_info {
> u8 t_bl;
> };
>
> +#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
> +#define DG1_QCLK_RATIO_MASK (0xFF << 2)
> +#define DG1_QCLK_RATIO_SHIFT 2
> +#define DG1_QCLK_REFERENCE (1 << 10)
> +
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4404)
> +#define DG1_DRAM_T_RCD_MASK (0x7F << 9)
> +#define DG1_DRAM_T_RCD_SHIFT 9
> +#define DG1_DRAM_T_RDPRE_MASK (0x3F << 11)
> +#define DG1_DRAM_T_RDPRE_SHIFT 11
> +#define DG1_DRAM_T_RAS_MASK (0xFF << 1)
> +#define DG1_DRAM_T_RAS_SHIFT 1
> +#define DG1_DRAM_T_RP_MASK (0x7F << 0)
> +#define DG1_DRAM_T_RP_SHIFT 0
> +
> +static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
> + struct intel_qgv_point *sp,
> + int point)
> +{
> + u32 val = 0;
> + u32 dclk_ratio = 0, dclk_reference = 0;
> +
> + val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
> + dclk_ratio = (val & DG1_QCLK_RATIO_MASK) >> DG1_QCLK_RATIO_SHIFT;
> + if (val & DG1_QCLK_REFERENCE)
> + dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
> + else
> + dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
> + sp->dclk = dclk_ratio * dclk_reference;
> + if (sp->dclk == 0)
> + return -EINVAL;
> +
> + val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> + sp->t_rp = (val & DG1_DRAM_T_RP_MASK) >> DG1_DRAM_T_RP_SHIFT;
> + sp->t_rdpre = (val & DG1_DRAM_T_RDPRE_MASK) >> DG1_DRAM_T_RDPRE_SHIFT;
> +
> + val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
> + sp->t_rcd = (val & DG1_DRAM_T_RCD_MASK) >> DG1_DRAM_T_RCD_SHIFT;
> + sp->t_ras = (val & DG1_DRAM_T_RAS_MASK) >> DG1_DRAM_T_RAS_SHIFT;
> +
> + sp->t_rc = sp->t_rp + sp->t_ras;
> + return 0;
> +}
> +
> static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> struct intel_qgv_point *sp,
> int point)
> @@ -100,7 +147,12 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_point *sp = &qi->points[i];
>
> ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> - if (ret)
> + if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
> + drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
> + ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
> + if (ret)
> + return ret;
> + } else if (ret)
> return ret;
>
> drm_dbg_kms(&dev_priv->drm,
> --
> 2.26.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2021-06-18 16:13 ` [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available Matthew Auld
2021-06-18 16:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
@ 2021-06-18 19:19 ` Patchwork
2021-06-18 22:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-21 5:46 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-18 19:19 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2857 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
URL : https://patchwork.freedesktop.org/series/91685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10243 -> Patchwork_20414
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/index.html
Known issues
------------
Here are the changes found in Patchwork_20414 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2] ([i915#203] / [i915#262])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u: [PASS][3] -> [DMESG-WARN][4] ([i915#262])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0.html
#### Possible fixes ####
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1372]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 37)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10243 -> Patchwork_20414
CI-20190529: 20190529
CI_DRM_10243: 8a81d98f376d18e55a8bb1894f5f7ac71541f9af @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6113: 138a29e30277b1039e9934fca5c782dc1e7a9f99 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20414: aa407a7fcb4f249c0f555be2e8065d75f9e8a45f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aa407a7fcb4f drm/i915/dg1: Double memory bandwidth available
c0e940ae8427 drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/index.html
[-- Attachment #1.2: Type: text/html, Size: 3527 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
` (2 preceding siblings ...)
2021-06-18 19:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
@ 2021-06-18 22:09 ` Patchwork
2021-06-21 5:46 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-18 22:09 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 26421 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
URL : https://patchwork.freedesktop.org/series/91685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10243_full -> Patchwork_20414_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20414_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-snb7/igt@gem_ctx_persistence@idempotent.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][2] -> [FAIL][3] ([i915#2846])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl2/igt@gem_exec_fair@basic-deadline.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][4] ([fdo#109271]) +52 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl7/igt@gem_exec_fair@basic-flow@rcs0.html
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl: NOTRUN -> [FAIL][12] ([i915#3633]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl6/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([i915#1895])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb2/igt@gem_exec_whisper@basic-queues-priority-all.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb8/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#307]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +34 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gen9_exec_parse@bb-large:
- shard-apl: NOTRUN -> [FAIL][18] ([i915#3296])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl8/igt@gen9_exec_parse@bb-large.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271]) +248 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-apl1/igt@i915_suspend@sysfs-reader.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-90:
- shard-iclb: [PASS][22] -> [DMESG-WARN][23] ([i915#3621])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb6/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb1/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +24 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl8/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@vga-hpd:
- shard-skl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +6 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-c-ctm-0-75:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([i915#1982])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl3/igt@kms_color@pipe-c-ctm-0-75.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl5/igt@kms_color@pipe-c-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +17 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][30] ([i915#1319])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl7/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][31] ([i915#2105])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][32] -> [DMESG-WARN][33] ([i915#180]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
- shard-apl: NOTRUN -> [DMESG-WARN][34] ([i915#180])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#2346] / [i915#533])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#79])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2:
- shard-glk: [PASS][39] -> [FAIL][40] ([i915#2122])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-glk2/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-glk6/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2122]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2642])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2672])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271]) +336 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-snb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: NOTRUN -> [FAIL][46] ([i915#1188])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
- shard-kbl: NOTRUN -> [FAIL][49] ([fdo#108145] / [i915#265])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][50] ([fdo#108145] / [i915#265])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][51] ([i915#265])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-skl: NOTRUN -> [FAIL][52] ([i915#265])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#658]) +7 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#658]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109441]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2437])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl3/igt@kms_writeback@writeback-fb-id.html
* igt@perf@non-zero-reason:
- shard-iclb: [PASS][58] -> [FAIL][59] ([i915#3431])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb2/igt@perf@non-zero-reason.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb2/igt@perf@non-zero-reason.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2994]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl6/igt@sysfs_clients@busy.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2994]) +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl2/igt@sysfs_clients@create.html
#### Possible fixes ####
* igt@drm_mm@all@evict:
- shard-skl: [INCOMPLETE][62] -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl8/igt@drm_mm@all@evict.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl8/igt@drm_mm@all@evict.html
* igt@gem_create@create-clear:
- shard-glk: [FAIL][64] ([i915#1888] / [i915#3160]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-glk3/igt@gem_create@create-clear.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-glk9/igt@gem_create@create-clear.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][66] ([i915#180]) -> [PASS][67] +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-skl: [TIMEOUT][68] ([i915#3063]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl7/igt@gem_eio@in-flight-contexts-immediate.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][70] ([i915#2369] / [i915#3063]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-tglb5/igt@gem_eio@unwedge-stress.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-tglb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][72] ([i915#2846]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-glk5/igt@gem_exec_fair@basic-deadline.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [INCOMPLETE][74] ([i915#198] / [i915#2405]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl5/igt@gem_workarounds@suspend-resume-fd.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_color@pipe-c-ctm-0-5:
- shard-skl: [DMESG-WARN][76] ([i915#1982]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl4/igt@kms_color@pipe-c-ctm-0-5.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl8/igt@kms_color@pipe-c-ctm-0-5.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [INCOMPLETE][78] ([i915#198] / [i915#1982]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][80] ([i915#2122]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_plane@plane-position-hole-dpms@pipe-a-planes:
- shard-iclb: [FAIL][82] ([i915#2472]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb8/igt@kms_plane@plane-position-hole-dpms@pipe-a-planes.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb7/igt@kms_plane@plane-position-hole-dpms@pipe-a-planes.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][84] ([fdo#109441]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][86] ([i915#1722]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-skl10/igt@perf@polling-small-buf.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-skl3/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][88] ([i915#2842]) -> [FAIL][89] ([i915#2849])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][90] ([i915#1804] / [i915#2684]) -> [WARN][91] ([i915#2684])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][92] ([i915#2684]) -> [WARN][93] ([i915#1804] / [i915#2684])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][94] ([i915#2920]) -> [SKIP][95] ([i915#658]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl7/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl4/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl3/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-kbl3/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl6/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl3/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl3/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl7/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-kbl3/igt@runner@aborted.html
- shard-iclb: ([FAIL][105], [FAIL][106]) ([i915#3002]) -> ([FAIL][107], [FAIL][108], [FAIL][109]) ([i915#1814] / [i915#3002])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb3/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-iclb2/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb2/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb6/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-iclb1/igt@runner@aborted.html
- shard-apl: ([FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-apl3/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-apl7/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-apl3/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10243/shard-apl8/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl3/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl6/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl1/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl7/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/shard-apl8/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2472]: https://gitlab.freedesktop.org/drm/intel/issues/2472
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3160]: https://gitlab.freedesktop.org/drm/intel/issues/3160
[i915#3296]: https://gitlab.freedesktop.org/drm/intel/issues/3296
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3431]: https://gitlab.freedesktop.org/drm/intel/issues/3431
[i915#3621]: https://gitlab.freedesktop.org/drm/intel/issues/3621
[i915#3633]: https://gitlab.freedesktop.org/drm/intel/issues/3633
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_10243 -> Patchwork_20414
CI-20190529: 20190529
CI_DRM_10243: 8a81d98f376d18e55a8bb1894f5f7ac71541f9af @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6113: 138a29e30277b1039e9934fca5c782dc1e7a9f99 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20414: aa407a7fcb4f249c0f555be2e8065d75f9e8a45f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20414/index.html
[-- Attachment #1.2: Type: text/html, Size: 33313 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
` (3 preceding siblings ...)
2021-06-18 22:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-06-21 5:46 ` Lucas De Marchi
2021-06-21 8:44 ` Matthew Auld
4 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2021-06-21 5:46 UTC (permalink / raw)
To: Matthew Auld; +Cc: Jani Nikula, Intel Graphics
On Fri, Jun 18, 2021 at 9:14 AM Matthew Auld <matthew.auld@intel.com> wrote:
>
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> The PUNIT FW is currently returning 0 for all memory bandwidth
> parameters. Read the values directly from MCHBAR offsets 0x5918 and
> 0x4000(4). This is a temporary WA until the PUNIT FW returns valid
> values.
This is supposed to be fixed for quite some time and this WA shouldn't
be needed. Is this really happening?
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Saarinen <jani.saarinen@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
humn... no s-o-b from you?
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 54 ++++++++++++++++++++++++-
> 1 file changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index bfb398f0432e..f3d8ff4ee0db 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -23,6 +23,53 @@ struct intel_qgv_info {
> u8 t_bl;
> };
>
> +#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
> +#define DG1_QCLK_RATIO_MASK (0xFF << 2)
> +#define DG1_QCLK_RATIO_SHIFT 2
> +#define DG1_QCLK_REFERENCE (1 << 10)
> +
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4404)
> +#define DG1_DRAM_T_RCD_MASK (0x7F << 9)
> +#define DG1_DRAM_T_RCD_SHIFT 9
> +#define DG1_DRAM_T_RDPRE_MASK (0x3F << 11)
> +#define DG1_DRAM_T_RDPRE_SHIFT 11
> +#define DG1_DRAM_T_RAS_MASK (0xFF << 1)
> +#define DG1_DRAM_T_RAS_SHIFT 1
> +#define DG1_DRAM_T_RP_MASK (0x7F << 0)
> +#define DG1_DRAM_T_RP_SHIFT 0
> +
> +static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
> + struct intel_qgv_point *sp,
> + int point)
> +{
> + u32 val = 0;
> + u32 dclk_ratio = 0, dclk_reference = 0;
> +
> + val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
> + dclk_ratio = (val & DG1_QCLK_RATIO_MASK) >> DG1_QCLK_RATIO_SHIFT;
> + if (val & DG1_QCLK_REFERENCE)
> + dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
> + else
> + dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
> + sp->dclk = dclk_ratio * dclk_reference;
> + if (sp->dclk == 0)
> + return -EINVAL;
> +
> + val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> + sp->t_rp = (val & DG1_DRAM_T_RP_MASK) >> DG1_DRAM_T_RP_SHIFT;
> + sp->t_rdpre = (val & DG1_DRAM_T_RDPRE_MASK) >> DG1_DRAM_T_RDPRE_SHIFT;
> +
> + val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
> + sp->t_rcd = (val & DG1_DRAM_T_RCD_MASK) >> DG1_DRAM_T_RCD_SHIFT;
> + sp->t_ras = (val & DG1_DRAM_T_RAS_MASK) >> DG1_DRAM_T_RAS_SHIFT;
> +
> + sp->t_rc = sp->t_rp + sp->t_ras;
> + return 0;
> +}
> +
> static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> struct intel_qgv_point *sp,
> int point)
> @@ -100,7 +147,12 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_point *sp = &qi->points[i];
>
> ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> - if (ret)
> + if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
> + drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
> + ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
> + if (ret)
> + return ret;
> + } else if (ret)
> return ret;
>
> drm_dbg_kms(&dev_priv->drm,
> --
> 2.26.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-06-21 5:46 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
@ 2021-06-21 8:44 ` Matthew Auld
2021-06-21 23:43 ` Lucas De Marchi
0 siblings, 1 reply; 9+ messages in thread
From: Matthew Auld @ 2021-06-21 8:44 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Jani Nikula, Thomas Hellström, Intel Graphics
On 21/06/2021 06:46, Lucas De Marchi wrote:
> On Fri, Jun 18, 2021 at 9:14 AM Matthew Auld <matthew.auld@intel.com> wrote:
>>
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> The PUNIT FW is currently returning 0 for all memory bandwidth
>> parameters. Read the values directly from MCHBAR offsets 0x5918 and
>> 0x4000(4). This is a temporary WA until the PUNIT FW returns valid
>> values.
>
> This is supposed to be fixed for quite some time and this WA shouldn't
> be needed. Is this really happening?
Yes, from the sample of machines I have tried recently they all seem to
need it. Same for Thomas, who also confirmed that these two patches are
needed. In dmesg I get:
[drm:icl_get_bw_info.isra.0 [i915]] Failed to get memory subsystem
information via pcode. IFWI needs update. Trying with MCHBAR
Internal CI looks to be the same from a quick look.
>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Jani Saarinen <jani.saarinen@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> humn... no s-o-b from you?
Will add.
>
> Lucas De Marchi
>
>> ---
>> drivers/gpu/drm/i915/display/intel_bw.c | 54 ++++++++++++++++++++++++-
>> 1 file changed, 53 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index bfb398f0432e..f3d8ff4ee0db 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -23,6 +23,53 @@ struct intel_qgv_info {
>> u8 t_bl;
>> };
>>
>> +#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
>> +#define DG1_QCLK_RATIO_MASK (0xFF << 2)
>> +#define DG1_QCLK_RATIO_SHIFT 2
>> +#define DG1_QCLK_REFERENCE (1 << 10)
>> +
>> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
>> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
>> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
>> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4404)
>> +#define DG1_DRAM_T_RCD_MASK (0x7F << 9)
>> +#define DG1_DRAM_T_RCD_SHIFT 9
>> +#define DG1_DRAM_T_RDPRE_MASK (0x3F << 11)
>> +#define DG1_DRAM_T_RDPRE_SHIFT 11
>> +#define DG1_DRAM_T_RAS_MASK (0xFF << 1)
>> +#define DG1_DRAM_T_RAS_SHIFT 1
>> +#define DG1_DRAM_T_RP_MASK (0x7F << 0)
>> +#define DG1_DRAM_T_RP_SHIFT 0
>> +
>> +static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
>> + struct intel_qgv_point *sp,
>> + int point)
>> +{
>> + u32 val = 0;
>> + u32 dclk_ratio = 0, dclk_reference = 0;
>> +
>> + val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
>> + dclk_ratio = (val & DG1_QCLK_RATIO_MASK) >> DG1_QCLK_RATIO_SHIFT;
>> + if (val & DG1_QCLK_REFERENCE)
>> + dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
>> + else
>> + dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
>> + sp->dclk = dclk_ratio * dclk_reference;
>> + if (sp->dclk == 0)
>> + return -EINVAL;
>> +
>> + val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
>> + sp->t_rp = (val & DG1_DRAM_T_RP_MASK) >> DG1_DRAM_T_RP_SHIFT;
>> + sp->t_rdpre = (val & DG1_DRAM_T_RDPRE_MASK) >> DG1_DRAM_T_RDPRE_SHIFT;
>> +
>> + val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
>> + sp->t_rcd = (val & DG1_DRAM_T_RCD_MASK) >> DG1_DRAM_T_RCD_SHIFT;
>> + sp->t_ras = (val & DG1_DRAM_T_RAS_MASK) >> DG1_DRAM_T_RAS_SHIFT;
>> +
>> + sp->t_rc = sp->t_rp + sp->t_ras;
>> + return 0;
>> +}
>> +
>> static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>> struct intel_qgv_point *sp,
>> int point)
>> @@ -100,7 +147,12 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>> struct intel_qgv_point *sp = &qi->points[i];
>>
>> ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
>> - if (ret)
>> + if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
>> + drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
>> + ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
>> + if (ret)
>> + return ret;
>> + } else if (ret)
>> return ret;
>>
>> drm_dbg_kms(&dev_priv->drm,
>> --
>> 2.26.3
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-06-21 8:44 ` Matthew Auld
@ 2021-06-21 23:43 ` Lucas De Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2021-06-21 23:43 UTC (permalink / raw)
To: Matthew Auld; +Cc: Jani Nikula, Thomas Hellström, Intel Graphics
On Mon, Jun 21, 2021 at 09:44:35AM +0100, Matthew Auld wrote:
>On 21/06/2021 06:46, Lucas De Marchi wrote:
>>On Fri, Jun 18, 2021 at 9:14 AM Matthew Auld <matthew.auld@intel.com> wrote:
>>>
>>>From: Clint Taylor <clinton.a.taylor@intel.com>
>>>
>>>The PUNIT FW is currently returning 0 for all memory bandwidth
>>>parameters. Read the values directly from MCHBAR offsets 0x5918 and
>>>0x4000(4). This is a temporary WA until the PUNIT FW returns valid
>>>values.
>>
>>This is supposed to be fixed for quite some time and this WA shouldn't
>>be needed. Is this really happening?
>
>Yes, from the sample of machines I have tried recently they all seem
>to need it. Same for Thomas, who also confirmed that these two patches
>are needed. In dmesg I get:
>
>[drm:icl_get_bw_info.isra.0 [i915]] Failed to get memory subsystem
>information via pcode. IFWI needs update. Trying with MCHBAR
My point was: is this something reproducible on machines outside Intel?
Machines from CI or internal should follow the recommendation from the
message above: "IFWI needs update".
>Internal CI looks to be the same from a quick look.
:(
>
>>
>>>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>Cc: Matt Roper <matthew.d.roper@intel.com>
>>>Cc: Jani Saarinen <jani.saarinen@intel.com>
>>>Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>
>>humn... no s-o-b from you?
>
>Will add.
>
>>
>>Lucas De Marchi
>>
>>>---
>>> drivers/gpu/drm/i915/display/intel_bw.c | 54 ++++++++++++++++++++++++-
>>> 1 file changed, 53 insertions(+), 1 deletion(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>>>index bfb398f0432e..f3d8ff4ee0db 100644
>>>--- a/drivers/gpu/drm/i915/display/intel_bw.c
>>>+++ b/drivers/gpu/drm/i915/display/intel_bw.c
>>>@@ -23,6 +23,53 @@ struct intel_qgv_info {
>>> u8 t_bl;
>>> };
>>>
>>>+#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
>>>+#define DG1_QCLK_RATIO_MASK (0xFF << 2)
>>>+#define DG1_QCLK_RATIO_SHIFT 2
>>>+#define DG1_QCLK_REFERENCE (1 << 10)
>>>+
>>>+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
>>>+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
>>>+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
>>>+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4404)
>>>+#define DG1_DRAM_T_RCD_MASK (0x7F << 9)
>>>+#define DG1_DRAM_T_RCD_SHIFT 9
>>>+#define DG1_DRAM_T_RDPRE_MASK (0x3F << 11)
>>>+#define DG1_DRAM_T_RDPRE_SHIFT 11
>>>+#define DG1_DRAM_T_RAS_MASK (0xFF << 1)
>>>+#define DG1_DRAM_T_RAS_SHIFT 1
>>>+#define DG1_DRAM_T_RP_MASK (0x7F << 0)
>>>+#define DG1_DRAM_T_RP_SHIFT 0
>>>+
>>>+static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
>>>+ struct intel_qgv_point *sp,
>>>+ int point)
>>>+{
>>>+ u32 val = 0;
>>>+ u32 dclk_ratio = 0, dclk_reference = 0;
>>>+
>>>+ val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
>>>+ dclk_ratio = (val & DG1_QCLK_RATIO_MASK) >> DG1_QCLK_RATIO_SHIFT;
>>>+ if (val & DG1_QCLK_REFERENCE)
>>>+ dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
>>>+ else
>>>+ dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
>>>+ sp->dclk = dclk_ratio * dclk_reference;
>>>+ if (sp->dclk == 0)
>>>+ return -EINVAL;
>>>+
>>>+ val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
>>>+ sp->t_rp = (val & DG1_DRAM_T_RP_MASK) >> DG1_DRAM_T_RP_SHIFT;
>>>+ sp->t_rdpre = (val & DG1_DRAM_T_RDPRE_MASK) >> DG1_DRAM_T_RDPRE_SHIFT;
>>>+
>>>+ val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
>>>+ sp->t_rcd = (val & DG1_DRAM_T_RCD_MASK) >> DG1_DRAM_T_RCD_SHIFT;
>>>+ sp->t_ras = (val & DG1_DRAM_T_RAS_MASK) >> DG1_DRAM_T_RAS_SHIFT;
>>>+
>>>+ sp->t_rc = sp->t_rp + sp->t_ras;
>>>+ return 0;
>>>+}
>>>+
>>> static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>>> struct intel_qgv_point *sp,
>>> int point)
>>>@@ -100,7 +147,12 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>>> struct intel_qgv_point *sp = &qi->points[i];
>>>
>>> ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
>>>- if (ret)
>>>+ if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
>>>+ drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
>>>+ ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
>>>+ if (ret)
>>>+ return ret;
>>>+ } else if (ret)
>>> return ret;
IMO this looks a little bit nicer to read:
ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
}
if (ret)
return ret;
Lucas De Marchi
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
@ 2021-06-24 8:31 Matthew Auld
0 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2021-06-24 8:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
From: Clint Taylor <clinton.a.taylor@intel.com>
The PUNIT FW is currently returning 0 for all memory bandwidth
parameters. Read the values directly from MCHBAR offsets 0x5918 and
0x4000(4). This is a temporary WA until the PUNIT FW returns valid
values.
v2(Lucas): tidy up checking for ret slightly
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Saarinen <jani.saarinen@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bfb398f0432e..62a70f364f2b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -23,6 +23,53 @@ struct intel_qgv_info {
u8 t_bl;
};
+#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
+#define DG1_QCLK_RATIO_MASK (0xFF << 2)
+#define DG1_QCLK_RATIO_SHIFT 2
+#define DG1_QCLK_REFERENCE (1 << 10)
+
+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4404)
+#define DG1_DRAM_T_RCD_MASK (0x7F << 9)
+#define DG1_DRAM_T_RCD_SHIFT 9
+#define DG1_DRAM_T_RDPRE_MASK (0x3F << 11)
+#define DG1_DRAM_T_RDPRE_SHIFT 11
+#define DG1_DRAM_T_RAS_MASK (0xFF << 1)
+#define DG1_DRAM_T_RAS_SHIFT 1
+#define DG1_DRAM_T_RP_MASK (0x7F << 0)
+#define DG1_DRAM_T_RP_SHIFT 0
+
+static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp,
+ int point)
+{
+ u32 val = 0;
+ u32 dclk_ratio = 0, dclk_reference = 0;
+
+ val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
+ dclk_ratio = (val & DG1_QCLK_RATIO_MASK) >> DG1_QCLK_RATIO_SHIFT;
+ if (val & DG1_QCLK_REFERENCE)
+ dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
+ else
+ dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
+ sp->dclk = dclk_ratio * dclk_reference;
+ if (sp->dclk == 0)
+ return -EINVAL;
+
+ val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
+ sp->t_rp = (val & DG1_DRAM_T_RP_MASK) >> DG1_DRAM_T_RP_SHIFT;
+ sp->t_rdpre = (val & DG1_DRAM_T_RDPRE_MASK) >> DG1_DRAM_T_RDPRE_SHIFT;
+
+ val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
+ sp->t_rcd = (val & DG1_DRAM_T_RCD_MASK) >> DG1_DRAM_T_RCD_SHIFT;
+ sp->t_ras = (val & DG1_DRAM_T_RAS_MASK) >> DG1_DRAM_T_RAS_SHIFT;
+
+ sp->t_rc = sp->t_rp + sp->t_ras;
+ return 0;
+}
+
static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp,
int point)
@@ -100,6 +147,11 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp = &qi->points[i];
ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
+ if (IS_DG1(dev_priv) && (ret || sp->dclk == 0)) {
+ drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information via pcode. IFWI needs update. Trying with MCHBAR\n");
+ ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
+ }
+
if (ret)
return ret;
--
2.26.3
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^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-06-24 8:31 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2021-06-18 16:13 ` [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available Matthew Auld
2021-06-18 16:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2021-06-18 19:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2021-06-18 22:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-21 5:46 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
2021-06-21 8:44 ` Matthew Auld
2021-06-21 23:43 ` Lucas De Marchi
2021-06-24 8:31 Matthew Auld
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