* [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes
@ 2021-06-25 23:55 José Roberto de Souza
2021-06-25 23:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer José Roberto de Souza
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: José Roberto de Souza @ 2021-06-25 23:55 UTC (permalink / raw)
To: intel-gfx
Implements changes around PSR for alderlake-P:
- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
removed setting SU_REGION_START/END_ADDR will do this job
- SU_REGION_START/END_ADDR have now line granularity but will need to
be aligned with DSC when the PSRS + DSC support lands
BSpec: 50422
BSpec: 50424
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++------
2 files changed, 48 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9643624fe160d..46bb19c4b63a4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 val;
+ u32 val = EDP_PSR2_ENABLE;
+
+ val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
- val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
+ if (!IS_ALDERLAKE_P(dev_priv))
+ val |= EDP_SU_TRACK_ENABLE;
- val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
val |= EDP_Y_COORDINATE_ENABLE;
@@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
static bool psr2_granularity_check(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
u16 y_granularity = 0;
@@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
return intel_dp->psr.su_y_granularity == 4;
/*
- * For SW tracking we can adjust the y to match sink requirement if
- * multiple of 4
+ * adl_p has 1 line granularity for other platforms with SW tracking we
+ * can adjust the y coordinate to match sink requirement if multiple of
+ * 4
*/
- if (intel_dp->psr.su_y_granularity <= 2)
+ if (IS_ALDERLAKE_P(dev_priv))
+ y_granularity = intel_dp->psr.su_y_granularity;
+ else if (intel_dp->psr.su_y_granularity <= 2)
y_granularity = 4;
else if ((intel_dp->psr.su_y_granularity % 4) == 0)
y_granularity = intel_dp->psr.su_y_granularity;
@@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
struct drm_rect *clip, bool full_update)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 val = PSR2_MAN_TRK_CTL_ENABLE;
if (full_update) {
- val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ if (IS_ALDERLAKE_P(dev_priv))
+ val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ else
+ val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+
goto exit;
}
if (clip->y1 == -1)
goto exit;
- drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+ } else {
+ drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
- val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
- val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
- val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+ }
exit:
crtc_state->psr2_man_track_ctl = val;
}
@@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
struct drm_rect *pipe_clip)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const u16 y_alignment = crtc_state->su_y_granularity;
pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
if (pipe_clip->y2 % y_alignment)
pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
+
+ if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
+ drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
}
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65c155b141899..2d38bd09391eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4586,7 +4586,7 @@ enum {
#define _PSR2_CTL_EDP 0x6f900
#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
#define EDP_PSR2_ENABLE (1 << 31)
-#define EDP_SU_TRACK_ENABLE (1 << 30)
+#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
@@ -4655,17 +4655,23 @@ enum {
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
#define PSR2_SU_STATUS_FRAMES 8
-#define _PSR2_MAN_TRK_CTL_A 0x60910
-#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
-#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
-#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
+#define _PSR2_MAN_TRK_CTL_A 0x60910
+#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
+#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
+#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
-#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
-#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
-#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
+#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
+#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
/* Icelake DSC Rate Control Range Parameter Registers */
#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
--
2.32.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
@ 2021-06-25 23:56 ` José Roberto de Souza
2021-07-20 19:51 ` Lucas De Marchi
2021-06-26 0:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes Patchwork
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: José Roberto de Souza @ 2021-06-25 23:56 UTC (permalink / raw)
To: intel-gfx
This is now a requirement for all display 12 and newer, not only for
tigerlake.
BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7dc72e4a4656b..270b1f26566df 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -911,11 +911,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
}
/*
- * Tigerlake is not supporting FBC with PSR2.
+ * Display 12+ is not supporting FBC with PSR2.
* Recommendation is to keep this combination disabled
* Bspec: 50422 HSD: 14010260002
*/
- if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
+ if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
fbc->no_fbc_reason = "not supported with PSR2";
return false;
}
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
2021-06-25 23:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer José Roberto de Souza
@ 2021-06-26 0:08 ` Patchwork
2021-06-26 0:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-26 0:08 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
URL : https://patchwork.freedesktop.org/series/91931/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
40703d3f9d23 drm/i915/display/adl_p: Implement PSR changes
-:149: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/i915_reg.h:4660:
+#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
-:152: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#152: FILE: drivers/gpu/drm/i915/i915_reg.h:4663:
+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-:162: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#162: FILE: drivers/gpu/drm/i915/i915_reg.h:4670:
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-:164: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#164: FILE: drivers/gpu/drm/i915/i915_reg.h:4672:
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
total: 0 errors, 4 warnings, 0 checks, 131 lines checked
399cecf3f729 drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
2021-06-25 23:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer José Roberto de Souza
2021-06-26 0:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes Patchwork
@ 2021-06-26 0:10 ` Patchwork
2021-06-26 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-26 0:10 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
URL : https://patchwork.freedesktop.org/series/91931/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
` (2 preceding siblings ...)
2021-06-26 0:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-06-26 0:39 ` Patchwork
2021-06-26 1:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-20 19:48 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-26 0:39 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2307 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
URL : https://patchwork.freedesktop.org/series/91931/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10282 -> Patchwork_20472
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/index.html
Known issues
------------
Here are the changes found in Patchwork_20472 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +16 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_mocs:
- {fi-tgl-1115g4}: [DMESG-WARN][2] ([i915#2867]) -> [PASS][3] +14 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/fi-tgl-1115g4/igt@i915_selftest@live@gt_mocs.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/fi-tgl-1115g4/igt@i915_selftest@live@gt_mocs.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
Participating hosts (43 -> 39)
------------------------------
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10282 -> Patchwork_20472
CI-20190529: 20190529
CI_DRM_10282: 67f5a18128770817e4218a9e496d2bf5047c51e8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6119: a306810ebbc8984bde38a57ef0c33eea394f4e18 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20472: 399cecf3f729c6dd519d878af2bc0dc40cab3bec @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
399cecf3f729 drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer
40703d3f9d23 drm/i915/display/adl_p: Implement PSR changes
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/index.html
[-- Attachment #1.2: Type: text/html, Size: 2939 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
` (3 preceding siblings ...)
2021-06-26 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-06-26 1:49 ` Patchwork
2021-07-20 19:48 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-26 1:49 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30295 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes
URL : https://patchwork.freedesktop.org/series/91931/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10282_full -> Patchwork_20472_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_20472_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20472_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20472_full:
### IGT changes ###
#### Warnings ####
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][1] ([i915#658]) -> [SKIP][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
Known issues
------------
Here are the changes found in Patchwork_20472_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#3002])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl7/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-kbl: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@gem_exec_fair@basic-flow@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-glk1/igt@gem_exec_fair@basic-none-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271]) +21 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl3/igt@gem_exec_params@no-vebox.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#307])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +81 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][19] ([i915#3002]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@gem_userptr_blits@input-checking.html
- shard-snb: NOTRUN -> [DMESG-WARN][20] ([i915#3002])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-snb2/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1436] / [i915#716])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl1/igt@gen9_exec_parse@allowed-all.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl4/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1937])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][24] -> [FAIL][25] ([i915#2521])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl3/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +12 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-snb2/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-iclb: NOTRUN -> [SKIP][28] ([fdo#109284] / [fdo#111827])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color@pipe-c-ctm-0-75:
- shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl6/igt@kms_color@pipe-c-ctm-0-75.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl9/igt@kms_color@pipe-c-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +20 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl2/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-glk: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk8/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl2/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][34] ([i915#1319]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][35] ([i915#2105])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@kms_content_protection@uevent.html
- shard-apl: NOTRUN -> [FAIL][36] ([i915#2105])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl8/igt@kms_content_protection@uevent.html
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109300] / [fdo#111066])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-rapid-movement:
- shard-glk: NOTRUN -> [SKIP][38] ([fdo#109271]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk8/igt@kms_cursor_crc@pipe-d-cursor-256x85-rapid-movement.html
* igt@kms_cursor_legacy@pipe-d-single-move:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_cursor_legacy@pipe-d-single-move.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109274])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2122])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl1/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2672])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109280]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][45] -> [DMESG-WARN][46] ([i915#180]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
- shard-skl: [PASS][47] -> [FAIL][48] ([i915#1188])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl8/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: NOTRUN -> [DMESG-WARN][51] ([i915#180]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][54] ([i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109441])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_psr@psr2_dpms.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#109441])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][62] ([i915#31])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-snb6/igt@kms_setmode@basic.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-skl: NOTRUN -> [WARN][63] ([i915#2100])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl3/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: [PASS][64] -> [INCOMPLETE][65] ([i915#155])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][66] -> [DMESG-WARN][67] ([i915#180] / [i915#295])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-query-forked-hang:
- shard-snb: NOTRUN -> [SKIP][68] ([fdo#109271]) +208 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-snb6/igt@kms_vblank@pipe-d-query-forked-hang.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271]) +239 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2437])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-c-source-rg:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#2530])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@nouveau_crc@pipe-c-source-rg.html
* igt@prime_nv_api@i915_nv_double_export:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109291])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@prime_nv_api@i915_nv_double_export.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][73] ([i915#3002])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-snb2/igt@runner@aborted.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2994]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl1/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-10:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2994])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][76] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb7/igt@gem_eio@unwedge-stress.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][78] ([i915#2846]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][80] ([i915#2842]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][82] ([i915#2842]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][84] ([i915#2842]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_gttfill@basic:
- shard-iclb: [INCOMPLETE][86] ([i915#2405]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb4/igt@gem_exec_gttfill@basic.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@gem_exec_gttfill@basic.html
* igt@gem_mmap_gtt@big-copy-xy:
- shard-glk: [FAIL][88] ([i915#307]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-glk3/igt@gem_mmap_gtt@big-copy-xy.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk5/igt@gem_mmap_gtt@big-copy-xy.html
* igt@gem_spin_batch@spin-each:
- shard-apl: [FAIL][90] ([i915#2898]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl3/igt@gem_spin_batch@spin-each.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl1/igt@gem_spin_batch@spin-each.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][92] ([i915#1436] / [i915#716]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-glk1/igt@gen9_exec_parse@allowed-all.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-glk8/igt@gen9_exec_parse@allowed-all.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [DMESG-WARN][94] ([i915#1982]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl7/igt@kms_color@pipe-a-ctm-0-5.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl7/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +7 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [DMESG-WARN][98] ([i915#180]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl1/igt@kms_flip@flip-vs-suspend@b-dp1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl8/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][100] ([fdo#108145] / [i915#265]) -> [PASS][101] +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][102] ([fdo#109441]) -> [PASS][103] +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][104] ([i915#1804] / [i915#2684]) -> [WARN][105] ([i915#2684])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][106] ([fdo#109349]) -> [DMESG-WARN][107] ([i915#1226])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-iclb: [SKIP][108] -> [SKIP][109] ([i915#658])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#3363])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl6/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl4/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl6/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl4/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-kbl1/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl4/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl4/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][129], [FAIL][130], [FAIL][131]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3363]) -> ([FAIL][132], [FAIL][133], [FAIL][134]) ([i915#1814] / [i915#3002] / [i915#3363])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl8/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl1/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-apl2/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl3/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl2/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-apl1/igt@runner@aborted.html
- shard-skl: ([FAIL][135], [FAIL][136]) ([i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1436] / [i915#1814] / [i915#3002] / [i915#3363])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10282/shard-skl10/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl4/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl5/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/shard-skl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2100]: https://gitlab.freedesktop.org/drm/intel/issues/2100
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/is
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20472/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
` (4 preceding siblings ...)
2021-06-26 1:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-07-20 19:48 ` Lucas De Marchi
2021-07-20 23:08 ` Souza, Jose
5 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2021-07-20 19:48 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Jun 25, 2021 at 04:55:59PM -0700, Jose Souza wrote:
>Implements changes around PSR for alderlake-P:
>
>- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
>- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> removed setting SU_REGION_START/END_ADDR will do this job
>- SU_REGION_START/END_ADDR have now line granularity but will need to
> be aligned with DSC when the PSRS + DSC support lands
>
>BSpec: 50422
>BSpec: 50424
>Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
> drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++------
> 2 files changed, 48 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index 9643624fe160d..46bb19c4b63a4 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> static void hsw_activate_psr2(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>- u32 val;
>+ u32 val = EDP_PSR2_ENABLE;
>+
>+ val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
>
>- val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
>+ if (!IS_ALDERLAKE_P(dev_priv))
>+ val |= EDP_SU_TRACK_ENABLE;
>
>- val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> val |= EDP_Y_COORDINATE_ENABLE;
>
>@@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> static bool psr2_granularity_check(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state)
> {
>+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> u16 y_granularity = 0;
>@@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
> return intel_dp->psr.su_y_granularity == 4;
>
> /*
>- * For SW tracking we can adjust the y to match sink requirement if
>- * multiple of 4
>+ * adl_p has 1 line granularity for other platforms with SW tracking we
missing a .? adl_p has 1 line granularity. For other platforms ...
>+ * can adjust the y coordinate to match sink requirement if multiple of
>+ * 4
> */
>- if (intel_dp->psr.su_y_granularity <= 2)
>+ if (IS_ALDERLAKE_P(dev_priv))
>+ y_granularity = intel_dp->psr.su_y_granularity;
>+ else if (intel_dp->psr.su_y_granularity <= 2)
this was already here, but not covered in the comment above. What is
this doing?
changes match spec.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
> y_granularity = 4;
> else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> y_granularity = intel_dp->psr.su_y_granularity;
>@@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
> static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> struct drm_rect *clip, bool full_update)
> {
>+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 val = PSR2_MAN_TRK_CTL_ENABLE;
>
> if (full_update) {
>- val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>+ if (IS_ALDERLAKE_P(dev_priv))
>+ val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>+ else
>+ val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
>+
> goto exit;
> }
>
> if (clip->y1 == -1)
> goto exit;
>
>- drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
>+ if (IS_ALDERLAKE_P(dev_priv)) {
>+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
>+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
>+ } else {
>+ drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
>
>- val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
>- val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
>- val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
>+ val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
>+ val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
>+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
>+ }
> exit:
> crtc_state->psr2_man_track_ctl = val;
> }
>@@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
> static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
> struct drm_rect *pipe_clip)
> {
>+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> const u16 y_alignment = crtc_state->su_y_granularity;
>
> pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> if (pipe_clip->y2 % y_alignment)
> pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
>+
>+ if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
>+ drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
> }
>
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 65c155b141899..2d38bd09391eb 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4586,7 +4586,7 @@ enum {
> #define _PSR2_CTL_EDP 0x6f900
> #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
> #define EDP_PSR2_ENABLE (1 << 31)
>-#define EDP_SU_TRACK_ENABLE (1 << 30)
>+#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
> #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
>@@ -4655,17 +4655,23 @@ enum {
> #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
> #define PSR2_SU_STATUS_FRAMES 8
>
>-#define _PSR2_MAN_TRK_CTL_A 0x60910
>-#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
>-#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
>-#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
>-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
>-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>+#define _PSR2_MAN_TRK_CTL_A 0x60910
>+#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
>+#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
>+#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
>+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
>+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
> #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
>-#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
>-#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
>-#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
>+#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
>+#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
>+#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
>+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
>+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
>+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
>+#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
>+#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
>
> /* Icelake DSC Rate Control Range Parameter Registers */
> #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>--
>2.32.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer
2021-06-25 23:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer José Roberto de Souza
@ 2021-07-20 19:51 ` Lucas De Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2021-07-20 19:51 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Jun 25, 2021 at 04:56:00PM -0700, Jose Souza wrote:
>This is now a requirement for all display 12 and newer, not only for
>tigerlake.
>
>BSpec: 50422
>Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>index 7dc72e4a4656b..270b1f26566df 100644
>--- a/drivers/gpu/drm/i915/display/intel_fbc.c
>+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>@@ -911,11 +911,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> }
>
> /*
>- * Tigerlake is not supporting FBC with PSR2.
>+ * Display 12+ is not supporting FBC with PSR2.
> * Recommendation is to keep this combination disabled
> * Bspec: 50422 HSD: 14010260002
> */
>- if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
>+ if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
> fbc->no_fbc_reason = "not supported with PSR2";
> return false;
> }
>--
>2.32.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes
2021-07-20 19:48 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
@ 2021-07-20 23:08 ` Souza, Jose
0 siblings, 0 replies; 9+ messages in thread
From: Souza, Jose @ 2021-07-20 23:08 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-gfx
On Tue, 2021-07-20 at 12:48 -0700, Lucas De Marchi wrote:
> On Fri, Jun 25, 2021 at 04:55:59PM -0700, Jose Souza wrote:
> > Implements changes around PSR for alderlake-P:
> >
> > - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> > - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> > removed setting SU_REGION_START/END_ADDR will do this job
> > - SU_REGION_START/END_ADDR have now line granularity but will need to
> > be aligned with DSC when the PSRS + DSC support lands
> >
> > BSpec: 50422
> > BSpec: 50424
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 43 ++++++++++++++++++------
> > drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++------
> > 2 files changed, 48 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 9643624fe160d..46bb19c4b63a4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -534,11 +534,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> > static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - u32 val;
> > + u32 val = EDP_PSR2_ENABLE;
> > +
> > + val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> >
> > - val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
> > + if (!IS_ALDERLAKE_P(dev_priv))
> > + val |= EDP_SU_TRACK_ENABLE;
> >
> > - val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> > if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
> > val |= EDP_Y_COORDINATE_ENABLE;
> >
> > @@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > static bool psr2_granularity_check(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > u16 y_granularity = 0;
> > @@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
> > return intel_dp->psr.su_y_granularity == 4;
> >
> > /*
> > - * For SW tracking we can adjust the y to match sink requirement if
> > - * multiple of 4
> > + * adl_p has 1 line granularity for other platforms with SW tracking we
>
> missing a .? adl_p has 1 line granularity. For other platforms ...
Thanks, will update the comment while applying.
>
> > + * can adjust the y coordinate to match sink requirement if multiple of
> > + * 4
> > */
> > - if (intel_dp->psr.su_y_granularity <= 2)
> > + if (IS_ALDERLAKE_P(dev_priv))
> > + y_granularity = intel_dp->psr.su_y_granularity;
> > + else if (intel_dp->psr.su_y_granularity <= 2)
>
> this was already here, but not covered in the comment above. What is
> this doing?
It kinda of was, "adjust the y coordinate to match sink requirement if multiple of 4".
Platforms older than Alderlake-P only support 4 lines of granularity, if panel requires 1 or 2 lines we can support that as 4 is also a multiple of 1
and 2.
>
>
> changes match spec.
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Thanks
>
> thanks
> Lucas De Marchi
>
> > y_granularity = 4;
> > else if ((intel_dp->psr.su_y_granularity % 4) == 0)
> > y_granularity = intel_dp->psr.su_y_granularity;
> > @@ -1525,21 +1531,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
> > static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> > struct drm_rect *clip, bool full_update)
> > {
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> >
> > if (full_update) {
> > - val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > + if (IS_ALDERLAKE_P(dev_priv))
> > + val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > + else
> > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > +
> > goto exit;
> > }
> >
> > if (clip->y1 == -1)
> > goto exit;
> >
> > - drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> > + if (IS_ALDERLAKE_P(dev_priv)) {
> > + val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> > + val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
> > + } else {
> > + drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
> >
> > - val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > - val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > - val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> > + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> > + }
> > exit:
> > crtc_state->psr2_man_track_ctl = val;
> > }
> > @@ -1563,11 +1580,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
> > static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
> > struct drm_rect *pipe_clip)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > const u16 y_alignment = crtc_state->su_y_granularity;
> >
> > pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> > if (pipe_clip->y2 % y_alignment)
> > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> > +
> > + if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
> > + drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
> > }
> >
> > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 65c155b141899..2d38bd09391eb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4586,7 +4586,7 @@ enum {
> > #define _PSR2_CTL_EDP 0x6f900
> > #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
> > #define EDP_PSR2_ENABLE (1 << 31)
> > -#define EDP_SU_TRACK_ENABLE (1 << 30)
> > +#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
> > #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
> > #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
> > #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
> > @@ -4655,17 +4655,23 @@ enum {
> > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
> > #define PSR2_SU_STATUS_FRAMES 8
> >
> > -#define _PSR2_MAN_TRK_CTL_A 0x60910
> > -#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
> > -#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > -#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
> > -#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
> > -#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > +#define _PSR2_MAN_TRK_CTL_A 0x60910
> > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
> > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
> > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
> > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
> > #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > -#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
> > -#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> > -#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
> > +#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
> > +#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> > +#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
> > +#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
> > +#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > +#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
> > +#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > +#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
> > +#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
> >
> > /* Icelake DSC Rate Control Range Parameter Registers */
> > #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
> > --
> > 2.32.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-07-20 23:08 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-25 23:55 [Intel-gfx] [PATCH 1/2] drm/i915/display/adl_p: Implement PSR changes José Roberto de Souza
2021-06-25 23:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer José Roberto de Souza
2021-07-20 19:51 ` Lucas De Marchi
2021-06-26 0:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes Patchwork
2021-06-26 0:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-26 0:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-26 1:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-20 19:48 ` [Intel-gfx] [PATCH 1/2] " Lucas De Marchi
2021-07-20 23:08 ` Souza, Jose
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