From: kernel test robot <lkp@intel.com>
To: kbuild@lists.01.org
Subject: Re: [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
Date: Sat, 26 Jun 2021 11:49:53 +0800 [thread overview]
Message-ID: <202106261103.OV3uPyOC-lkp@intel.com> (raw)
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CC: kbuild-all(a)lists.01.org
In-Reply-To: <20210622200511.3739914-4-trix@redhat.com>
References: <20210622200511.3739914-4-trix@redhat.com>
TO: trix(a)redhat.com
TO: hao.wu(a)intel.com
TO: mdf(a)kernel.org
TO: corbet(a)lwn.net
TO: michal.simek(a)xilinx.com
TO: gregkh(a)linuxfoundation.org
TO: nava.manne(a)xilinx.com
TO: dinguyen(a)kernel.org
TO: krzysztof.kozlowski(a)canonical.com
TO: yilun.xu(a)intel.com
TO: davidgow(a)google.com
Hi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.13-rc7 next-20210625]
[cannot apply to xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: i386-randconfig-m031-20210625 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/fpga/xilinx/zynq-fpga.c:626 zynq_fpga_probe() warn: 'priv->clk' not released on lines: 615.
vim +626 drivers/fpga/xilinx/zynq-fpga.c
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 552
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 553 static int zynq_fpga_probe(struct platform_device *pdev)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 554 {
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 555 struct device *dev = &pdev->dev;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 556 struct zynq_fpga_priv *priv;
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 557 struct fpga_manager *mgr;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 558 struct resource *res;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 559 int err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 560
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 561 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 562 if (!priv)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 563 return -ENOMEM;
425902f5c8e303 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 564 spin_lock_init(&priv->dma_lock);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 565
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 567 priv->io_base = devm_ioremap_resource(dev, res);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 568 if (IS_ERR(priv->io_base))
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 569 return PTR_ERR(priv->io_base);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 570
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 572 "syscon");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 573 if (IS_ERR(priv->slcr)) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 574 dev_err(dev, "unable to get zynq-slcr regmap\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 575 return PTR_ERR(priv->slcr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 576 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 577
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 578 init_completion(&priv->dma_done);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 579
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 580 priv->irq = platform_get_irq(pdev, 0);
d20c0da8b2020a drivers/fpga/zynq-fpga.c Stephen Boyd 2019-07-30 581 if (priv->irq < 0)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 582 return priv->irq;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 583
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 584 priv->clk = devm_clk_get(dev, "ref_clk");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 585 if (IS_ERR(priv->clk)) {
daec0f4a594d48 drivers/fpga/zynq-fpga.c Shubhrajyoti Datta 2020-02-12 586 if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 587 dev_err(dev, "input clock not found\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 588 return PTR_ERR(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 589 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 590
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 591 err = clk_prepare_enable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 592 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 593 dev_err(dev, "unable to enable clock\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 594 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 595 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 596
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 597 /* unlock the device */
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 598 zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 599
6b45e0f24c7b53 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 600 zynq_fpga_set_irq(priv, 0);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 601 zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 602 err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 603 priv);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 604 if (err) {
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 605 dev_err(dev, "unable to request IRQ\n");
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 606 clk_disable_unprepare(priv->clk);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 607 return err;
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 608 }
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 609
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 610 clk_disable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 611
084181fe8cc747 drivers/fpga/zynq-fpga.c Alan Tull 2018-10-15 612 mgr = devm_fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 613 &zynq_fpga_ops, priv);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 614 if (!mgr)
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 615 return -ENOMEM;
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 616
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 617 platform_set_drvdata(pdev, mgr);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 618
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 619 err = fpga_mgr_register(mgr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 620 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 621 dev_err(dev, "unable to register FPGA manager\n");
6376931babd833 drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-19 622 clk_unprepare(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 623 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 624 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 625
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 @626 return 0;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 627 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 628
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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WARNING: multiple messages have this Message-ID (diff)
From: Dan Carpenter <dan.carpenter@oracle.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
Date: Mon, 28 Jun 2021 11:46:21 +0300 [thread overview]
Message-ID: <202106261103.OV3uPyOC-lkp@intel.com> (raw)
In-Reply-To: <20210622200511.3739914-4-trix@redhat.com>
[-- Attachment #1: Type: text/plain, Size: 8367 bytes --]
Hi,
url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
config: i386-randconfig-m031-20210625 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/fpga/xilinx/zynq-fpga.c:626 zynq_fpga_probe() warn: 'priv->clk' not released on lines: 615.
vim +626 drivers/fpga/xilinx/zynq-fpga.c
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 553 static int zynq_fpga_probe(struct platform_device *pdev)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 554 {
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 555 struct device *dev = &pdev->dev;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 556 struct zynq_fpga_priv *priv;
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 557 struct fpga_manager *mgr;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 558 struct resource *res;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 559 int err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 560
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 561 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 562 if (!priv)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 563 return -ENOMEM;
425902f5c8e303 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 564 spin_lock_init(&priv->dma_lock);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 565
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 567 priv->io_base = devm_ioremap_resource(dev, res);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 568 if (IS_ERR(priv->io_base))
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 569 return PTR_ERR(priv->io_base);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 570
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 572 "syscon");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 573 if (IS_ERR(priv->slcr)) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 574 dev_err(dev, "unable to get zynq-slcr regmap\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 575 return PTR_ERR(priv->slcr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 576 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 577
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 578 init_completion(&priv->dma_done);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 579
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 580 priv->irq = platform_get_irq(pdev, 0);
d20c0da8b2020a drivers/fpga/zynq-fpga.c Stephen Boyd 2019-07-30 581 if (priv->irq < 0)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 582 return priv->irq;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 583
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 584 priv->clk = devm_clk_get(dev, "ref_clk");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 585 if (IS_ERR(priv->clk)) {
daec0f4a594d48 drivers/fpga/zynq-fpga.c Shubhrajyoti Datta 2020-02-12 586 if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 587 dev_err(dev, "input clock not found\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 588 return PTR_ERR(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 589 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 590
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 591 err = clk_prepare_enable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 592 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 593 dev_err(dev, "unable to enable clock\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 594 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 595 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 596
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 597 /* unlock the device */
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 598 zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 599
6b45e0f24c7b53 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 600 zynq_fpga_set_irq(priv, 0);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 601 zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 602 err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 603 priv);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 604 if (err) {
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 605 dev_err(dev, "unable to request IRQ\n");
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 606 clk_disable_unprepare(priv->clk);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 607 return err;
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 608 }
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 609
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 610 clk_disable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 611
084181fe8cc747 drivers/fpga/zynq-fpga.c Alan Tull 2018-10-15 612 mgr = devm_fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 613 &zynq_fpga_ops, priv);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 614 if (!mgr)
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 615 return -ENOMEM;
clk_unprepare(priv->clk);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 616
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 617 platform_set_drvdata(pdev, mgr);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 618
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 619 err = fpga_mgr_register(mgr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 620 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 621 dev_err(dev, "unable to register FPGA manager\n");
6376931babd833 drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-19 622 clk_unprepare(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 623 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 624 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 625
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 @626 return 0;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 627 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
next reply other threads:[~2021-06-26 3:49 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-26 3:49 kernel test robot [this message]
2021-06-28 8:46 ` [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout Dan Carpenter
-- strict thread matches above, loose matches on Subject: below --
2021-06-22 20:05 [PATCH v5 0/4] fpga: reorganize to subdirs trix
2021-06-22 20:05 ` trix
2021-06-22 20:05 ` [PATCH v5 1/4] fpga: dfl: reorganize to subdir layout trix
2021-06-22 20:05 ` trix
2021-06-22 20:05 ` [PATCH v5 2/4] fpga: xilinx: " trix
2021-06-22 20:05 ` trix
2021-07-05 14:48 ` kernel test robot
2021-06-22 20:05 ` [PATCH v5 3/4] fpga: altera: " trix
2021-06-22 20:05 ` trix
2021-07-02 1:56 ` kernel test robot
2021-07-02 2:43 ` Moritz Fischer
2021-06-22 20:05 ` [PATCH v5 4/4] fpga: lattice: " trix
2021-06-22 20:05 ` trix
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