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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniele.ceraolospurio@intel.com, john.c.harrison@intel.com,
	Michal.Wajdeczko@intel.com
Subject: [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers
Date: Sun, 27 Jun 2021 16:14:35 -0700	[thread overview]
Message-ID: <20210627231439.138612-4-matthew.brost@intel.com> (raw)
In-Reply-To: <20210627231439.138612-1-matthew.brost@intel.com>

With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often software hits the case where no space is available in the CTB
buffer.

Cc: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 80db59b45c45..43e03aa2dde8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -58,11 +58,16 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
  *      +--------+-----------------------------------------------+------+
  *
  * Size of each `CT Buffer`_ must be multiple of 4K.
- * As we don't expect too many messages, for now use minimum sizes.
+ * We don't expect too many messages in flight at any time, unless we are
+ * using the GuC submission. In that case each request requires a minimum
+ * 2 dwords which gives us a maximum 256 queue'd requests. Hopefully this
+ * enough space to avoid backpressure on the driver. We increase the size
+ * of the receive buffer (relative to the send) to ensure a G2H response
+ * CTB has a landing spot.
  */
 #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
 #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
-#define CTB_G2H_BUFFER_SIZE	(SZ_4K)
+#define CTB_G2H_BUFFER_SIZE	(4 * CTB_H2G_BUFFER_SIZE)
 
 struct ct_request {
 	struct list_head link;
@@ -643,7 +648,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
 	/* beware of buffer wrap case */
 	if (unlikely(available < 0))
 		available += size;
-	CT_DEBUG(ct, "available %d (%u:%u)\n", available, head, tail);
+	CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
 	GEM_BUG_ON(available < 0);
 
 	header = cmds[head];
-- 
2.28.0


WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers
Date: Sun, 27 Jun 2021 16:14:35 -0700	[thread overview]
Message-ID: <20210627231439.138612-4-matthew.brost@intel.com> (raw)
In-Reply-To: <20210627231439.138612-1-matthew.brost@intel.com>

With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often software hits the case where no space is available in the CTB
buffer.

Cc: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 80db59b45c45..43e03aa2dde8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -58,11 +58,16 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
  *      +--------+-----------------------------------------------+------+
  *
  * Size of each `CT Buffer`_ must be multiple of 4K.
- * As we don't expect too many messages, for now use minimum sizes.
+ * We don't expect too many messages in flight at any time, unless we are
+ * using the GuC submission. In that case each request requires a minimum
+ * 2 dwords which gives us a maximum 256 queue'd requests. Hopefully this
+ * enough space to avoid backpressure on the driver. We increase the size
+ * of the receive buffer (relative to the send) to ensure a G2H response
+ * CTB has a landing spot.
  */
 #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
 #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
-#define CTB_G2H_BUFFER_SIZE	(SZ_4K)
+#define CTB_G2H_BUFFER_SIZE	(4 * CTB_H2G_BUFFER_SIZE)
 
 struct ct_request {
 	struct list_head link;
@@ -643,7 +648,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
 	/* beware of buffer wrap case */
 	if (unlikely(available < 0))
 		available += size;
-	CT_DEBUG(ct, "available %d (%u:%u)\n", available, head, tail);
+	CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
 	GEM_BUG_ON(available < 0);
 
 	header = cmds[head];
-- 
2.28.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-06-27 22:57 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-27 23:14 [PATCH 0/7] CT changes required for GuC submission Matthew Brost
2021-06-27 23:14 ` [Intel-gfx] " Matthew Brost
2021-06-27 23:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-06-27 23:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-27 23:14 ` [PATCH 1/7] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-27 23:14   ` [Intel-gfx] " Matthew Brost
2021-06-27 23:14 ` [PATCH 2/7] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-27 23:14   ` [Intel-gfx] " Matthew Brost
2021-06-27 23:14 ` Matthew Brost [this message]
2021-06-27 23:14   ` [Intel-gfx] [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-27 23:14 ` [PATCH 4/7] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-27 23:14   ` [Intel-gfx] " Matthew Brost
2021-06-30 22:52   ` Michal Wajdeczko
2021-06-30 22:52     ` [Intel-gfx] " Michal Wajdeczko
2021-07-01  0:19     ` Matthew Brost
2021-07-01  0:19       ` [Intel-gfx] " Matthew Brost
2021-06-27 23:14 ` [PATCH 5/7] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-27 23:14   ` [Intel-gfx] " Matthew Brost
2021-06-30 23:23   ` Michal Wajdeczko
2021-06-30 23:23     ` [Intel-gfx] " Michal Wajdeczko
2021-07-01  0:36     ` Matthew Brost
2021-07-01  0:36       ` [Intel-gfx] " Matthew Brost
2021-06-27 23:14 ` [PATCH 6/7] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-27 23:14   ` [Intel-gfx] " Matthew Brost
2021-06-27 23:14 ` [PATCH 7/7] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-27 23:14   ` [Intel-gfx] " Matthew Brost
2021-06-27 23:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for CT changes required for GuC submission Patchwork
2021-06-28  0:51 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-01 17:15 [PATCH 0/7] " Matthew Brost
2021-07-01 17:15 ` [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-07-06 22:20 [PATCH 0/7] CT changes required for GuC submission Matthew Brost
2021-07-06 22:20 ` [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-07-08 16:20 [PATCH 0/7] CT changes required for GuC submission Matthew Brost
2021-07-08 16:20 ` [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers Matthew Brost

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