* [PATCH v5 1/7] platform/x86: amd-pmc: Fix command completion code
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
@ 2021-06-29 8:47 ` Shyam Sundar S K
2021-07-06 9:58 ` Hans de Goede
2021-06-29 8:47 ` [PATCH v5 2/7] platform/x86: amd-pmc: Fix SMU firmware reporting mechanism Shyam Sundar S K
` (6 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:47 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
The protocol to submit a job request to SMU is to wait for
AMD_PMC_REGISTER_RESPONSE to return 1,meaning SMU is ready to take
requests. PMC driver has to make sure that the response code is always
AMD_PMC_RESULT_OK before making any command submissions.
When we submit a message to SMU, we have to wait until it processes
the request. Adding a read_poll_timeout() check as this was missing in
the existing code.
Also, add a mutex to protect amd_pmc_send_cmd() calls to SMU.
Fixes: 156ec4731cb2 ("platform/x86: amd-pmc: Add AMD platform support for S2Idle")
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Acked-by: Raul E Rangel <rrangel@chromium.org>
---
v2: no change
v3:
- use mutex to protect multiple calls to SMU
- add a switch-case to handle smu responses.
v4:
- Handle different error codes based on smu responses.
v5:
- Remove redundant rc assignment as pointed by Raul
drivers/platform/x86/amd-pmc.c | 38 ++++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index b9da58ee9b1e..1b5f149932c1 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -68,6 +68,7 @@ struct amd_pmc_dev {
u32 base_addr;
u32 cpu_id;
struct device *dev;
+ struct mutex lock; /* generic mutex lock */
#if IS_ENABLED(CONFIG_DEBUG_FS)
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
@@ -138,9 +139,10 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
u8 msg;
u32 val;
+ mutex_lock(&dev->lock);
/* Wait until we get a valid response */
rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
- val, val > 0, PMC_MSG_DELAY_MIN_US,
+ val, val != 0, PMC_MSG_DELAY_MIN_US,
PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
if (rc) {
dev_err(dev->dev, "failed to talk to SMU\n");
@@ -156,7 +158,37 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
/* Write message ID to message ID register */
msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
- return 0;
+ /* Wait until we get a valid response */
+ rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
+ val, val != 0, PMC_MSG_DELAY_MIN_US,
+ PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
+ if (rc) {
+ dev_err(dev->dev, "SMU response timed out\n");
+ goto out_unlock;
+ }
+
+ switch (val) {
+ case AMD_PMC_RESULT_OK:
+ break;
+ case AMD_PMC_RESULT_CMD_REJECT_BUSY:
+ dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
+ rc = -EBUSY;
+ goto out_unlock;
+ case AMD_PMC_RESULT_CMD_UNKNOWN:
+ dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
+ rc = -EINVAL;
+ goto out_unlock;
+ case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
+ case AMD_PMC_RESULT_FAILED:
+ default:
+ dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
+ rc = -EIO;
+ goto out_unlock;
+ }
+
+out_unlock:
+ mutex_unlock(&dev->lock);
+ return rc;
}
static int __maybe_unused amd_pmc_suspend(struct device *dev)
@@ -259,6 +291,7 @@ static int amd_pmc_probe(struct platform_device *pdev)
amd_pmc_dump_registers(dev);
+ mutex_init(&dev->lock);
platform_set_drvdata(pdev, dev);
amd_pmc_dbgfs_register(dev);
return 0;
@@ -269,6 +302,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
amd_pmc_dbgfs_unregister(dev);
+ mutex_destroy(&dev->lock);
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v5 1/7] platform/x86: amd-pmc: Fix command completion code
2021-06-29 8:47 ` [PATCH v5 1/7] platform/x86: amd-pmc: Fix command completion code Shyam Sundar S K
@ 2021-07-06 9:58 ` Hans de Goede
0 siblings, 0 replies; 12+ messages in thread
From: Hans de Goede @ 2021-07-06 9:58 UTC (permalink / raw)
To: Shyam Sundar S K, mgross, rrangel; +Cc: platform-driver-x86
Hi,
On 6/29/21 10:47 AM, Shyam Sundar S K wrote:
> The protocol to submit a job request to SMU is to wait for
> AMD_PMC_REGISTER_RESPONSE to return 1,meaning SMU is ready to take
> requests. PMC driver has to make sure that the response code is always
> AMD_PMC_RESULT_OK before making any command submissions.
>
> When we submit a message to SMU, we have to wait until it processes
> the request. Adding a read_poll_timeout() check as this was missing in
> the existing code.
>
> Also, add a mutex to protect amd_pmc_send_cmd() calls to SMU.
>
> Fixes: 156ec4731cb2 ("platform/x86: amd-pmc: Add AMD platform support for S2Idle")
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> Acked-by: Raul E Rangel <rrangel@chromium.org>
> ---
> v2: no change
> v3:
> - use mutex to protect multiple calls to SMU
> - add a switch-case to handle smu responses.
> v4:
> - Handle different error codes based on smu responses.
> v5:
> - Remove redundant rc assignment as pointed by Raul
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
I'll apply this to the platform-drivers-x86 tree once 5.14-rc1 out,
since this is just a bunch of fixes + some new hw-ids I'll also
include this series in my next pdx86-fixes for 5.14 pull-req to Linus.
Regards,
Hans
>
> drivers/platform/x86/amd-pmc.c | 38 ++++++++++++++++++++++++++++++++--
> 1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
> index b9da58ee9b1e..1b5f149932c1 100644
> --- a/drivers/platform/x86/amd-pmc.c
> +++ b/drivers/platform/x86/amd-pmc.c
> @@ -68,6 +68,7 @@ struct amd_pmc_dev {
> u32 base_addr;
> u32 cpu_id;
> struct device *dev;
> + struct mutex lock; /* generic mutex lock */
> #if IS_ENABLED(CONFIG_DEBUG_FS)
> struct dentry *dbgfs_dir;
> #endif /* CONFIG_DEBUG_FS */
> @@ -138,9 +139,10 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
> u8 msg;
> u32 val;
>
> + mutex_lock(&dev->lock);
> /* Wait until we get a valid response */
> rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
> - val, val > 0, PMC_MSG_DELAY_MIN_US,
> + val, val != 0, PMC_MSG_DELAY_MIN_US,
> PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
> if (rc) {
> dev_err(dev->dev, "failed to talk to SMU\n");
> @@ -156,7 +158,37 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
> /* Write message ID to message ID register */
> msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
> amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
> - return 0;
> + /* Wait until we get a valid response */
> + rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
> + val, val != 0, PMC_MSG_DELAY_MIN_US,
> + PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
> + if (rc) {
> + dev_err(dev->dev, "SMU response timed out\n");
> + goto out_unlock;
> + }
> +
> + switch (val) {
> + case AMD_PMC_RESULT_OK:
> + break;
> + case AMD_PMC_RESULT_CMD_REJECT_BUSY:
> + dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
> + rc = -EBUSY;
> + goto out_unlock;
> + case AMD_PMC_RESULT_CMD_UNKNOWN:
> + dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
> + rc = -EINVAL;
> + goto out_unlock;
> + case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
> + case AMD_PMC_RESULT_FAILED:
> + default:
> + dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
> + rc = -EIO;
> + goto out_unlock;
> + }
> +
> +out_unlock:
> + mutex_unlock(&dev->lock);
> + return rc;
> }
>
> static int __maybe_unused amd_pmc_suspend(struct device *dev)
> @@ -259,6 +291,7 @@ static int amd_pmc_probe(struct platform_device *pdev)
>
> amd_pmc_dump_registers(dev);
>
> + mutex_init(&dev->lock);
> platform_set_drvdata(pdev, dev);
> amd_pmc_dbgfs_register(dev);
> return 0;
> @@ -269,6 +302,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
> struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
>
> amd_pmc_dbgfs_unregister(dev);
> + mutex_destroy(&dev->lock);
> return 0;
> }
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 2/7] platform/x86: amd-pmc: Fix SMU firmware reporting mechanism
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
2021-06-29 8:47 ` [PATCH v5 1/7] platform/x86: amd-pmc: Fix command completion code Shyam Sundar S K
@ 2021-06-29 8:47 ` Shyam Sundar S K
2021-07-06 9:59 ` Hans de Goede
2021-06-29 8:47 ` [PATCH v5 3/7] platform/x86: amd-pmc: call dump registers only once Shyam Sundar S K
` (5 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:47 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
It was lately understood that the current mechanism available in the
driver to get SMU firmware info works only on internal SMU builds and
there is a separate way to get all the SMU logging counters (addressed
in the next patch). Hence remove all the smu info shown via debugfs as it
is no more useful.
Fixes: 156ec4731cb2 ("platform/x86: amd-pmc: Add AMD platform support for S2Idle")
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
v2: split into multiple patches as suggested by Hans
v3: No change
v4: No change
v5: NO change
drivers/platform/x86/amd-pmc.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index 1b5f149932c1..b1d6175a13b2 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -52,7 +52,6 @@
#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
-#define AMD_SMU_FW_VERSION 0x0
#define PMC_MSG_DELAY_MIN_US 100
#define RESPONSE_REGISTER_LOOP_MAX 200
@@ -89,11 +88,6 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
#ifdef CONFIG_DEBUG_FS
static int smu_fw_info_show(struct seq_file *s, void *unused)
{
- struct amd_pmc_dev *dev = s->private;
- u32 value;
-
- value = ioread32(dev->smu_base + AMD_SMU_FW_VERSION);
- seq_printf(s, "SMU FW Info: %x\n", value);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
@@ -280,10 +274,6 @@ static int amd_pmc_probe(struct platform_device *pdev)
pci_dev_put(rdev);
base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
- dev->smu_base = devm_ioremap(dev->dev, base_addr, AMD_PMC_MAPPING_SIZE);
- if (!dev->smu_base)
- return -ENOMEM;
-
dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
AMD_PMC_MAPPING_SIZE);
if (!dev->regbase)
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v5 2/7] platform/x86: amd-pmc: Fix SMU firmware reporting mechanism
2021-06-29 8:47 ` [PATCH v5 2/7] platform/x86: amd-pmc: Fix SMU firmware reporting mechanism Shyam Sundar S K
@ 2021-07-06 9:59 ` Hans de Goede
0 siblings, 0 replies; 12+ messages in thread
From: Hans de Goede @ 2021-07-06 9:59 UTC (permalink / raw)
To: Shyam Sundar S K, mgross, rrangel; +Cc: platform-driver-x86
Hi,
On 6/29/21 10:47 AM, Shyam Sundar S K wrote:
> It was lately understood that the current mechanism available in the
> driver to get SMU firmware info works only on internal SMU builds and
> there is a separate way to get all the SMU logging counters (addressed
> in the next patch). Hence remove all the smu info shown via debugfs as it
> is no more useful.
>
> Fixes: 156ec4731cb2 ("platform/x86: amd-pmc: Add AMD platform support for S2Idle")
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
> v2: split into multiple patches as suggested by Hans
> v3: No change
> v4: No change
> v5: NO change
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
>
> drivers/platform/x86/amd-pmc.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
> index 1b5f149932c1..b1d6175a13b2 100644
> --- a/drivers/platform/x86/amd-pmc.c
> +++ b/drivers/platform/x86/amd-pmc.c
> @@ -52,7 +52,6 @@
> #define AMD_CPU_ID_PCO AMD_CPU_ID_RV
> #define AMD_CPU_ID_CZN AMD_CPU_ID_RN
>
> -#define AMD_SMU_FW_VERSION 0x0
> #define PMC_MSG_DELAY_MIN_US 100
> #define RESPONSE_REGISTER_LOOP_MAX 200
>
> @@ -89,11 +88,6 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
> #ifdef CONFIG_DEBUG_FS
> static int smu_fw_info_show(struct seq_file *s, void *unused)
> {
> - struct amd_pmc_dev *dev = s->private;
> - u32 value;
> -
> - value = ioread32(dev->smu_base + AMD_SMU_FW_VERSION);
> - seq_printf(s, "SMU FW Info: %x\n", value);
> return 0;
> }
> DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
> @@ -280,10 +274,6 @@ static int amd_pmc_probe(struct platform_device *pdev)
> pci_dev_put(rdev);
> base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
>
> - dev->smu_base = devm_ioremap(dev->dev, base_addr, AMD_PMC_MAPPING_SIZE);
> - if (!dev->smu_base)
> - return -ENOMEM;
> -
> dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
> AMD_PMC_MAPPING_SIZE);
> if (!dev->regbase)
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 3/7] platform/x86: amd-pmc: call dump registers only once
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
2021-06-29 8:47 ` [PATCH v5 1/7] platform/x86: amd-pmc: Fix command completion code Shyam Sundar S K
2021-06-29 8:47 ` [PATCH v5 2/7] platform/x86: amd-pmc: Fix SMU firmware reporting mechanism Shyam Sundar S K
@ 2021-06-29 8:47 ` Shyam Sundar S K
2021-07-06 9:59 ` Hans de Goede
2021-06-29 8:48 ` [PATCH v5 4/7] platform/x86: amd-pmc: Add support for logging SMU metrics Shyam Sundar S K
` (4 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:47 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
Currently amd_pmc_dump_registers() routine is being called at
multiple places. The best to call it is after command submission
to SMU.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
v2: split into multiple patches as suggested by Hans
v3: No change
v4: No change
v5: No change
drivers/platform/x86/amd-pmc.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index b1d6175a13b2..e5107e3b1911 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -182,6 +182,7 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
out_unlock:
mutex_unlock(&dev->lock);
+ amd_pmc_dump_registers(dev);
return rc;
}
@@ -194,7 +195,6 @@ static int __maybe_unused amd_pmc_suspend(struct device *dev)
if (rc)
dev_err(pdev->dev, "suspend failed\n");
- amd_pmc_dump_registers(pdev);
return 0;
}
@@ -207,7 +207,6 @@ static int __maybe_unused amd_pmc_resume(struct device *dev)
if (rc)
dev_err(pdev->dev, "resume failed\n");
- amd_pmc_dump_registers(pdev);
return 0;
}
@@ -279,8 +278,6 @@ static int amd_pmc_probe(struct platform_device *pdev)
if (!dev->regbase)
return -ENOMEM;
- amd_pmc_dump_registers(dev);
-
mutex_init(&dev->lock);
platform_set_drvdata(pdev, dev);
amd_pmc_dbgfs_register(dev);
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/7] platform/x86: amd-pmc: call dump registers only once
2021-06-29 8:47 ` [PATCH v5 3/7] platform/x86: amd-pmc: call dump registers only once Shyam Sundar S K
@ 2021-07-06 9:59 ` Hans de Goede
0 siblings, 0 replies; 12+ messages in thread
From: Hans de Goede @ 2021-07-06 9:59 UTC (permalink / raw)
To: Shyam Sundar S K, mgross, rrangel; +Cc: platform-driver-x86
Hi,
On 6/29/21 10:47 AM, Shyam Sundar S K wrote:
> Currently amd_pmc_dump_registers() routine is being called at
> multiple places. The best to call it is after command submission
> to SMU.
>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
> v2: split into multiple patches as suggested by Hans
> v3: No change
> v4: No change
> v5: No change
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
>
> drivers/platform/x86/amd-pmc.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
> index b1d6175a13b2..e5107e3b1911 100644
> --- a/drivers/platform/x86/amd-pmc.c
> +++ b/drivers/platform/x86/amd-pmc.c
> @@ -182,6 +182,7 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
>
> out_unlock:
> mutex_unlock(&dev->lock);
> + amd_pmc_dump_registers(dev);
> return rc;
> }
>
> @@ -194,7 +195,6 @@ static int __maybe_unused amd_pmc_suspend(struct device *dev)
> if (rc)
> dev_err(pdev->dev, "suspend failed\n");
>
> - amd_pmc_dump_registers(pdev);
> return 0;
> }
>
> @@ -207,7 +207,6 @@ static int __maybe_unused amd_pmc_resume(struct device *dev)
> if (rc)
> dev_err(pdev->dev, "resume failed\n");
>
> - amd_pmc_dump_registers(pdev);
> return 0;
> }
>
> @@ -279,8 +278,6 @@ static int amd_pmc_probe(struct platform_device *pdev)
> if (!dev->regbase)
> return -ENOMEM;
>
> - amd_pmc_dump_registers(dev);
> -
> mutex_init(&dev->lock);
> platform_set_drvdata(pdev, dev);
> amd_pmc_dbgfs_register(dev);
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 4/7] platform/x86: amd-pmc: Add support for logging SMU metrics
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
` (2 preceding siblings ...)
2021-06-29 8:47 ` [PATCH v5 3/7] platform/x86: amd-pmc: call dump registers only once Shyam Sundar S K
@ 2021-06-29 8:48 ` Shyam Sundar S K
2021-06-29 8:48 ` [PATCH v5 5/7] amd-pmc: Add support for logging s0ix counters Shyam Sundar S K
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:48 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
SMU provides a way to dump the s0ix debug statistics in the form of a
metrics table via a of set special mailbox commands.
Add support to the driver which can send these commands to SMU and expose
the information received via debugfs. The information contains the s0ix
entry/exit, active time of each IP block etc.
As a side note, SMU subsystem logging is not supported on Picasso based
SoC's.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
v2: No change
v3: No change
v4: No change
v5: No change
drivers/platform/x86/amd-pmc.c | 147 +++++++++++++++++++++++++++++++--
1 file changed, 139 insertions(+), 8 deletions(-)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index e5107e3b1911..0ebb2732c46a 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -46,6 +46,14 @@
#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
#define AMD_PMC_RESULT_FAILED 0xFF
+/* SMU Message Definations */
+#define SMU_MSG_GETSMUVERSION 0x02
+#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
+#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
+#define SMU_MSG_LOG_START 0x06
+#define SMU_MSG_LOG_RESET 0x07
+#define SMU_MSG_LOG_DUMP_DATA 0x08
+#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
/* List of supported CPU ids */
#define AMD_CPU_ID_RV 0x15D0
#define AMD_CPU_ID_RN 0x1630
@@ -55,17 +63,42 @@
#define PMC_MSG_DELAY_MIN_US 100
#define RESPONSE_REGISTER_LOOP_MAX 200
+#define SOC_SUBSYSTEM_IP_MAX 12
+#define DELAY_MIN_US 2000
+#define DELAY_MAX_US 3000
enum amd_pmc_def {
MSG_TEST = 0x01,
MSG_OS_HINT_PCO,
MSG_OS_HINT_RN,
};
+struct amd_pmc_bit_map {
+ const char *name;
+ u32 bit_mask;
+};
+
+static const struct amd_pmc_bit_map soc15_ip_blk[] = {
+ {"DISPLAY", BIT(0)},
+ {"CPU", BIT(1)},
+ {"GFX", BIT(2)},
+ {"VDD", BIT(3)},
+ {"ACP", BIT(4)},
+ {"VCN", BIT(5)},
+ {"ISP", BIT(6)},
+ {"NBIO", BIT(7)},
+ {"DF", BIT(8)},
+ {"USB0", BIT(9)},
+ {"USB1", BIT(10)},
+ {"LAPIC", BIT(11)},
+ {}
+};
+
struct amd_pmc_dev {
void __iomem *regbase;
- void __iomem *smu_base;
+ void __iomem *smu_virt_addr;
u32 base_addr;
u32 cpu_id;
+ u32 active_ips;
struct device *dev;
struct mutex lock; /* generic mutex lock */
#if IS_ENABLED(CONFIG_DEBUG_FS)
@@ -74,6 +107,7 @@ struct amd_pmc_dev {
};
static struct amd_pmc_dev pmc;
+static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret);
static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
{
@@ -85,9 +119,49 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
iowrite32(val, dev->regbase + reg_offset);
}
+struct smu_metrics {
+ u32 table_version;
+ u32 hint_count;
+ u32 s0i3_cyclecount;
+ u32 timein_s0i2;
+ u64 timeentering_s0i3_lastcapture;
+ u64 timeentering_s0i3_totaltime;
+ u64 timeto_resume_to_os_lastcapture;
+ u64 timeto_resume_to_os_totaltime;
+ u64 timein_s0i3_lastcapture;
+ u64 timein_s0i3_totaltime;
+ u64 timein_swdrips_lastcapture;
+ u64 timein_swdrips_totaltime;
+ u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
+ u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
+} __packed;
+
#ifdef CONFIG_DEBUG_FS
static int smu_fw_info_show(struct seq_file *s, void *unused)
{
+ struct amd_pmc_dev *dev = s->private;
+ struct smu_metrics table;
+ int idx;
+
+ if (dev->cpu_id == AMD_CPU_ID_PCO)
+ return -EINVAL;
+
+ memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
+
+ seq_puts(s, "\n=== SMU Statistics ===\n");
+ seq_printf(s, "Table Version: %d\n", table.table_version);
+ seq_printf(s, "Hint Count: %d\n", table.hint_count);
+ seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount);
+ seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
+ seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
+
+ seq_puts(s, "\n=== Active time (in us) ===\n");
+ for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
+ if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
+ seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
+ table.timecondition_notmet_lastcapture[idx]);
+ }
+
return 0;
}
DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
@@ -113,6 +187,32 @@ static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
}
#endif /* CONFIG_DEBUG_FS */
+static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
+{
+ u32 phys_addr_low, phys_addr_hi;
+ u64 smu_phys_addr;
+
+ if (dev->cpu_id == AMD_CPU_ID_PCO)
+ return -EINVAL;
+
+ /* Get Active devices list from SMU */
+ amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
+
+ /* Get dram address */
+ amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
+ amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
+ smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
+
+ dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
+ if (!dev->smu_virt_addr)
+ return -ENOMEM;
+
+ /* Start the logging */
+ amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
+
+ return 0;
+}
+
static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
{
u32 value;
@@ -127,10 +227,9 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
}
-static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
+static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret)
{
int rc;
- u8 msg;
u32 val;
mutex_lock(&dev->lock);
@@ -150,8 +249,8 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
/* Write message ID to message ID register */
- msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
+
/* Wait until we get a valid response */
rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
val, val != 0, PMC_MSG_DELAY_MIN_US,
@@ -163,6 +262,11 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
switch (val) {
case AMD_PMC_RESULT_OK:
+ if (ret) {
+ /* PMFW may take longer time to return back the data */
+ usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
+ *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
+ }
break;
case AMD_PMC_RESULT_CMD_REJECT_BUSY:
dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
@@ -186,12 +290,29 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
return rc;
}
+static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
+{
+ switch (dev->cpu_id) {
+ case AMD_CPU_ID_PCO:
+ return MSG_OS_HINT_PCO;
+ case AMD_CPU_ID_RN:
+ return MSG_OS_HINT_RN;
+ }
+ return -EINVAL;
+}
+
static int __maybe_unused amd_pmc_suspend(struct device *dev)
{
struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
int rc;
+ u8 msg;
- rc = amd_pmc_send_cmd(pdev, 1);
+ /* Reset and Start SMU logging - to monitor the s0i3 stats */
+ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
+ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
+
+ msg = amd_pmc_get_os_hint(pdev);
+ rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0);
if (rc)
dev_err(pdev->dev, "suspend failed\n");
@@ -202,8 +323,13 @@ static int __maybe_unused amd_pmc_resume(struct device *dev)
{
struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
int rc;
+ u8 msg;
- rc = amd_pmc_send_cmd(pdev, 0);
+ /* Let SMU know that we are looking for stats */
+ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
+
+ msg = amd_pmc_get_os_hint(pdev);
+ rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
if (rc)
dev_err(pdev->dev, "resume failed\n");
@@ -226,8 +352,7 @@ static int amd_pmc_probe(struct platform_device *pdev)
{
struct amd_pmc_dev *dev = &pmc;
struct pci_dev *rdev;
- u32 base_addr_lo;
- u32 base_addr_hi;
+ u32 base_addr_lo, base_addr_hi;
u64 base_addr;
int err;
u32 val;
@@ -279,6 +404,12 @@ static int amd_pmc_probe(struct platform_device *pdev)
return -ENOMEM;
mutex_init(&dev->lock);
+
+ /* Use SMU to get the s0i3 debug stats */
+ err = amd_pmc_setup_smu_logging(dev);
+ if (err)
+ dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
+
platform_set_drvdata(pdev, dev);
amd_pmc_dbgfs_register(dev);
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 5/7] amd-pmc: Add support for logging s0ix counters
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
` (3 preceding siblings ...)
2021-06-29 8:48 ` [PATCH v5 4/7] platform/x86: amd-pmc: Add support for logging SMU metrics Shyam Sundar S K
@ 2021-06-29 8:48 ` Shyam Sundar S K
2021-06-29 8:48 ` [PATCH v5 6/7] platform/x86: amd-pmc: Add support for ACPI ID AMDI0006 Shyam Sundar S K
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:48 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
Even the FCH SSC registers provides certain level of information
about the s0ix entry and exit times which comes handy when the SMU
fails to report the statistics via the mailbox communication.
This information is captured via a new debugfs file "s0ix_stats".
A non-zero entry in this counters would mean that the system entered
the s0ix state.
If s0ix entry time and exit time don't change during suspend to idle,
the silicon has not entered the deepest state.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
v2: No change
v3: No change
v4: No change
v5: No change
drivers/platform/x86/amd-pmc.c | 45 +++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index 0ebb2732c46a..7f011c3f60f2 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -46,6 +46,15 @@
#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
#define AMD_PMC_RESULT_FAILED 0xFF
+/* FCH SSC Registers */
+#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
+#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
+#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
+#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
+#define FCH_SSC_MAPPING_SIZE 0x800
+#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
+#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
+
/* SMU Message Definations */
#define SMU_MSG_GETSMUVERSION 0x02
#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
@@ -96,6 +105,7 @@ static const struct amd_pmc_bit_map soc15_ip_blk[] = {
struct amd_pmc_dev {
void __iomem *regbase;
void __iomem *smu_virt_addr;
+ void __iomem *fch_virt_addr;
u32 base_addr;
u32 cpu_id;
u32 active_ips;
@@ -166,6 +176,29 @@ static int smu_fw_info_show(struct seq_file *s, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
+static int s0ix_stats_show(struct seq_file *s, void *unused)
+{
+ struct amd_pmc_dev *dev = s->private;
+ u64 entry_time, exit_time, residency;
+
+ entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
+ entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
+
+ exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
+ exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
+
+ /* It's in 48MHz. We need to convert it */
+ residency = (exit_time - entry_time) / 48;
+
+ seq_puts(s, "=== S0ix statistics ===\n");
+ seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
+ seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
+ seq_printf(s, "Residency Time: %lld\n", residency);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
+
static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
{
debugfs_remove_recursive(dev->dbgfs_dir);
@@ -176,6 +209,8 @@ static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
&smu_fw_info_fops);
+ debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
+ &s0ix_stats_fops);
}
#else
static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
@@ -353,7 +388,7 @@ static int amd_pmc_probe(struct platform_device *pdev)
struct amd_pmc_dev *dev = &pmc;
struct pci_dev *rdev;
u32 base_addr_lo, base_addr_hi;
- u64 base_addr;
+ u64 base_addr, fch_phys_addr;
int err;
u32 val;
@@ -405,6 +440,14 @@ static int amd_pmc_probe(struct platform_device *pdev)
mutex_init(&dev->lock);
+ /* Use FCH registers to get the S0ix stats */
+ base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
+ base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
+ fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
+ dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
+ if (!dev->fch_virt_addr)
+ return -ENOMEM;
+
/* Use SMU to get the s0i3 debug stats */
err = amd_pmc_setup_smu_logging(dev);
if (err)
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 6/7] platform/x86: amd-pmc: Add support for ACPI ID AMDI0006
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
` (4 preceding siblings ...)
2021-06-29 8:48 ` [PATCH v5 5/7] amd-pmc: Add support for logging s0ix counters Shyam Sundar S K
@ 2021-06-29 8:48 ` Shyam Sundar S K
2021-06-29 8:48 ` [PATCH v5 7/7] platform/x86: amd-pmc: Add new acpi id for future PMC controllers Shyam Sundar S K
2021-07-14 13:12 ` [PATCH v5 0/7] updates to amd-pmc driver Hans de Goede
7 siblings, 0 replies; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:48 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
Some newer BIOSes have added another ACPI ID for the uPEP device.
SMU statistics behave identically on this device.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
v2: No change
v3: No change
v4: No change
v5: No change
drivers/platform/x86/amd-pmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index 7f011c3f60f2..c5054fa2aed9 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -469,6 +469,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
static const struct acpi_device_id amd_pmc_acpi_ids[] = {
{"AMDI0005", 0},
+ {"AMDI0006", 0},
{"AMD0004", 0},
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 7/7] platform/x86: amd-pmc: Add new acpi id for future PMC controllers
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
` (5 preceding siblings ...)
2021-06-29 8:48 ` [PATCH v5 6/7] platform/x86: amd-pmc: Add support for ACPI ID AMDI0006 Shyam Sundar S K
@ 2021-06-29 8:48 ` Shyam Sundar S K
2021-07-14 13:12 ` [PATCH v5 0/7] updates to amd-pmc driver Hans de Goede
7 siblings, 0 replies; 12+ messages in thread
From: Shyam Sundar S K @ 2021-06-29 8:48 UTC (permalink / raw)
To: hdegoede, mgross, rrangel; +Cc: platform-driver-x86, Shyam Sundar S K
The upcoming PMC controller would have a newer acpi id, add that to
the supported acpid device list.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
v2: No change
v3: No change
v4: No change
v5: No change
drivers/platform/x86/amd-pmc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
index c5054fa2aed9..d2f9a62e1166 100644
--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -68,6 +68,7 @@
#define AMD_CPU_ID_RN 0x1630
#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
+#define AMD_CPU_ID_YC 0x14B5
#define PMC_MSG_DELAY_MIN_US 100
#define RESPONSE_REGISTER_LOOP_MAX 200
@@ -331,6 +332,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
case AMD_CPU_ID_PCO:
return MSG_OS_HINT_PCO;
case AMD_CPU_ID_RN:
+ case AMD_CPU_ID_YC:
return MSG_OS_HINT_RN;
}
return -EINVAL;
@@ -376,6 +378,7 @@ static const struct dev_pm_ops amd_pmc_pm_ops = {
};
static const struct pci_device_id pmc_pci_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
@@ -470,6 +473,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
static const struct acpi_device_id amd_pmc_acpi_ids[] = {
{"AMDI0005", 0},
{"AMDI0006", 0},
+ {"AMDI0007", 0},
{"AMD0004", 0},
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v5 0/7] updates to amd-pmc driver
2021-06-29 8:47 [PATCH v5 0/7] updates to amd-pmc driver Shyam Sundar S K
` (6 preceding siblings ...)
2021-06-29 8:48 ` [PATCH v5 7/7] platform/x86: amd-pmc: Add new acpi id for future PMC controllers Shyam Sundar S K
@ 2021-07-14 13:12 ` Hans de Goede
7 siblings, 0 replies; 12+ messages in thread
From: Hans de Goede @ 2021-07-14 13:12 UTC (permalink / raw)
To: Shyam Sundar S K, mgross, rrangel; +Cc: platform-driver-x86
Hi,
On 6/29/21 10:47 AM, Shyam Sundar S K wrote:
> Couple of existing issues on the completion codes to SMU
> and a newer way to get the s0ix statistics are introduced.
>
> Also, add acpi ids for current and future revisions of the
> pmc controller.
>
> Shyam Sundar S K (7):
> platform/x86: amd-pmc: Fix command completion code
> platform/x86: amd-pmc: Fix SMU firmware reporting mechanism
> platform/x86: amd-pmc: call dump registers only once
> platform/x86: amd-pmc: Add support for logging SMU metrics
> amd-pmc: Add support for logging s0ix counters
> platform/x86: amd-pmc: Add support for ACPI ID AMDI0006
> platform/x86: amd-pmc: Add new acpi id for future PMC controllers
Thank you for your patch-series, I've applied the series to my
review-hans branch:
https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/log/?h=review-hans
I will also apply this to the fixes branch and include it in my
upcoming v5.14 pdx86 fixes pull-req to Linus.
Once I've run some tests on this branch the patches there will be
added to the platform-drivers-x86/for-next branch and eventually
will be included in the pdx86 pull-request to Linus for the next
merge-window.
Regards,
Hans
^ permalink raw reply [flat|nested] 12+ messages in thread