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From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: jitao.shi@mediatek.com, chunkuang.hu@kernel.org,
	matthias.bgg@gmail.com, drinkcat@chromium.org,
	eizan@chromium.org, kernel@collabora.com,
	linux-mediatek@lists.infradead.org, hsinyi@chromium.org,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/6] arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
Date: Wed, 30 Jun 2021 16:46:44 +0200	[thread overview]
Message-ID: <20210630164623.4.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid> (raw)
In-Reply-To: <20210630144646.868702-1-enric.balletbo@collabora.com>

Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

While here, also remove the undocumented and also not used
'mediatek,syscon-dsi' property.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---

 arch/arm64/boot/dts/mediatek/mt8183.dtsi  | 3 ++-
 include/dt-bindings/reset/mt8183-resets.h | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 085e2c96b5f4..2d02365633c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1286,6 +1286,7 @@ mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8183-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
 				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1400,11 +1401,11 @@ dsi0: dsi@14014000 {
 			reg = <0 0x14014000 0 0x1000>;
 			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
-			mediatek,syscon-dsi = <&mmsys 0x140>;
 			clocks = <&mmsys CLK_MM_DSI0_MM>,
 				 <&mmsys CLK_MM_DSI0_IF>,
 				 <&mipi_tx0>;
 			clock-names = "engine", "digital", "hs";
+			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
 			phys = <&mipi_tx0>;
 			phy-names = "dphy";
 		};
diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h
index a1bbd41e0d12..48c5d2de0a38 100644
--- a/include/dt-bindings/reset/mt8183-resets.h
+++ b/include/dt-bindings/reset/mt8183-resets.h
@@ -80,6 +80,9 @@
 
 #define MT8183_INFRACFG_SW_RST_NUM				128
 
+/* MMSYS resets */
+#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0			25
+
 #define MT8183_TOPRGU_MM_SW_RST					1
 #define MT8183_TOPRGU_MFG_SW_RST				2
 #define MT8183_TOPRGU_VENC_SW_RST				3
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: jitao.shi@mediatek.com, chunkuang.hu@kernel.org,
	matthias.bgg@gmail.com, drinkcat@chromium.org,
	eizan@chromium.org, kernel@collabora.com,
	linux-mediatek@lists.infradead.org, hsinyi@chromium.org,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/6] arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
Date: Wed, 30 Jun 2021 16:46:44 +0200	[thread overview]
Message-ID: <20210630164623.4.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid> (raw)
In-Reply-To: <20210630144646.868702-1-enric.balletbo@collabora.com>

Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

While here, also remove the undocumented and also not used
'mediatek,syscon-dsi' property.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---

 arch/arm64/boot/dts/mediatek/mt8183.dtsi  | 3 ++-
 include/dt-bindings/reset/mt8183-resets.h | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 085e2c96b5f4..2d02365633c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1286,6 +1286,7 @@ mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8183-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
 				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1400,11 +1401,11 @@ dsi0: dsi@14014000 {
 			reg = <0 0x14014000 0 0x1000>;
 			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
-			mediatek,syscon-dsi = <&mmsys 0x140>;
 			clocks = <&mmsys CLK_MM_DSI0_MM>,
 				 <&mmsys CLK_MM_DSI0_IF>,
 				 <&mipi_tx0>;
 			clock-names = "engine", "digital", "hs";
+			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
 			phys = <&mipi_tx0>;
 			phy-names = "dphy";
 		};
diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h
index a1bbd41e0d12..48c5d2de0a38 100644
--- a/include/dt-bindings/reset/mt8183-resets.h
+++ b/include/dt-bindings/reset/mt8183-resets.h
@@ -80,6 +80,9 @@
 
 #define MT8183_INFRACFG_SW_RST_NUM				128
 
+/* MMSYS resets */
+#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0			25
+
 #define MT8183_TOPRGU_MM_SW_RST					1
 #define MT8183_TOPRGU_MFG_SW_RST				2
 #define MT8183_TOPRGU_VENC_SW_RST				3
-- 
2.30.2


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: jitao.shi@mediatek.com, chunkuang.hu@kernel.org,
	matthias.bgg@gmail.com, drinkcat@chromium.org,
	eizan@chromium.org, kernel@collabora.com,
	linux-mediatek@lists.infradead.org, hsinyi@chromium.org,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/6] arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
Date: Wed, 30 Jun 2021 16:46:44 +0200	[thread overview]
Message-ID: <20210630164623.4.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid> (raw)
In-Reply-To: <20210630144646.868702-1-enric.balletbo@collabora.com>

Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

While here, also remove the undocumented and also not used
'mediatek,syscon-dsi' property.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---

 arch/arm64/boot/dts/mediatek/mt8183.dtsi  | 3 ++-
 include/dt-bindings/reset/mt8183-resets.h | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 085e2c96b5f4..2d02365633c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1286,6 +1286,7 @@ mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8183-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
 				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1400,11 +1401,11 @@ dsi0: dsi@14014000 {
 			reg = <0 0x14014000 0 0x1000>;
 			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
-			mediatek,syscon-dsi = <&mmsys 0x140>;
 			clocks = <&mmsys CLK_MM_DSI0_MM>,
 				 <&mmsys CLK_MM_DSI0_IF>,
 				 <&mipi_tx0>;
 			clock-names = "engine", "digital", "hs";
+			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
 			phys = <&mipi_tx0>;
 			phy-names = "dphy";
 		};
diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h
index a1bbd41e0d12..48c5d2de0a38 100644
--- a/include/dt-bindings/reset/mt8183-resets.h
+++ b/include/dt-bindings/reset/mt8183-resets.h
@@ -80,6 +80,9 @@
 
 #define MT8183_INFRACFG_SW_RST_NUM				128
 
+/* MMSYS resets */
+#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0			25
+
 #define MT8183_TOPRGU_MM_SW_RST					1
 #define MT8183_TOPRGU_MFG_SW_RST				2
 #define MT8183_TOPRGU_VENC_SW_RST				3
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-06-30 14:48 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-30 14:46 [PATCH 0/6] Add support to the mmsys driver to be a reset controller Enric Balletbo i Serra
2021-06-30 14:46 ` Enric Balletbo i Serra
2021-06-30 14:46 ` Enric Balletbo i Serra
2021-06-30 14:46 ` Enric Balletbo i Serra
2021-06-30 14:46 ` [PATCH 1/6] arm64: dts: mediatek: Move reset controller constants into common location Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 17:52   ` kernel test robot
2021-06-30 17:52     ` kernel test robot
2021-06-30 17:52     ` kernel test robot
2021-07-01  1:06   ` kernel test robot
2021-07-01  1:06     ` kernel test robot
2021-07-01  1:06     ` kernel test robot
2021-06-30 14:46 ` [PATCH 2/6] dt-bindings: mediatek: Add #reset-cells to mmsys system controller Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46 ` [PATCH 3/6] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0 Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 22:48   ` Chun-Kuang Hu
2021-06-30 22:48     ` Chun-Kuang Hu
2021-06-30 22:48     ` Chun-Kuang Hu
2021-07-14  8:41     ` Enric Balletbo i Serra
2021-07-14  8:41       ` Enric Balletbo i Serra
2021-07-14  8:41       ` Enric Balletbo i Serra
2021-06-30 14:46 ` Enric Balletbo i Serra [this message]
2021-06-30 14:46   ` [PATCH 4/6] arm64: dts: mt8183: " Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46 ` [PATCH 5/6] soc: mediatek: mmsys: Add reset controller support Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46 ` [PATCH 6/6] drm/mediatek: mtk_dsi: Reset the dsi0 hardware Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra
2021-06-30 14:46   ` Enric Balletbo i Serra

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