* Re: [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support
@ 2021-07-02 6:43 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-07-02 6:43 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 15453 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <20210701202427.1547543-11-matthew.d.roper@intel.com>
References: <20210701202427.1547543-11-matthew.d.roper@intel.com>
TO: Matt Roper <matthew.d.roper@intel.com>
TO: intel-gfx(a)lists.freedesktop.org
CC: Stuart Summers <stuart.summers@intel.com>
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
CC: dri-devel(a)lists.freedesktop.org
Hi Matt,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next next-20210701]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next drm/drm-next v5.13]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Matt-Roper/Begin-enabling-Xe_HP-SDV-and-DG2-platforms/20210702-042813
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
:::::: branch date: 10 hours ago
:::::: commit date: 10 hours ago
config: i386-randconfig-s001-20210630 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/321471eb113a846b2eb16a97779e7eb468d88798
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Matt-Roper/Begin-enabling-Xe_HP-SDV-and-DG2-platforms/20210702-042813
git checkout 321471eb113a846b2eb16a97779e7eb468d88798
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
drivers/gpu/drm/i915/intel_uncore.c:1620:1: sparse: sparse: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1620:1: sparse: sparse: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1620:1: sparse: sparse: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1620:1: sparse: sparse: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1621:1: sparse: sparse: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1621:1: sparse: sparse: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1621:1: sparse: sparse: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1621:1: sparse: sparse: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1622:1: sparse: sparse: context imbalance in 'fwtable_read8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1622:1: sparse: sparse: context imbalance in 'fwtable_read16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1622:1: sparse: sparse: context imbalance in 'fwtable_read32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1622:1: sparse: sparse: context imbalance in 'fwtable_read64' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1623:1: sparse: sparse: context imbalance in 'gen6_read8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1623:1: sparse: sparse: context imbalance in 'gen6_read16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1623:1: sparse: sparse: context imbalance in 'gen6_read32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1623:1: sparse: sparse: context imbalance in 'gen6_read64' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1686:1: sparse: sparse: context imbalance in 'gen6_write8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1687:1: sparse: sparse: context imbalance in 'gen6_write16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1688:1: sparse: sparse: context imbalance in 'gen6_write32' - different lock contexts for basic block
>> drivers/gpu/drm/i915/intel_uncore.c:1712:1: sparse: sparse: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block
>> drivers/gpu/drm/i915/intel_uncore.c:1712:1: sparse: sparse: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block
>> drivers/gpu/drm/i915/intel_uncore.c:1712:1: sparse: sparse: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1713:1: sparse: sparse: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1713:1: sparse: sparse: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1713:1: sparse: sparse: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1714:1: sparse: sparse: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1714:1: sparse: sparse: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1714:1: sparse: sparse: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1715:1: sparse: sparse: context imbalance in 'fwtable_write8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1715:1: sparse: sparse: context imbalance in 'fwtable_write16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1715:1: sparse: sparse: context imbalance in 'fwtable_write32' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1716:1: sparse: sparse: context imbalance in 'gen8_write8' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1716:1: sparse: sparse: context imbalance in 'gen8_write16' - different lock contexts for basic block
drivers/gpu/drm/i915/intel_uncore.c:1716:1: sparse: sparse: context imbalance in 'gen8_write32' - different lock contexts for basic block
vim +/xehp_fwtable_write8 +1712 drivers/gpu/drm/i915/intel_uncore.c
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1619
cf82d9ddd3b520 Michel Thierry 2019-09-13 1620 __gen_reg_read_funcs(gen12_fwtable);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1621 __gen_reg_read_funcs(gen11_fwtable);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 @1622 __gen_reg_read_funcs(fwtable);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 @1623 __gen_reg_read_funcs(gen6);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1624
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1625 #undef __gen_reg_read_funcs
51f67885842e36 Chris Wilson 2015-01-16 1626 #undef GEN6_READ_FOOTER
51f67885842e36 Chris Wilson 2015-01-16 1627 #undef GEN6_READ_HEADER
5d738795968dfa Ben Widawsky 2013-10-04 1628
51f67885842e36 Chris Wilson 2015-01-16 1629 #define GEN2_WRITE_HEADER \
5d738795968dfa Ben Widawsky 2013-10-04 1630 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
87b391b9518497 Daniele Ceraolo Spurio 2019-06-13 1631 assert_rpm_wakelock_held(uncore->rpm); \
907b28c56ea406 Chris Wilson 2013-07-19 1632
51f67885842e36 Chris Wilson 2015-01-16 1633 #define GEN2_WRITE_FOOTER
0d9653014f081e Ville Syrjälä 2013-12-02 1634
51f67885842e36 Chris Wilson 2015-01-16 1635 #define __gen2_write(x) \
0b27448141bbe9 Ben Widawsky 2013-10-04 1636 static void \
a2b4abfc626b13 Daniele Ceraolo Spurio 2019-03-25 1637 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
51f67885842e36 Chris Wilson 2015-01-16 1638 GEN2_WRITE_HEADER; \
6cc5ca76882521 Daniele Ceraolo Spurio 2019-03-25 1639 __raw_uncore_write##x(uncore, reg, val); \
51f67885842e36 Chris Wilson 2015-01-16 1640 GEN2_WRITE_FOOTER; \
4032ef4315475d Ben Widawsky 2013-10-04 1641 }
4032ef4315475d Ben Widawsky 2013-10-04 1642
4032ef4315475d Ben Widawsky 2013-10-04 1643 #define __gen5_write(x) \
4032ef4315475d Ben Widawsky 2013-10-04 1644 static void \
a2b4abfc626b13 Daniele Ceraolo Spurio 2019-03-25 1645 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
51f67885842e36 Chris Wilson 2015-01-16 1646 GEN2_WRITE_HEADER; \
6ebc9692a7add6 Daniele Ceraolo Spurio 2019-03-19 1647 ilk_dummy_write(uncore); \
6cc5ca76882521 Daniele Ceraolo Spurio 2019-03-25 1648 __raw_uncore_write##x(uncore, reg, val); \
51f67885842e36 Chris Wilson 2015-01-16 1649 GEN2_WRITE_FOOTER; \
4032ef4315475d Ben Widawsky 2013-10-04 1650 }
4032ef4315475d Ben Widawsky 2013-10-04 1651
51f67885842e36 Chris Wilson 2015-01-16 1652 __gen5_write(8)
51f67885842e36 Chris Wilson 2015-01-16 1653 __gen5_write(16)
51f67885842e36 Chris Wilson 2015-01-16 1654 __gen5_write(32)
51f67885842e36 Chris Wilson 2015-01-16 1655 __gen2_write(8)
51f67885842e36 Chris Wilson 2015-01-16 1656 __gen2_write(16)
51f67885842e36 Chris Wilson 2015-01-16 1657 __gen2_write(32)
51f67885842e36 Chris Wilson 2015-01-16 1658
51f67885842e36 Chris Wilson 2015-01-16 1659 #undef __gen5_write
51f67885842e36 Chris Wilson 2015-01-16 1660 #undef __gen2_write
51f67885842e36 Chris Wilson 2015-01-16 1661
51f67885842e36 Chris Wilson 2015-01-16 1662 #undef GEN2_WRITE_FOOTER
51f67885842e36 Chris Wilson 2015-01-16 1663 #undef GEN2_WRITE_HEADER
51f67885842e36 Chris Wilson 2015-01-16 1664
51f67885842e36 Chris Wilson 2015-01-16 1665 #define GEN6_WRITE_HEADER \
f0f59a00a1c9be Ville Syrjälä 2015-11-18 1666 u32 offset = i915_mmio_reg_offset(reg); \
51f67885842e36 Chris Wilson 2015-01-16 1667 unsigned long irqflags; \
51f67885842e36 Chris Wilson 2015-01-16 1668 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
87b391b9518497 Daniele Ceraolo Spurio 2019-06-13 1669 assert_rpm_wakelock_held(uncore->rpm); \
272c7e52302e91 Daniele Ceraolo Spurio 2019-03-19 1670 spin_lock_irqsave(&uncore->lock, irqflags); \
2cf7bf6f2f2067 Daniele Ceraolo Spurio 2019-03-25 1671 unclaimed_reg_debug(uncore, reg, false, true)
51f67885842e36 Chris Wilson 2015-01-16 1672
51f67885842e36 Chris Wilson 2015-01-16 1673 #define GEN6_WRITE_FOOTER \
2cf7bf6f2f2067 Daniele Ceraolo Spurio 2019-03-25 1674 unclaimed_reg_debug(uncore, reg, false, false); \
272c7e52302e91 Daniele Ceraolo Spurio 2019-03-19 1675 spin_unlock_irqrestore(&uncore->lock, irqflags)
51f67885842e36 Chris Wilson 2015-01-16 1676
4032ef4315475d Ben Widawsky 2013-10-04 1677 #define __gen6_write(x) \
4032ef4315475d Ben Widawsky 2013-10-04 1678 static void \
a2b4abfc626b13 Daniele Ceraolo Spurio 2019-03-25 1679 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
51f67885842e36 Chris Wilson 2015-01-16 1680 GEN6_WRITE_HEADER; \
a338908c11528a Mika Kuoppala 2017-04-06 1681 if (NEEDS_FORCE_WAKE(offset)) \
6ebc9692a7add6 Daniele Ceraolo Spurio 2019-03-19 1682 __gen6_gt_wait_for_fifo(uncore); \
6cc5ca76882521 Daniele Ceraolo Spurio 2019-03-25 1683 __raw_uncore_write##x(uncore, reg, val); \
51f67885842e36 Chris Wilson 2015-01-16 1684 GEN6_WRITE_FOOTER; \
4032ef4315475d Ben Widawsky 2013-10-04 1685 }
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1686 __gen6_write(8)
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1687 __gen6_write(16)
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1688 __gen6_write(32)
4032ef4315475d Ben Widawsky 2013-10-04 1689
ccfceda22cc018 Daniele Ceraolo Spurio 2017-02-03 1690 #define __gen_write(func, x) \
ab2aa47e4b2d2a Ben Widawsky 2013-11-02 1691 static void \
a2b4abfc626b13 Daniele Ceraolo Spurio 2019-03-25 1692 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
6863b76c629549 Tvrtko Ursulin 2016-04-12 1693 enum forcewake_domains fw_engine; \
51f67885842e36 Chris Wilson 2015-01-16 1694 GEN6_WRITE_HEADER; \
272c7e52302e91 Daniele Ceraolo Spurio 2019-03-19 1695 fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
6a42d0f4b32d9f Ville Syrjälä 2015-10-22 1696 if (fw_engine) \
272c7e52302e91 Daniele Ceraolo Spurio 2019-03-19 1697 __force_wake_auto(uncore, fw_engine); \
6cc5ca76882521 Daniele Ceraolo Spurio 2019-03-25 1698 __raw_uncore_write##x(uncore, reg, val); \
51f67885842e36 Chris Wilson 2015-01-16 1699 GEN6_WRITE_FOOTER; \
1938e59ab719f3 Deepak S 2014-05-23 1700 }
4032ef4315475d Ben Widawsky 2013-10-04 1701
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1702 #define __gen_reg_write_funcs(func) \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1703 static enum forcewake_domains \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1704 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1705 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1706 } \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1707 \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1708 __gen_write(func, 8) \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1709 __gen_write(func, 16) \
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1710 __gen_write(func, 32)
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1711
321471eb113a84 Matt Roper 2021-07-01 @1712 __gen_reg_write_funcs(xehp_fwtable);
cf82d9ddd3b520 Michel Thierry 2019-09-13 1713 __gen_reg_write_funcs(gen12_fwtable);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1714 __gen_reg_write_funcs(gen11_fwtable);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1715 __gen_reg_write_funcs(fwtable);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1716 __gen_reg_write_funcs(gen8);
ccb2aceaaa5f92 Daniele Ceraolo Spurio 2019-06-19 1717
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
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^ permalink raw reply [flat|nested] 2+ messages in thread* [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms
@ 2021-07-01 20:23 Matt Roper
2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper
0 siblings, 1 reply; 2+ messages in thread
From: Matt Roper @ 2021-07-01 20:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, James Ausmus, dri-devel, Rodrigo Vivi
This series provides some of the initial enablement patches for two
upcoming discrete GPUs:
* XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP
* DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP
Both platforms will need additional enablement patches beyond what's
present in this series before they're truly usable, including various
LMEM and GuC work that's already happening separately. The new
features/functionality that these platforms bring (such as multi-tile
support, dedicated compute engines, etc.) may be referenced in passing
in some of these patches but will be fully enabled in future series.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Akeem G Abodunrin (1):
drm/i915/dg2: Add new LRI reg offsets
Animesh Manna (1):
drm/i915/dg2: Update to bigjoiner path
Ankit Nautiyal (1):
drm/i915/dg2: Configure PCON in DP pre-enable path
Anusha Srivatsa (2):
drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP
enable
drm/i915/display/dsc: Set BPP in the kernel
Daniele Ceraolo Spurio (1):
drm/i915/xehp: handle new steering options
Gwan-gyeong Mun (1):
drm/i915/dg2: Update lane disable power state during PSR
John Harrison (4):
drm/i915/selftests: Allow for larger engine counts
drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
drm/i915/xehp: Extra media engines - Part 2 (interrupts)
drm/i915/xehp: Extra media engines - Part 3 (reset)
José Roberto de Souza (1):
drm/i915/dg2: Add DG2 to the PSR2 defeature list
Lucas De Marchi (5):
drm/i915: Add "release id" version
drm/i915: Add XE_HP initial definitions
drm/i915/xehpsdv: add initial XeHP SDV definitions
drm/i915/xehpsdv: Define MOCS table for XeHP SDV
drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
Matt Roper (29):
drm/i915/xehp: Xe_HP forcewake support
drm/i915/xehp: Define multicast register ranges
drm/i915/xehp: Loop over all gslices for INSTDONE processing
drm/i915/xehpsdv: Add maximum sseu limits
drm/i915/xehpsdv: Define steering tables
drm/i915/xehpsdv: Read correct RP_STATE_CAP register
drm/i915/dg2: add DG2 platform info
drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
drm/i915/dg2: Add forcewake table
drm/i915/dg2: Update LNCF steering ranges
drm/i915/dg2: Add SQIDI steering
drm/i915/dg2: Maintain backward-compatible nested batch behavior
drm/i915/dg2: Report INSTDONE_GEOM values in error state
drm/i915/dg2: Define MOCS table for DG2
drm/i915/dg2: Add fake PCH
drm/i915/dg2: Add cdclk table and reference clock
drm/i915/dg2: Skip shared DPLL handling
drm/i915/dg2: Don't wait for AUX power well enable ACKs
drm/i915/dg2: Setup display outputs
drm/i915/dg2: Add dbuf programming
drm/i915/dg2: Don't program BW_BUDDY registers
drm/i915/dg2: Don't read DRAM info
drm/i915/dg2: DG2 has fixed memory bandwidth
drm/i915/dg2: Add MPLLB programming for SNPS PHY
drm/i915/dg2: Add MPLLB programming for HDMI
drm/i915/dg2: Add vswing programming for SNPS phys
drm/i915/dg2: Update modeset sequences
drm/i915/dg2: Classify DG2 PHY types
drm/i915/dg2: Wait for SNPS PHY calibration during display init
Matthew Auld (1):
drm/i915/xehp: Changes to ss/eu definitions
Paulo Zanoni (1):
drm/i915: Fork DG1 interrupt handler
Prathap Kumar Valsan (1):
drm/i915/xehp: New engine context offsets
Stuart Summers (2):
drm/i915/xehp: Handle new device context ID format
drm/i915/xehpsdv: Add compute DSS type
Tvrtko Ursulin (1):
drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
Venkata Sandeep Dhanalakota (1):
drm/i915/gen12: Use fuse info to enable SFC
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_bw.c | 24 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 165 +++-
drivers/gpu/drm/i915/display/intel_display.c | 94 +-
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_debugfs.c | 103 ++-
.../drm/i915/display/intel_display_power.c | 25 +
.../drm/i915/display/intel_display_power.h | 10 +
.../drm/i915/display/intel_display_types.h | 18 +-
drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 12 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 11 +
drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 862 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_snps_phy.h | 35 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 144 ++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 +-
.../drm/i915/gt/intel_execlists_submission.c | 78 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 66 +-
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 156 +++-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 66 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +
drivers/gpu/drm/i915/gt/intel_rps.c | 19 +-
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 116 ++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 20 +-
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 175 +++-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 10 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 32 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 48 +-
drivers/gpu/drm/i915/i915_getparam.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 36 +-
drivers/gpu/drm/i915/i915_irq.c | 141 ++-
drivers/gpu/drm/i915/i915_pci.c | 63 +-
drivers/gpu/drm/i915/i915_perf.c | 29 +-
drivers/gpu/drm/i915/i915_reg.h | 109 ++-
drivers/gpu/drm/i915/intel_device_info.c | 4 +
drivers/gpu/drm/i915/intel_device_info.h | 10 +-
drivers/gpu/drm/i915/intel_dram.c | 6 +-
drivers/gpu/drm/i915/intel_pch.c | 3 +
drivers/gpu/drm/i915/intel_pch.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 120 ++-
drivers/gpu/drm/i915/intel_step.c | 20 +-
drivers/gpu/drm/i915/intel_step.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 367 ++++++--
drivers/gpu/drm/i915/intel_uncore.h | 14 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
include/uapi/drm/i915_drm.h | 3 -
59 files changed, 3085 insertions(+), 289 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.h
--
2.25.4
^ permalink raw reply [flat|nested] 2+ messages in thread* [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support 2021-07-01 20:23 [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper @ 2021-07-01 20:23 ` Matt Roper 0 siblings, 0 replies; 2+ messages in thread From: Matt Roper @ 2021-07-01 20:23 UTC (permalink / raw) To: intel-gfx; +Cc: Stuart Summers, Daniele Ceraolo Spurio, dri-devel Implement Xe_HP forcewake handling. While we're at it, let's reorder to the forcewake assignment if/else ladder to match our usual driver conventions. Co-authored-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- .../drm/i915/gt/intel_execlists_submission.c | 4 + drivers/gpu/drm/i915/intel_uncore.c | 336 +++++++++++++++--- drivers/gpu/drm/i915/intel_uncore.h | 14 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + 4 files changed, 302 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index cdb2126a159a..15ba0d83151a 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -3318,6 +3318,10 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); execlists->ctrl_reg = uncore->regs + i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); + + engine->fw_domain = intel_uncore_forcewake_for_reg(engine->uncore, + RING_EXECLIST_CONTROL(engine->mmio_base), + FW_REG_WRITE); } else { execlists->submit_reg = uncore->regs + i915_mmio_reg_offset(RING_ELSP(base)); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index d067524f9162..676b0052f01e 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -24,6 +24,8 @@ #include <linux/pm_runtime.h> #include <asm/iosf_mbi.h> +#include "gt/intel_lrc_reg.h" /* for shadow reg list */ + #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" @@ -68,8 +70,14 @@ static const char * const forcewake_domain_names[] = { "vdbox1", "vdbox2", "vdbox3", + "vdbox4", + "vdbox5", + "vdbox6", + "vdbox7", "vebox0", "vebox1", + "vebox2", + "vebox3", }; const char * @@ -952,30 +960,80 @@ static const i915_reg_t gen8_shadowed_regs[] = { }; static const i915_reg_t gen11_shadowed_regs[] = { - RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ - GEN6_RPNSWREQ, /* 0xA008 */ - GEN6_RC_VIDEO_FREQ, /* 0xA00C */ - RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ - RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ - RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ - RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ - RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ - RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ - RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ + RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ + RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */ + GEN6_RPNSWREQ, /* 0xA008 */ + GEN6_RC_VIDEO_FREQ, /* 0xA00C */ + RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ + RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */ + RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */ + RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */ + RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ + RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */ + RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */ + RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */ + RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ + RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */ /* TODO: Other registers are not yet used */ }; static const i915_reg_t gen12_shadowed_regs[] = { - RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ - GEN6_RPNSWREQ, /* 0xA008 */ - GEN6_RC_VIDEO_FREQ, /* 0xA00C */ - RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ - RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ - RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ - RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ - RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ - RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ - RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ + RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ + RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */ + GEN6_RPNSWREQ, /* 0xA008 */ + GEN6_RC_VIDEO_FREQ, /* 0xA00C */ + RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ + RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */ + RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */ + RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */ + RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ + RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */ + RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */ + RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */ + RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ + RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */ + /* TODO: Other registers are not yet used */ +}; + +static const i915_reg_t xehp_shadowed_regs[] = { + RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ + RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */ + GEN6_RPNSWREQ, /* 0xA008 */ + GEN6_RC_VIDEO_FREQ, /* 0xA00C */ + RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ + RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */ + RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */ + RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */ + RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ + RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */ + RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */ + RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ + RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */ + RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ + RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */ + RING_TAIL(XEHP_BSD5_RING_BASE), /* 0x1E0000 (base) */ + RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE), /* 0x1E0550 */ + RING_TAIL(XEHP_BSD6_RING_BASE), /* 0x1E4000 (base) */ + RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE), /* 0x1E4550 */ + RING_TAIL(XEHP_VEBOX3_RING_BASE), /* 0x1E8000 (base) */ + RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE), /* 0x1E8550 */ + RING_TAIL(XEHP_BSD7_RING_BASE), /* 0x1F0000 (base) */ + RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE), /* 0x1F0550 */ + RING_TAIL(XEHP_BSD8_RING_BASE), /* 0x1F4000 (base) */ + RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE), /* 0x1F4550 */ + RING_TAIL(XEHP_VEBOX4_RING_BASE), /* 0x1F8000 (base) */ + RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE), /* 0x1F8550 */ /* TODO: Other registers are not yet used */ }; @@ -991,17 +1049,18 @@ static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) return 0; } -#define __is_genX_shadowed(x) \ -static bool is_gen##x##_shadowed(u32 offset) \ +#define __is_X_shadowed(x) \ +static bool is_##x##_shadowed(u32 offset) \ { \ - const i915_reg_t *regs = gen##x##_shadowed_regs; \ - return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \ + const i915_reg_t *regs = x##_shadowed_regs; \ + return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \ mmio_reg_cmp); \ } -__is_genX_shadowed(8) -__is_genX_shadowed(11) -__is_genX_shadowed(12) +__is_X_shadowed(gen8) +__is_X_shadowed(gen11) +__is_X_shadowed(gen12) +__is_X_shadowed(xehp) static enum forcewake_domains gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) @@ -1065,6 +1124,15 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { __fwd; \ }) +#define __xehp_fwtable_reg_write_fw_domains(uncore, offset) \ +({ \ + enum forcewake_domains __fwd = 0; \ + const u32 __offset = (offset); \ + if (!is_xehp_shadowed(__offset)) \ + __fwd = find_fw_domain(uncore, __offset); \ + __fwd; \ +}) + /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ static const struct intel_forcewake_range __gen9_fw_ranges[] = { GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), @@ -1249,6 +1317,145 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = { 0x1d3f00 - 0x1d3fff: VD2 */ }; +/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ +static const struct intel_forcewake_range __xehp_fw_ranges[] = { + GEN_FW_RANGE(0x0, 0x1fff, 0), /* + 0x0 - 0xaff: reserved + 0xb00 - 0x1fff: always on */ + GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), + GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* + 0x4b00 - 0x4fff: reserved + 0x5000 - 0x51ff: always on */ + GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), + GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x8160, 0x81ff, 0), /* + 0x8160 - 0x817f: reserved + 0x8180 - 0x81ff: always on */ + GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), + GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* + 0x8500 - 0x87ff: gt + 0x8800 - 0x8fff: reserved + 0x9000 - 0x947f: gt + 0x9480 - 0x94cf: reserved */ + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x9560, 0x97ff, 0), /* + 0x9560 - 0x95ff: always on + 0x9600 - 0x97ff: reserved */ + GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* + 0x9800 - 0xb4ff: gt + 0xb500 - 0xbfff: reserved + 0xc000 - 0xcfff: gt */ + GEN_FW_RANGE(0xd000, 0xd7ff, 0), + GEN_FW_RANGE(0xd800, 0xdbff, FORCEWAKE_GT), + GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* + 0xdd00 - 0xddff: gt + 0xde00 - 0xde7f: reserved */ + GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* + 0xde80 - 0xdfff: render + 0xe000 - 0xe0ff: reserved + 0xe100 - 0xe8ff: render */ + GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* + 0xe900 - 0xe9ff: gt + 0xea00 - 0xefff: reserved + 0xf000 - 0xffff: gt */ + GEN_FW_RANGE(0x10000, 0x13fff, 0), /* + 0x10000 - 0x11fff: reserved + 0x12000 - 0x127ff: always on + 0x12800 - 0x13fff: reserved */ + GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), + GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), + GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* + 0x14800 - 0x14fff: render + 0x15000 - 0x16dff: reserved + 0x16e00 - 0x1ffff: render */ + GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* + 0x20000 - 0x20fff: VD0 + 0x21000 - 0x21fff: reserved */ + GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), + GEN_FW_RANGE(0x24000, 0x2417f, 0), /* + 0x24000 - 0x2407f: always on + 0x24080 - 0x2417f: reserved */ + GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* + 0x24180 - 0x241ff: gt + 0x24200 - 0x249ff: reserved */ + GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* + 0x24a00 - 0x24a7f: render + 0x24a80 - 0x251ff: reserved */ + GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* + 0x25200 - 0x252ff: gt + 0x25300 - 0x25fff: reserved */ + GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* + 0x26000 - 0x27fff: render + 0x28000 - 0x29fff: reserved + 0x2a000 - 0x2ffff: undocumented */ + GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), + GEN_FW_RANGE(0x40000, 0x1bffff, 0), + GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* + 0x1c0000 - 0x1c2bff: VD0 + 0x1c2c00 - 0x1c2cff: reserved + 0x1c2d00 - 0x1c2dff: VD0 + 0x1c2e00 - 0x1c3eff: reserved + 0x1c3f00 - 0x1c3fff: VD0 */ + GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* + 0x1c4000 - 0x1c6bff: VD1 + 0x1c6c00 - 0x1c6cff: reserved + 0x1c6d00 - 0x1c6dff: VD1 + 0x1c6e00 - 0x1c7fff: reserved */ + GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* + 0x1c8000 - 0x1ca0ff: VE0 + 0x1ca100 - 0x1cbfff: reserved */ + GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), + GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), + GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* + 0x1d0000 - 0x1d2bff: VD2 + 0x1d2c00 - 0x1d2cff: reserved + 0x1d2d00 - 0x1d2dff: VD2 + 0x1d2e00 - 0x1d3eff: reserved + 0x1d3f00 - 0x1d3fff: VD2 */ + GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* + 0x1d4000 - 0x1d6bff: VD3 + 0x1d6c00 - 0x1d6cff: reserved + 0x1d6d00 - 0x1d6dff: VD3 + 0x1d6e00 - 0x1d7fff: reserved */ + GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* + 0x1d8000 - 0x1da0ff: VE1 + 0x1da100 - 0x1dffff: reserved */ + GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* + 0x1e0000 - 0x1e2bff: VD4 + 0x1e2c00 - 0x1e2cff: reserved + 0x1e2d00 - 0x1e2dff: VD4 + 0x1e2e00 - 0x1e3eff: reserved + 0x1e3f00 - 0x1e3fff: VD4 */ + GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* + 0x1e4000 - 0x1e6bff: VD5 + 0x1e6c00 - 0x1e6cff: reserved + 0x1e6d00 - 0x1e6dff: VD5 + 0x1e6e00 - 0x1e7fff: reserved */ + GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* + 0x1e8000 - 0x1ea0ff: VE2 + 0x1ea100 - 0x1effff: reserved */ + GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* + 0x1f0000 - 0x1f2bff: VD6 + 0x1f2c00 - 0x1f2cff: reserved + 0x1f2d00 - 0x1f2dff: VD6 + 0x1f2e00 - 0x1f3eff: reserved + 0x1f3f00 - 0x1f3fff: VD6 */ + GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* + 0x1f4000 - 0x1f6bff: VD7 + 0x1f6c00 - 0x1f6cff: reserved + 0x1f6d00 - 0x1f6dff: VD7 + 0x1f6e00 - 0x1f7fff: reserved */ + GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3), +}; + static void ilk_dummy_write(struct intel_uncore *uncore) { @@ -1502,6 +1709,7 @@ __gen_write(func, 8) \ __gen_write(func, 16) \ __gen_write(func, 32) +__gen_reg_write_funcs(xehp_fwtable); __gen_reg_write_funcs(gen12_fwtable); __gen_reg_write_funcs(gen11_fwtable); __gen_reg_write_funcs(fwtable); @@ -1582,8 +1790,14 @@ static int __fw_domain_init(struct intel_uncore *uncore, BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7)); BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3)); d->mask = BIT(domain_id); @@ -1870,36 +2084,36 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) return ret; forcewake_early_sanitize(uncore, 0); - if (IS_GRAPHICS_VER(i915, 6, 7)) { - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); - - if (IS_VALLEYVIEW(i915)) { - ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); - ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); - } else { - ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); - } - } else if (GRAPHICS_VER(i915) == 8) { - if (IS_CHERRYVIEW(i915)) { - ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); - ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); - } else { - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); - ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); - } - } else if (IS_GRAPHICS_VER(i915, 9, 10)) { - ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); - ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); - } else if (GRAPHICS_VER(i915) == 11) { - ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges); + ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable); ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); - } else { + } else if (GRAPHICS_VER(i915) >= 12) { ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable); + } else if (GRAPHICS_VER(i915) == 11) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); + ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); + } else if (IS_GRAPHICS_VER(i915, 9, 10)) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); + ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); + } else if (IS_CHERRYVIEW(i915)) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); + ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); + } else if (GRAPHICS_VER(i915) == 8) { + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); + ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); + } else if (IS_VALLEYVIEW(i915)) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); + } else if (IS_GRAPHICS_VER(i915, 6, 7)) { + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); + ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); } uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; @@ -1988,6 +2202,22 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, if (HAS_ENGINE(gt, _VCS(i))) continue; + /* + * Starting with XeHP, the power well for an even-numbered + * VDBOX is also used for shared units within the + * media slice such as SFC. So even if the engine + * itself is fused off, we still need to initialize + * the forcewake domain if any of the other engines + * in the same media slice are present. + */ + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) { + if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1))) + continue; + + if (HAS_ENGINE(gt, _VECS(i / 2))) + continue; + } + if (fw_domains & BIT(domain_id)) fw_domain_fini(uncore, domain_id); } diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index a18bdb57af7b..3c0b0a8b5250 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -52,8 +52,14 @@ enum forcewake_domain_id { FW_DOMAIN_ID_MEDIA_VDBOX1, FW_DOMAIN_ID_MEDIA_VDBOX2, FW_DOMAIN_ID_MEDIA_VDBOX3, + FW_DOMAIN_ID_MEDIA_VDBOX4, + FW_DOMAIN_ID_MEDIA_VDBOX5, + FW_DOMAIN_ID_MEDIA_VDBOX6, + FW_DOMAIN_ID_MEDIA_VDBOX7, FW_DOMAIN_ID_MEDIA_VEBOX0, FW_DOMAIN_ID_MEDIA_VEBOX1, + FW_DOMAIN_ID_MEDIA_VEBOX2, + FW_DOMAIN_ID_MEDIA_VEBOX3, FW_DOMAIN_ID_COUNT }; @@ -66,10 +72,16 @@ enum forcewake_domains { FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2), FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3), + FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4), + FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5), + FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6), + FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7), FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0), FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1), + FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2), + FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3), - FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1 + FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1, }; struct intel_uncore_funcs { diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c index 8ef9e6a4ad05..720b60853f8b 100644 --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c @@ -68,6 +68,7 @@ static int intel_shadow_table_check(void) { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) }, { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) }, { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) }, + { xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) }, }; const i915_reg_t *reg; unsigned int i, j; @@ -103,6 +104,7 @@ int intel_uncore_mock_selftests(void) { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true }, { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true }, { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true }, + { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true }, }; int err, i; -- 2.25.4 ^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-07-02 6:43 UTC | newest] Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-07-02 6:43 [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2021-07-01 20:23 [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper 2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper
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