From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, "Jason Ekstrand" <jason@jlekstrand.net>, "Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>, "Jordan Justen" <jordan.l.justen@intel.com>, dri-devel@lists.freedesktop.org, "Kenneth Graunke" <kenneth@whitecape.org>, "Daniel Vetter" <daniel.vetter@ffwll.ch> Subject: [PATCH v3 5/5] drm/i915/uapi: reject set_domain for discrete Date: Mon, 5 Jul 2021 14:53:10 +0100 [thread overview] Message-ID: <20210705135310.1502437-5-matthew.auld@intel.com> (raw) In-Reply-To: <20210705135310.1502437-1-matthew.auld@intel.com> The CPU domain should be static for discrete, and on DG1 we don't need any flushing since everything is already coherent, so really all this does is an object wait, for which we have an ioctl. Longer term the desired caching should be an immutable creation time property for the BO, which can be set with something like gem_create_ext. One other user is iris + userptr, which uses the set_domain to probe all the pages to check if the GUP succeeds, however keeping the set_domain around just for that seems rather scuffed. We could equally just submit a dummy batch, which should hopefully be good enough, otherwise adding a new creation time flag for userptr might be an option. Although longer term we will also have vm_bind, which should also be a nice fit for this, so adding a whole new flag is likely overkill. v2: add some more kernel doc, also add the implicit rules with caching Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ include/uapi/drm/i915_drm.h | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 43004bef55cb..b684a62bf3b0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -490,6 +490,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, u32 write_domain = args->write_domain; int err; + if (IS_DGFX(to_i915(dev))) + return -ENODEV; + /* Only handle setting domains to types used by the CPU. */ if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 6f94e5e7569a..fd1a9878730c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -900,6 +900,24 @@ struct drm_i915_gem_mmap_offset { * * All other domains are rejected. * + * Note that for discrete, starting from DG1, this is no longer supported, and + * is instead rejected. On such platforms the CPU domain is effectively static, + * where we also only support a single &drm_i915_gem_mmap_offset cache mode, + * which can't be set explicitly and instead depends on the object placements, + * as per the below. + * + * Implicit caching rules, starting from DG1: + * + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and + * mapped as write-combined only. + * + * - Everything else is always allocated and mapped as write-back, with the + * guarantee that everything is also coherent with the GPU. + * + * Note that this is likely to change in the future again, where we might need + * more flexibility on future devices, so making this all explicit as part of a + * new &drm_i915_gem_create_ext extension is probable. */ struct drm_i915_gem_set_domain { /** @handle: Handle for the object. */ -- 2.26.3
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, dri-devel@lists.freedesktop.org, "Kenneth Graunke" <kenneth@whitecape.org>, "Daniel Vetter" <daniel.vetter@ffwll.ch> Subject: [Intel-gfx] [PATCH v3 5/5] drm/i915/uapi: reject set_domain for discrete Date: Mon, 5 Jul 2021 14:53:10 +0100 [thread overview] Message-ID: <20210705135310.1502437-5-matthew.auld@intel.com> (raw) In-Reply-To: <20210705135310.1502437-1-matthew.auld@intel.com> The CPU domain should be static for discrete, and on DG1 we don't need any flushing since everything is already coherent, so really all this does is an object wait, for which we have an ioctl. Longer term the desired caching should be an immutable creation time property for the BO, which can be set with something like gem_create_ext. One other user is iris + userptr, which uses the set_domain to probe all the pages to check if the GUP succeeds, however keeping the set_domain around just for that seems rather scuffed. We could equally just submit a dummy batch, which should hopefully be good enough, otherwise adding a new creation time flag for userptr might be an option. Although longer term we will also have vm_bind, which should also be a nice fit for this, so adding a whole new flag is likely overkill. v2: add some more kernel doc, also add the implicit rules with caching Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ include/uapi/drm/i915_drm.h | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 43004bef55cb..b684a62bf3b0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -490,6 +490,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, u32 write_domain = args->write_domain; int err; + if (IS_DGFX(to_i915(dev))) + return -ENODEV; + /* Only handle setting domains to types used by the CPU. */ if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 6f94e5e7569a..fd1a9878730c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -900,6 +900,24 @@ struct drm_i915_gem_mmap_offset { * * All other domains are rejected. * + * Note that for discrete, starting from DG1, this is no longer supported, and + * is instead rejected. On such platforms the CPU domain is effectively static, + * where we also only support a single &drm_i915_gem_mmap_offset cache mode, + * which can't be set explicitly and instead depends on the object placements, + * as per the below. + * + * Implicit caching rules, starting from DG1: + * + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and + * mapped as write-combined only. + * + * - Everything else is always allocated and mapped as write-back, with the + * guarantee that everything is also coherent with the GPU. + * + * Note that this is likely to change in the future again, where we might need + * more flexibility on future devices, so making this all explicit as part of a + * new &drm_i915_gem_create_ext extension is probable. */ struct drm_i915_gem_set_domain { /** @handle: Handle for the object. */ -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-05 13:53 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-05 13:53 [PATCH v3 1/5] drm/i915: use consistent CPU mappings for pin_map users Matthew Auld 2021-07-05 13:53 ` [Intel-gfx] " Matthew Auld 2021-07-05 13:53 ` [PATCH v3 2/5] drm/i915/uapi: convert drm_i915_gem_caching to kernel doc Matthew Auld 2021-07-05 13:53 ` [Intel-gfx] " Matthew Auld 2021-07-07 0:29 ` Ramalingam C 2021-07-07 0:29 ` [Intel-gfx] " Ramalingam C 2021-07-05 13:53 ` [PATCH v3 3/5] drm/i915/uapi: reject caching ioctls for discrete Matthew Auld 2021-07-05 13:53 ` [Intel-gfx] " Matthew Auld 2021-07-07 0:38 ` Ramalingam C 2021-07-07 0:38 ` [Intel-gfx] " Ramalingam C 2021-07-13 18:03 ` Kenneth Graunke 2021-07-13 18:03 ` [Intel-gfx] " Kenneth Graunke 2021-07-05 13:53 ` [PATCH v3 4/5] drm/i915/uapi: convert drm_i915_gem_set_domain to kernel doc Matthew Auld 2021-07-05 13:53 ` [Intel-gfx] " Matthew Auld 2021-07-07 0:41 ` Ramalingam C 2021-07-07 0:41 ` [Intel-gfx] " Ramalingam C 2021-07-05 13:53 ` Matthew Auld [this message] 2021-07-05 13:53 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/uapi: reject set_domain for discrete Matthew Auld 2021-07-07 0:49 ` Ramalingam C 2021-07-07 0:49 ` [Intel-gfx] " Ramalingam C 2021-07-05 15:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915: use consistent CPU mappings for pin_map users Patchwork 2021-07-05 15:46 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-07-07 0:12 ` [PATCH v3 1/5] " Ramalingam C 2021-07-07 0:12 ` [Intel-gfx] " Ramalingam C 2021-07-07 11:46 ` Daniel Vetter 2021-07-07 11:46 ` [Intel-gfx] " Daniel Vetter
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