* [PATCH] arm64: tegra: Enable SMMU support for PCIe on Tegra194
@ 2021-07-13 4:44 Vidya Sagar
2021-07-13 9:55 ` Jon Hunter
2021-07-13 11:35 ` [PATCH V2] " Vidya Sagar
0 siblings, 2 replies; 4+ messages in thread
From: Vidya Sagar @ 2021-07-13 4:44 UTC (permalink / raw)
To: robh+dt, thierry.reding, jonathanh
Cc: devicetree, linux-tegra, linux-kernel, kthota, mmaddireddy,
vidyas, sagar.tv
As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on
Tegra194"), SMMU support is enabled system-wide on Tegra194. However,
there was a bit of overlap between the SMMU enablement and the PCIe
support addition, so the PCIe device tree nodes are missing the iommus
and interconnects properties. This in turn leads to SMMU faults for
these devices, since by default the ARM SMMU will fault.
Add the iommus and interconnects properties to all the PCIe device
tree nodes to restore their functionality.
Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 60 +++++++++++++++++++++---
1 file changed, 54 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 076d5efc4c3d..b55522aacfb0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1840,7 +1840,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE1>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14120000 {
@@ -1890,7 +1894,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE2>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14140000 {
@@ -1940,7 +1948,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE3>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14160000 {
@@ -1990,7 +2002,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE4>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14180000 {
@@ -2040,7 +2056,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE0>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@141a0000 {
@@ -2094,7 +2114,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE5>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie_ep@14160000 {
@@ -2127,6 +2151,14 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE4>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie_ep@14180000 {
@@ -2159,6 +2191,14 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE0>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie_ep@141a0000 {
@@ -2194,6 +2234,14 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
+ interconnect-names = "dma-mem", "dma-mem";
+ iommus = <&smmu TEGRA194_SID_PCIE5>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
sram@40000000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: tegra: Enable SMMU support for PCIe on Tegra194
2021-07-13 4:44 [PATCH] arm64: tegra: Enable SMMU support for PCIe on Tegra194 Vidya Sagar
@ 2021-07-13 9:55 ` Jon Hunter
2021-07-13 11:35 ` [PATCH V2] " Vidya Sagar
1 sibling, 0 replies; 4+ messages in thread
From: Jon Hunter @ 2021-07-13 9:55 UTC (permalink / raw)
To: Vidya Sagar, robh+dt, thierry.reding
Cc: devicetree, linux-tegra, linux-kernel, kthota, mmaddireddy, sagar.tv
On 13/07/2021 05:44, Vidya Sagar wrote:
> As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on
> Tegra194"), SMMU support is enabled system-wide on Tegra194. However,
> there was a bit of overlap between the SMMU enablement and the PCIe
> support addition, so the PCIe device tree nodes are missing the iommus
> and interconnects properties. This in turn leads to SMMU faults for
> these devices, since by default the ARM SMMU will fault.
>
> Add the iommus and interconnects properties to all the PCIe device
> tree nodes to restore their functionality.
>
> Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194")
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 60 +++++++++++++++++++++---
> 1 file changed, 54 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 076d5efc4c3d..b55522aacfb0 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1840,7 +1840,11 @@
>
> interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
> <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
> - interconnect-names = "read", "write";
> + interconnect-names = "dma-mem", "dma-mem";
Thierry indicated that the convention we have been using is that only
the entry is called 'dma-mem'. So could be good to update this to be
consistent with the other interconnect-names entries. Otherwise ...
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH V2] arm64: tegra: Enable SMMU support for PCIe on Tegra194
2021-07-13 4:44 [PATCH] arm64: tegra: Enable SMMU support for PCIe on Tegra194 Vidya Sagar
2021-07-13 9:55 ` Jon Hunter
@ 2021-07-13 11:35 ` Vidya Sagar
2021-07-14 7:32 ` Thierry Reding
1 sibling, 1 reply; 4+ messages in thread
From: Vidya Sagar @ 2021-07-13 11:35 UTC (permalink / raw)
To: robh+dt, thierry.reding, jonathanh
Cc: devicetree, linux-tegra, linux-kernel, kthota, mmaddireddy,
vidyas, sagar.tv
As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on
Tegra194"), SMMU support is enabled system-wide on Tegra194. However,
there was a bit of overlap between the SMMU enablement and the PCIe
support addition, so the PCIe device tree nodes are missing the iommus
and interconnects properties. This in turn leads to SMMU faults for
these devices, since by default the ARM SMMU will fault.
Add the iommus and interconnects properties to all the PCIe device
tree nodes to restore their functionality.
Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
V2:
* Changed interconnect-names from "dma-mem", "dma-mem" -> "dma-mem", "write"
* Added Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 60 +++++++++++++++++++++---
1 file changed, 54 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 076d5efc4c3d..5ba7a4519b95 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1840,7 +1840,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE1>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14120000 {
@@ -1890,7 +1894,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE2>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14140000 {
@@ -1940,7 +1948,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE3>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14160000 {
@@ -1990,7 +2002,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE4>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@14180000 {
@@ -2040,7 +2056,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE0>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie@141a0000 {
@@ -2094,7 +2114,11 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
- interconnect-names = "read", "write";
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE5>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie_ep@14160000 {
@@ -2127,6 +2151,14 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE4>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie_ep@14180000 {
@@ -2159,6 +2191,14 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE0>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
pcie_ep@141a0000 {
@@ -2194,6 +2234,14 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_PCIE5>;
+ iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
};
sram@40000000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH V2] arm64: tegra: Enable SMMU support for PCIe on Tegra194
2021-07-13 11:35 ` [PATCH V2] " Vidya Sagar
@ 2021-07-14 7:32 ` Thierry Reding
0 siblings, 0 replies; 4+ messages in thread
From: Thierry Reding @ 2021-07-14 7:32 UTC (permalink / raw)
To: Vidya Sagar
Cc: robh+dt, jonathanh, devicetree, linux-tegra, linux-kernel,
kthota, mmaddireddy, sagar.tv
[-- Attachment #1: Type: text/plain, Size: 1095 bytes --]
On Tue, Jul 13, 2021 at 05:05:46PM +0530, Vidya Sagar wrote:
> As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on
> Tegra194"), SMMU support is enabled system-wide on Tegra194. However,
> there was a bit of overlap between the SMMU enablement and the PCIe
> support addition, so the PCIe device tree nodes are missing the iommus
> and interconnects properties. This in turn leads to SMMU faults for
> these devices, since by default the ARM SMMU will fault.
>
> Add the iommus and interconnects properties to all the PCIe device
> tree nodes to restore their functionality.
>
> Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194")
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> V2:
> * Changed interconnect-names from "dma-mem", "dma-mem" -> "dma-mem", "write"
> * Added Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 60 +++++++++++++++++++++---
> 1 file changed, 54 insertions(+), 6 deletions(-)
Applied, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
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Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-13 4:44 [PATCH] arm64: tegra: Enable SMMU support for PCIe on Tegra194 Vidya Sagar
2021-07-13 9:55 ` Jon Hunter
2021-07-13 11:35 ` [PATCH V2] " Vidya Sagar
2021-07-14 7:32 ` Thierry Reding
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