From: Eduardo Habkost <ehabkost@redhat.com> To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com>, kvm@vger.kernel.org, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, "Michael S. Tsirkin" <mst@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, Michael Roth <michael.roth@amd.com>, "Dr. David Alan Gilbert" <dgilbert@redhat.com>, Igor Mammedov <imammedo@redhat.com>, zhenwei pi <pizhenwei@bytedance.com> Subject: [PULL 08/11] target/i386: suppress CPUID leaves not defined by the CPU vendor Date: Tue, 13 Jul 2021 12:09:54 -0400 [thread overview] Message-ID: <20210713160957.3269017-9-ehabkost@redhat.com> (raw) In-Reply-To: <20210713160957.3269017-1-ehabkost@redhat.com> From: Michael Roth <michael.roth@amd.com> Currently all built-in CPUs report cache information via CPUID leaves 2 and 4, but these have never been defined for AMD. In the case of SEV-SNP this can cause issues with CPUID enforcement. Address this by allowing CPU types to suppress these via a new "x-vendor-cpuid-only" CPU property, which is true by default, but switched off for older machine types to maintain compatibility. Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: zhenwei pi <pizhenwei@bytedance.com> Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Message-Id: <20210708003623.18665-1-michael.roth@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 3 +++ hw/i386/pc.c | 1 + target/i386/cpu.c | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8f3747dd285..950a991a71c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1748,6 +1748,9 @@ struct X86CPU { /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; + /* Only advertise CPUID leaves defined by the vendor */ + bool vendor_cpuid_only; + /* Enable auto level-increase for Intel Processor Trace leave */ bool intel_pt_auto_level; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8e1220db728..aa79c5e0e6f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -98,6 +98,7 @@ GlobalProperty pc_compat_6_0[] = { { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, }; const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 46befde3876..6b7043e4253 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5155,6 +5155,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (cpu->cache_info_passthrough) { host_cpuid(index, 0, eax, ebx, ecx, edx); break; + } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + *eax = *ebx = *ecx = *edx = 0; + break; } *eax = 1; /* Number of CPUID[EAX=2] calls required */ *ebx = 0; @@ -5176,6 +5179,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if ((*eax & 31) && cs->nr_cores > 1) { *eax |= (cs->nr_cores - 1) << 26; } + } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + *eax = *ebx = *ecx = *edx = 0; } else { *eax = 0; switch (count) { @@ -6651,6 +6656,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), + DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Eduardo Habkost <ehabkost@redhat.com> To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org> Cc: Eduardo Habkost <ehabkost@redhat.com>, kvm@vger.kernel.org, "Michael S. Tsirkin" <mst@redhat.com>, Michael Roth <michael.roth@amd.com>, Marcelo Tosatti <mtosatti@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, "Dr. David Alan Gilbert" <dgilbert@redhat.com>, zhenwei pi <pizhenwei@bytedance.com>, Igor Mammedov <imammedo@redhat.com>, Paolo Bonzini <pbonzini@redhat.com> Subject: [PULL 08/11] target/i386: suppress CPUID leaves not defined by the CPU vendor Date: Tue, 13 Jul 2021 12:09:54 -0400 [thread overview] Message-ID: <20210713160957.3269017-9-ehabkost@redhat.com> (raw) In-Reply-To: <20210713160957.3269017-1-ehabkost@redhat.com> From: Michael Roth <michael.roth@amd.com> Currently all built-in CPUs report cache information via CPUID leaves 2 and 4, but these have never been defined for AMD. In the case of SEV-SNP this can cause issues with CPUID enforcement. Address this by allowing CPU types to suppress these via a new "x-vendor-cpuid-only" CPU property, which is true by default, but switched off for older machine types to maintain compatibility. Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: zhenwei pi <pizhenwei@bytedance.com> Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Message-Id: <20210708003623.18665-1-michael.roth@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.h | 3 +++ hw/i386/pc.c | 1 + target/i386/cpu.c | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8f3747dd285..950a991a71c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1748,6 +1748,9 @@ struct X86CPU { /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; + /* Only advertise CPUID leaves defined by the vendor */ + bool vendor_cpuid_only; + /* Enable auto level-increase for Intel Processor Trace leave */ bool intel_pt_auto_level; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8e1220db728..aa79c5e0e6f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -98,6 +98,7 @@ GlobalProperty pc_compat_6_0[] = { { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, }; const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 46befde3876..6b7043e4253 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5155,6 +5155,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (cpu->cache_info_passthrough) { host_cpuid(index, 0, eax, ebx, ecx, edx); break; + } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + *eax = *ebx = *ecx = *edx = 0; + break; } *eax = 1; /* Number of CPUID[EAX=2] calls required */ *ebx = 0; @@ -5176,6 +5179,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if ((*eax & 31) && cs->nr_cores > 1) { *eax |= (cs->nr_cores - 1) << 26; } + } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + *eax = *ebx = *ecx = *edx = 0; } else { *eax = 0; switch (count) { @@ -6651,6 +6656,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), + DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, -- 2.31.1
next prev parent reply other threads:[~2021-07-13 16:19 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-13 16:09 [PULL 00/11] x86 queue, 2021-07-13 Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 01/11] i386: clarify 'hv-passthrough' behavior Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 02/11] i386: hardcode supported eVMCS version to '1' Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 03/11] i386: make hyperv_expand_features() return bool Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 04/11] i386: expand Hyper-V features during CPU feature expansion time Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-15 20:51 ` Peter Maydell 2021-07-15 20:51 ` Peter Maydell 2021-07-16 9:07 ` Vitaly Kuznetsov 2021-07-16 9:07 ` Vitaly Kuznetsov 2021-07-13 16:09 ` [PULL 05/11] i386: kill off hv_cpuid_check_and_set() Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 06/11] i386: HV_HYPERCALL_AVAILABLE privilege bit is always needed Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 07/11] i386: Hyper-V SynIC requires POST_MESSAGES/SIGNAL_EVENTS privileges Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost [this message] 2021-07-13 16:09 ` [PULL 08/11] target/i386: suppress CPUID leaves not defined by the CPU vendor Eduardo Habkost 2021-07-13 16:09 ` [PULL 09/11] target/i386: Fix cpuid level for AMD Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 10/11] numa: Report expected initiator Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-13 16:09 ` [PULL 11/11] numa: Parse initiator= attribute before cpus= attribute Eduardo Habkost 2021-07-13 16:09 ` Eduardo Habkost 2021-07-14 13:11 ` [PULL 00/11] x86 queue, 2021-07-13 Peter Maydell 2021-07-14 13:11 ` Peter Maydell
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