[PATCH 0/6] soundwire/ASoC: abstract platform-dependent bases

[PATCH 0/6] soundwire/ASoC: abstract platform-dependent bases

[Bard Liao]

shim base and alh base are platform-dependent. This series suggests
to use variables for those bases. It allows us to use different bases
for new platforms.

Bard Liao (6):
  soundwire: move intel sdw register definitions to sdw_intel.h
  ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc
  ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition
  ASoC: SOF: intel: move sof_intel_dsp_desc() forward
  ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops
  soundwire: intel: introduce shim and alh base

 drivers/soundwire/intel.c           | 74 ------------------------
 drivers/soundwire/intel_init.c      | 14 ++---
 include/linux/soundwire/sdw_intel.h | 87 +++++++++++++++++++++++++++++
 sound/soc/sof/intel/cnl.c           |  6 ++
 sound/soc/sof/intel/hda.c           | 39 ++++++++-----
 sound/soc/sof/intel/hda.h           |  8 ++-
 sound/soc/sof/intel/icl.c           |  3 +
 sound/soc/sof/intel/shim.h          |  3 +
 sound/soc/sof/intel/tgl.c           | 12 ++++
 9 files changed, 149 insertions(+), 97 deletions(-)

-- 
2.17.1

[PATCH 0/6] soundwire/ASoC: abstract platform-dependent bases

[Bard Liao]

shim base and alh base are platform-dependent. This series suggests
to use variables for those bases. It allows us to use different bases
for new platforms.

Bard Liao (6):
  soundwire: move intel sdw register definitions to sdw_intel.h
  ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc
  ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition
  ASoC: SOF: intel: move sof_intel_dsp_desc() forward
  ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops
  soundwire: intel: introduce shim and alh base

 drivers/soundwire/intel.c           | 74 ------------------------
 drivers/soundwire/intel_init.c      | 14 ++---
 include/linux/soundwire/sdw_intel.h | 87 +++++++++++++++++++++++++++++
 sound/soc/sof/intel/cnl.c           |  6 ++
 sound/soc/sof/intel/hda.c           | 39 ++++++++-----
 sound/soc/sof/intel/hda.h           |  8 ++-
 sound/soc/sof/intel/icl.c           |  3 +
 sound/soc/sof/intel/shim.h          |  3 +
 sound/soc/sof/intel/tgl.c           | 12 ++++
 9 files changed, 149 insertions(+), 97 deletions(-)

-- 
2.17.1

[PATCH 1/6] soundwire: move intel sdw register definitions to sdw_intel.h

[Bard Liao]

So it is visible to other drivers.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 drivers/soundwire/intel.c           | 74 ---------------------------
 drivers/soundwire/intel_init.c      |  6 ---
 include/linux/soundwire/sdw_intel.h | 79 +++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+), 80 deletions(-)

diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index c11e3d8cd308..15668d6fecd6 100644
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -40,80 +40,6 @@ static int md_flags;
 module_param_named(sdw_md_flags, md_flags, int, 0444);
 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
 
-/* Intel SHIM Registers Definition */
-#define SDW_SHIM_LCAP			0x0
-#define SDW_SHIM_LCTL			0x4
-#define SDW_SHIM_IPPTR			0x8
-#define SDW_SHIM_SYNC			0xC
-
-#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
-#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
-#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
-#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
-#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
-#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
-
-#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
-#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
-#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
-
-#define SDW_SHIM_WAKEEN			0x190
-#define SDW_SHIM_WAKESTS		0x192
-
-#define SDW_SHIM_LCTL_SPA		BIT(0)
-#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
-#define SDW_SHIM_LCTL_CPA		BIT(8)
-#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
-
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
-#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
-#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
-#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
-#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
-
-#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
-#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
-#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
-
-#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
-#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
-#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
-#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
-
-#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
-#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
-#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
-#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
-
-#define SDW_SHIM_IOCTL_MIF		BIT(0)
-#define SDW_SHIM_IOCTL_CO		BIT(1)
-#define SDW_SHIM_IOCTL_COE		BIT(2)
-#define SDW_SHIM_IOCTL_DO		BIT(3)
-#define SDW_SHIM_IOCTL_DOE		BIT(4)
-#define SDW_SHIM_IOCTL_BKE		BIT(5)
-#define SDW_SHIM_IOCTL_WPDD		BIT(6)
-#define SDW_SHIM_IOCTL_CIBD		BIT(8)
-#define SDW_SHIM_IOCTL_DIBD		BIT(9)
-
-#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
-#define SDW_SHIM_CTMCTL_DODS		BIT(1)
-#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
-
-#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
-#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
-
-/* Intel ALH Register definitions */
-#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
-#define SDW_ALH_NUM_STREAMS		64
-
-#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
-#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
-#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
-
 enum intel_pdi_type {
 	INTEL_PDI_IN = 0,
 	INTEL_PDI_OUT = 1,
diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
index 9e283bef53d2..03ff69ab1797 100644
--- a/drivers/soundwire/intel_init.c
+++ b/drivers/soundwire/intel_init.c
@@ -18,12 +18,6 @@
 #include "cadence_master.h"
 #include "intel.h"
 
-#define SDW_SHIM_LCAP		0x0
-#define SDW_SHIM_BASE		0x2C000
-#define SDW_ALH_BASE		0x2C800
-#define SDW_LINK_BASE		0x30000
-#define SDW_LINK_SIZE		0x10000
-
 static void intel_link_dev_release(struct device *dev)
 {
 	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 1ebea7764011..7fce6aee0c36 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -7,6 +7,85 @@
 #include <linux/irqreturn.h>
 #include <linux/soundwire/sdw.h>
 
+#define SDW_SHIM_BASE			0x2C000
+#define SDW_ALH_BASE			0x2C800
+#define SDW_LINK_BASE			0x30000
+#define SDW_LINK_SIZE			0x10000
+
+/* Intel SHIM Registers Definition */
+#define SDW_SHIM_LCAP			0x0
+#define SDW_SHIM_LCTL			0x4
+#define SDW_SHIM_IPPTR			0x8
+#define SDW_SHIM_SYNC			0xC
+
+#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
+#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
+#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
+#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
+#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
+#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
+
+#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
+#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
+#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
+#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
+#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
+
+#define SDW_SHIM_WAKEEN			0x190
+#define SDW_SHIM_WAKESTS		0x192
+
+#define SDW_SHIM_LCTL_SPA		BIT(0)
+#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
+#define SDW_SHIM_LCTL_CPA		BIT(8)
+#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
+
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
+#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
+#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
+#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
+#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
+
+#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
+#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
+#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
+
+#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
+#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
+#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
+#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
+
+#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
+#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
+#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
+#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
+
+#define SDW_SHIM_IOCTL_MIF		BIT(0)
+#define SDW_SHIM_IOCTL_CO		BIT(1)
+#define SDW_SHIM_IOCTL_COE		BIT(2)
+#define SDW_SHIM_IOCTL_DO		BIT(3)
+#define SDW_SHIM_IOCTL_DOE		BIT(4)
+#define SDW_SHIM_IOCTL_BKE		BIT(5)
+#define SDW_SHIM_IOCTL_WPDD		BIT(6)
+#define SDW_SHIM_IOCTL_CIBD		BIT(8)
+#define SDW_SHIM_IOCTL_DIBD		BIT(9)
+
+#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
+#define SDW_SHIM_CTMCTL_DODS		BIT(1)
+#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
+
+#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
+#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
+
+/* Intel ALH Register definitions */
+#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
+#define SDW_ALH_NUM_STREAMS		64
+
+#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
+#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
+#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
+
 /**
  * struct sdw_intel_stream_params_data: configuration passed during
  * the @params_stream callback, e.g. for interaction with DSP
-- 
2.17.1

[PATCH 1/6] soundwire: move intel sdw register definitions to sdw_intel.h

[Bard Liao]

So it is visible to other drivers.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 drivers/soundwire/intel.c           | 74 ---------------------------
 drivers/soundwire/intel_init.c      |  6 ---
 include/linux/soundwire/sdw_intel.h | 79 +++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+), 80 deletions(-)

diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index c11e3d8cd308..15668d6fecd6 100644
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -40,80 +40,6 @@ static int md_flags;
 module_param_named(sdw_md_flags, md_flags, int, 0444);
 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
 
-/* Intel SHIM Registers Definition */
-#define SDW_SHIM_LCAP			0x0
-#define SDW_SHIM_LCTL			0x4
-#define SDW_SHIM_IPPTR			0x8
-#define SDW_SHIM_SYNC			0xC
-
-#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
-#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
-#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
-#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
-#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
-#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
-
-#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
-#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
-#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
-
-#define SDW_SHIM_WAKEEN			0x190
-#define SDW_SHIM_WAKESTS		0x192
-
-#define SDW_SHIM_LCTL_SPA		BIT(0)
-#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
-#define SDW_SHIM_LCTL_CPA		BIT(8)
-#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
-
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
-#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
-#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
-#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
-#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
-
-#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
-#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
-#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
-
-#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
-#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
-#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
-#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
-
-#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
-#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
-#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
-#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
-
-#define SDW_SHIM_IOCTL_MIF		BIT(0)
-#define SDW_SHIM_IOCTL_CO		BIT(1)
-#define SDW_SHIM_IOCTL_COE		BIT(2)
-#define SDW_SHIM_IOCTL_DO		BIT(3)
-#define SDW_SHIM_IOCTL_DOE		BIT(4)
-#define SDW_SHIM_IOCTL_BKE		BIT(5)
-#define SDW_SHIM_IOCTL_WPDD		BIT(6)
-#define SDW_SHIM_IOCTL_CIBD		BIT(8)
-#define SDW_SHIM_IOCTL_DIBD		BIT(9)
-
-#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
-#define SDW_SHIM_CTMCTL_DODS		BIT(1)
-#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
-
-#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
-#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
-
-/* Intel ALH Register definitions */
-#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
-#define SDW_ALH_NUM_STREAMS		64
-
-#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
-#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
-#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
-
 enum intel_pdi_type {
 	INTEL_PDI_IN = 0,
 	INTEL_PDI_OUT = 1,
diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
index 9e283bef53d2..03ff69ab1797 100644
--- a/drivers/soundwire/intel_init.c
+++ b/drivers/soundwire/intel_init.c
@@ -18,12 +18,6 @@
 #include "cadence_master.h"
 #include "intel.h"
 
-#define SDW_SHIM_LCAP		0x0
-#define SDW_SHIM_BASE		0x2C000
-#define SDW_ALH_BASE		0x2C800
-#define SDW_LINK_BASE		0x30000
-#define SDW_LINK_SIZE		0x10000
-
 static void intel_link_dev_release(struct device *dev)
 {
 	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 1ebea7764011..7fce6aee0c36 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -7,6 +7,85 @@
 #include <linux/irqreturn.h>
 #include <linux/soundwire/sdw.h>
 
+#define SDW_SHIM_BASE			0x2C000
+#define SDW_ALH_BASE			0x2C800
+#define SDW_LINK_BASE			0x30000
+#define SDW_LINK_SIZE			0x10000
+
+/* Intel SHIM Registers Definition */
+#define SDW_SHIM_LCAP			0x0
+#define SDW_SHIM_LCTL			0x4
+#define SDW_SHIM_IPPTR			0x8
+#define SDW_SHIM_SYNC			0xC
+
+#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
+#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
+#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
+#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
+#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
+#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
+
+#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
+#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
+#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
+#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
+#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
+
+#define SDW_SHIM_WAKEEN			0x190
+#define SDW_SHIM_WAKESTS		0x192
+
+#define SDW_SHIM_LCTL_SPA		BIT(0)
+#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
+#define SDW_SHIM_LCTL_CPA		BIT(8)
+#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
+
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
+#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
+#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
+#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
+#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
+
+#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
+#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
+#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
+
+#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
+#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
+#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
+#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
+
+#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
+#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
+#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
+#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
+
+#define SDW_SHIM_IOCTL_MIF		BIT(0)
+#define SDW_SHIM_IOCTL_CO		BIT(1)
+#define SDW_SHIM_IOCTL_COE		BIT(2)
+#define SDW_SHIM_IOCTL_DO		BIT(3)
+#define SDW_SHIM_IOCTL_DOE		BIT(4)
+#define SDW_SHIM_IOCTL_BKE		BIT(5)
+#define SDW_SHIM_IOCTL_WPDD		BIT(6)
+#define SDW_SHIM_IOCTL_CIBD		BIT(8)
+#define SDW_SHIM_IOCTL_DIBD		BIT(9)
+
+#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
+#define SDW_SHIM_CTMCTL_DODS		BIT(1)
+#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
+
+#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
+#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
+
+/* Intel ALH Register definitions */
+#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
+#define SDW_ALH_NUM_STREAMS		64
+
+#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
+#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
+#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
+
 /**
  * struct sdw_intel_stream_params_data: configuration passed during
  * the @params_stream callback, e.g. for interaction with DSP
-- 
2.17.1

Re: [PATCH 1/6] soundwire: move intel sdw register definitions to sdw_intel.h

[Vinod Koul]

On 14-07-21, 10:46, Bard Liao wrote:
> So it is visible to other drivers.

More detailed log please, who are others...

Otherwise the changes look fine to me, how do you wnat this to be
picked? I guess asoc parts are dependent on this

> 
> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
> ---
>  drivers/soundwire/intel.c           | 74 ---------------------------
>  drivers/soundwire/intel_init.c      |  6 ---
>  include/linux/soundwire/sdw_intel.h | 79 +++++++++++++++++++++++++++++
>  3 files changed, 79 insertions(+), 80 deletions(-)
> 
> diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
> index c11e3d8cd308..15668d6fecd6 100644
> --- a/drivers/soundwire/intel.c
> +++ b/drivers/soundwire/intel.c
> @@ -40,80 +40,6 @@ static int md_flags;
>  module_param_named(sdw_md_flags, md_flags, int, 0444);
>  MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
>  
> -/* Intel SHIM Registers Definition */
> -#define SDW_SHIM_LCAP			0x0
> -#define SDW_SHIM_LCTL			0x4
> -#define SDW_SHIM_IPPTR			0x8
> -#define SDW_SHIM_SYNC			0xC
> -
> -#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> -#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> -#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> -#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> -#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> -#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> -
> -#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
> -#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
> -#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> -#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> -#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> -
> -#define SDW_SHIM_WAKEEN			0x190
> -#define SDW_SHIM_WAKESTS		0x192
> -
> -#define SDW_SHIM_LCTL_SPA		BIT(0)
> -#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> -#define SDW_SHIM_LCTL_CPA		BIT(8)
> -#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> -
> -#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
> -#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
> -#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> -#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> -#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> -#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> -#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> -
> -#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> -#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> -#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> -
> -#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> -#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> -#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> -#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> -
> -#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> -#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> -#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> -#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> -
> -#define SDW_SHIM_IOCTL_MIF		BIT(0)
> -#define SDW_SHIM_IOCTL_CO		BIT(1)
> -#define SDW_SHIM_IOCTL_COE		BIT(2)
> -#define SDW_SHIM_IOCTL_DO		BIT(3)
> -#define SDW_SHIM_IOCTL_DOE		BIT(4)
> -#define SDW_SHIM_IOCTL_BKE		BIT(5)
> -#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> -#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> -#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> -
> -#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> -#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> -#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> -
> -#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> -#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> -
> -/* Intel ALH Register definitions */
> -#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> -#define SDW_ALH_NUM_STREAMS		64
> -
> -#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> -#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> -#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> -
>  enum intel_pdi_type {
>  	INTEL_PDI_IN = 0,
>  	INTEL_PDI_OUT = 1,
> diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
> index 9e283bef53d2..03ff69ab1797 100644
> --- a/drivers/soundwire/intel_init.c
> +++ b/drivers/soundwire/intel_init.c
> @@ -18,12 +18,6 @@
>  #include "cadence_master.h"
>  #include "intel.h"
>  
> -#define SDW_SHIM_LCAP		0x0
> -#define SDW_SHIM_BASE		0x2C000
> -#define SDW_ALH_BASE		0x2C800
> -#define SDW_LINK_BASE		0x30000
> -#define SDW_LINK_SIZE		0x10000
> -
>  static void intel_link_dev_release(struct device *dev)
>  {
>  	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
> diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
> index 1ebea7764011..7fce6aee0c36 100644
> --- a/include/linux/soundwire/sdw_intel.h
> +++ b/include/linux/soundwire/sdw_intel.h
> @@ -7,6 +7,85 @@
>  #include <linux/irqreturn.h>
>  #include <linux/soundwire/sdw.h>
>  
> +#define SDW_SHIM_BASE			0x2C000
> +#define SDW_ALH_BASE			0x2C800
> +#define SDW_LINK_BASE			0x30000
> +#define SDW_LINK_SIZE			0x10000
> +
> +/* Intel SHIM Registers Definition */
> +#define SDW_SHIM_LCAP			0x0
> +#define SDW_SHIM_LCTL			0x4
> +#define SDW_SHIM_IPPTR			0x8
> +#define SDW_SHIM_SYNC			0xC
> +
> +#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> +#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> +#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> +#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> +#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> +#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> +
> +#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
> +#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
> +#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> +#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> +#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> +
> +#define SDW_SHIM_WAKEEN			0x190
> +#define SDW_SHIM_WAKESTS		0x192
> +
> +#define SDW_SHIM_LCTL_SPA		BIT(0)
> +#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> +#define SDW_SHIM_LCTL_CPA		BIT(8)
> +#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> +
> +#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
> +#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
> +#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> +#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> +#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> +#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> +#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> +
> +#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> +#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> +#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> +
> +#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> +#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> +#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> +#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> +
> +#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> +#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> +#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> +#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> +
> +#define SDW_SHIM_IOCTL_MIF		BIT(0)
> +#define SDW_SHIM_IOCTL_CO		BIT(1)
> +#define SDW_SHIM_IOCTL_COE		BIT(2)
> +#define SDW_SHIM_IOCTL_DO		BIT(3)
> +#define SDW_SHIM_IOCTL_DOE		BIT(4)
> +#define SDW_SHIM_IOCTL_BKE		BIT(5)
> +#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> +#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> +#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> +
> +#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> +#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> +#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> +
> +#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> +#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> +
> +/* Intel ALH Register definitions */
> +#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> +#define SDW_ALH_NUM_STREAMS		64
> +
> +#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> +#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> +#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> +
>  /**
>   * struct sdw_intel_stream_params_data: configuration passed during
>   * the @params_stream callback, e.g. for interaction with DSP
> -- 
> 2.17.1

-- 
~Vinod

Re: [PATCH 1/6] soundwire: move intel sdw register definitions to sdw_intel.h

[Vinod Koul]

On 14-07-21, 10:46, Bard Liao wrote:
> So it is visible to other drivers.

More detailed log please, who are others...

Otherwise the changes look fine to me, how do you wnat this to be
picked? I guess asoc parts are dependent on this

> 
> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
> ---
>  drivers/soundwire/intel.c           | 74 ---------------------------
>  drivers/soundwire/intel_init.c      |  6 ---
>  include/linux/soundwire/sdw_intel.h | 79 +++++++++++++++++++++++++++++
>  3 files changed, 79 insertions(+), 80 deletions(-)
> 
> diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
> index c11e3d8cd308..15668d6fecd6 100644
> --- a/drivers/soundwire/intel.c
> +++ b/drivers/soundwire/intel.c
> @@ -40,80 +40,6 @@ static int md_flags;
>  module_param_named(sdw_md_flags, md_flags, int, 0444);
>  MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
>  
> -/* Intel SHIM Registers Definition */
> -#define SDW_SHIM_LCAP			0x0
> -#define SDW_SHIM_LCTL			0x4
> -#define SDW_SHIM_IPPTR			0x8
> -#define SDW_SHIM_SYNC			0xC
> -
> -#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> -#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> -#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> -#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> -#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> -#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> -
> -#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
> -#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
> -#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> -#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> -#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> -
> -#define SDW_SHIM_WAKEEN			0x190
> -#define SDW_SHIM_WAKESTS		0x192
> -
> -#define SDW_SHIM_LCTL_SPA		BIT(0)
> -#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> -#define SDW_SHIM_LCTL_CPA		BIT(8)
> -#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> -
> -#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
> -#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
> -#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> -#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> -#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> -#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> -#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> -
> -#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> -#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> -#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> -
> -#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> -#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> -#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> -#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> -
> -#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> -#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> -#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> -#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> -
> -#define SDW_SHIM_IOCTL_MIF		BIT(0)
> -#define SDW_SHIM_IOCTL_CO		BIT(1)
> -#define SDW_SHIM_IOCTL_COE		BIT(2)
> -#define SDW_SHIM_IOCTL_DO		BIT(3)
> -#define SDW_SHIM_IOCTL_DOE		BIT(4)
> -#define SDW_SHIM_IOCTL_BKE		BIT(5)
> -#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> -#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> -#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> -
> -#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> -#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> -#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> -
> -#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> -#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> -
> -/* Intel ALH Register definitions */
> -#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> -#define SDW_ALH_NUM_STREAMS		64
> -
> -#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> -#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> -#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> -
>  enum intel_pdi_type {
>  	INTEL_PDI_IN = 0,
>  	INTEL_PDI_OUT = 1,
> diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
> index 9e283bef53d2..03ff69ab1797 100644
> --- a/drivers/soundwire/intel_init.c
> +++ b/drivers/soundwire/intel_init.c
> @@ -18,12 +18,6 @@
>  #include "cadence_master.h"
>  #include "intel.h"
>  
> -#define SDW_SHIM_LCAP		0x0
> -#define SDW_SHIM_BASE		0x2C000
> -#define SDW_ALH_BASE		0x2C800
> -#define SDW_LINK_BASE		0x30000
> -#define SDW_LINK_SIZE		0x10000
> -
>  static void intel_link_dev_release(struct device *dev)
>  {
>  	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
> diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
> index 1ebea7764011..7fce6aee0c36 100644
> --- a/include/linux/soundwire/sdw_intel.h
> +++ b/include/linux/soundwire/sdw_intel.h
> @@ -7,6 +7,85 @@
>  #include <linux/irqreturn.h>
>  #include <linux/soundwire/sdw.h>
>  
> +#define SDW_SHIM_BASE			0x2C000
> +#define SDW_ALH_BASE			0x2C800
> +#define SDW_LINK_BASE			0x30000
> +#define SDW_LINK_SIZE			0x10000
> +
> +/* Intel SHIM Registers Definition */
> +#define SDW_SHIM_LCAP			0x0
> +#define SDW_SHIM_LCTL			0x4
> +#define SDW_SHIM_IPPTR			0x8
> +#define SDW_SHIM_SYNC			0xC
> +
> +#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> +#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> +#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> +#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> +#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> +#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> +
> +#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
> +#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
> +#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> +#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> +#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> +
> +#define SDW_SHIM_WAKEEN			0x190
> +#define SDW_SHIM_WAKESTS		0x192
> +
> +#define SDW_SHIM_LCTL_SPA		BIT(0)
> +#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> +#define SDW_SHIM_LCTL_CPA		BIT(8)
> +#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> +
> +#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
> +#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
> +#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> +#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> +#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> +#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> +#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> +
> +#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> +#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> +#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> +
> +#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> +#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> +#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> +#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> +
> +#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> +#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> +#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> +#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> +
> +#define SDW_SHIM_IOCTL_MIF		BIT(0)
> +#define SDW_SHIM_IOCTL_CO		BIT(1)
> +#define SDW_SHIM_IOCTL_COE		BIT(2)
> +#define SDW_SHIM_IOCTL_DO		BIT(3)
> +#define SDW_SHIM_IOCTL_DOE		BIT(4)
> +#define SDW_SHIM_IOCTL_BKE		BIT(5)
> +#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> +#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> +#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> +
> +#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> +#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> +#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> +
> +#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> +#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> +
> +/* Intel ALH Register definitions */
> +#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> +#define SDW_ALH_NUM_STREAMS		64
> +
> +#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> +#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> +#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> +
>  /**
>   * struct sdw_intel_stream_params_data: configuration passed during
>   * the @params_stream callback, e.g. for interaction with DSP
> -- 
> 2.17.1

-- 
~Vinod

RE: [PATCH 1/6] soundwire: move intel sdw register definitions to sdw_intel.h

[Liao, Bard]

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Thursday, July 22, 2021 10:25 PM
> To: Bard Liao <yung-chuan.liao@linux.intel.com>
> Cc: alsa-devel@alsa-project.org; linux-kernel@vger.kernel.org; tiwai@suse.de;
> broonie@kernel.org; gregkh@linuxfoundation.org;
> srinivas.kandagatla@linaro.org; pierre-louis.bossart@linux.intel.com; Kale,
> Sanyog R <sanyog.r.kale@intel.com>; Liao, Bard <bard.liao@intel.com>
> Subject: Re: [PATCH 1/6] soundwire: move intel sdw register definitions to
> sdw_intel.h
> 
> On 14-07-21, 10:46, Bard Liao wrote:
> > So it is visible to other drivers.
> 
> More detailed log please, who are others...

Thanks. I will send v2 to update the commit message.

> 
> Otherwise the changes look fine to me, how do you wnat this to be picked? I
> guess asoc parts are dependent on this
> 

Yes, ASoC parts are dependent on this. Maybe you can add an ACK if the
SoundWire parts look good to you. And Mark can apply the series when he
think the ASoC parts are ready to merge. The  opposite way also works for
me.

Thanks.

> >
> > Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
> > Reviewed-by: Pierre-Louis Bossart
> > <pierre-louis.bossart@linux.intel.com>
> > Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
> > ---
> >  drivers/soundwire/intel.c           | 74 ---------------------------
> >  drivers/soundwire/intel_init.c      |  6 ---
> >  include/linux/soundwire/sdw_intel.h | 79
> > +++++++++++++++++++++++++++++
> >  3 files changed, 79 insertions(+), 80 deletions(-)
> >
> > diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
> > index c11e3d8cd308..15668d6fecd6 100644
> > --- a/drivers/soundwire/intel.c
> > +++ b/drivers/soundwire/intel.c
> > @@ -40,80 +40,6 @@ static int md_flags;
> > module_param_named(sdw_md_flags, md_flags, int, 0444);
> > MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags
> > (0x0 all off)");
> >
> > -/* Intel SHIM Registers Definition */
> > -#define SDW_SHIM_LCAP			0x0
> > -#define SDW_SHIM_LCTL			0x4
> > -#define SDW_SHIM_IPPTR			0x8
> > -#define SDW_SHIM_SYNC			0xC
> > -
> > -#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> > -#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> > -
> > -#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 *
> (y)))
> > -#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 *
> (y)))
> > -#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> > -#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> > -#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> > -
> > -#define SDW_SHIM_WAKEEN			0x190
> > -#define SDW_SHIM_WAKESTS		0x192
> > -
> > -#define SDW_SHIM_LCTL_SPA		BIT(0)
> > -#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> > -#define SDW_SHIM_LCTL_CPA		BIT(8)
> > -#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> > -
> > -#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > -#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > -#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> > -#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> > -#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> > -#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> > -#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> > -
> > -#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> > -#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> > -#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> > -
> > -#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> > -#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> > -#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> > -#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> > -
> > -#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> > -#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> > -#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> > -#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> > -
> > -#define SDW_SHIM_IOCTL_MIF		BIT(0)
> > -#define SDW_SHIM_IOCTL_CO		BIT(1)
> > -#define SDW_SHIM_IOCTL_COE		BIT(2)
> > -#define SDW_SHIM_IOCTL_DO		BIT(3)
> > -#define SDW_SHIM_IOCTL_DOE		BIT(4)
> > -#define SDW_SHIM_IOCTL_BKE		BIT(5)
> > -#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> > -#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> > -#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> > -
> > -#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> > -#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> > -#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> > -
> > -#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> > -#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> > -
> > -/* Intel ALH Register definitions */
> > -#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> > -#define SDW_ALH_NUM_STREAMS		64
> > -
> > -#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> > -#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> > -#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> > -
> >  enum intel_pdi_type {
> >  	INTEL_PDI_IN = 0,
> >  	INTEL_PDI_OUT = 1,
> > diff --git a/drivers/soundwire/intel_init.c
> > b/drivers/soundwire/intel_init.c index 9e283bef53d2..03ff69ab1797
> > 100644
> > --- a/drivers/soundwire/intel_init.c
> > +++ b/drivers/soundwire/intel_init.c
> > @@ -18,12 +18,6 @@
> >  #include "cadence_master.h"
> >  #include "intel.h"
> >
> > -#define SDW_SHIM_LCAP		0x0
> > -#define SDW_SHIM_BASE		0x2C000
> > -#define SDW_ALH_BASE		0x2C800
> > -#define SDW_LINK_BASE		0x30000
> > -#define SDW_LINK_SIZE		0x10000
> > -
> >  static void intel_link_dev_release(struct device *dev)  {
> >  	struct auxiliary_device *auxdev = to_auxiliary_dev(dev); diff --git
> > a/include/linux/soundwire/sdw_intel.h
> > b/include/linux/soundwire/sdw_intel.h
> > index 1ebea7764011..7fce6aee0c36 100644
> > --- a/include/linux/soundwire/sdw_intel.h
> > +++ b/include/linux/soundwire/sdw_intel.h
> > @@ -7,6 +7,85 @@
> >  #include <linux/irqreturn.h>
> >  #include <linux/soundwire/sdw.h>
> >
> > +#define SDW_SHIM_BASE			0x2C000
> > +#define SDW_ALH_BASE			0x2C800
> > +#define SDW_LINK_BASE			0x30000
> > +#define SDW_LINK_SIZE			0x10000
> > +
> > +/* Intel SHIM Registers Definition */
> > +#define SDW_SHIM_LCAP			0x0
> > +#define SDW_SHIM_LCTL			0x4
> > +#define SDW_SHIM_IPPTR			0x8
> > +#define SDW_SHIM_SYNC			0xC
> > +
> > +#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> > +#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> > +
> > +#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 *
> (y)))
> > +#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 *
> (y)))
> > +#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> > +#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> > +#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> > +
> > +#define SDW_SHIM_WAKEEN			0x190
> > +#define SDW_SHIM_WAKESTS		0x192
> > +
> > +#define SDW_SHIM_LCTL_SPA		BIT(0)
> > +#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> > +#define SDW_SHIM_LCTL_CPA		BIT(8)
> > +#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> > +
> > +#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > +#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > +#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> > +#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> > +#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> > +#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> > +#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> > +
> > +#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> > +#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> > +#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> > +
> > +#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> > +#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> > +#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> > +#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> > +
> > +#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> > +#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> > +#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> > +#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> > +
> > +#define SDW_SHIM_IOCTL_MIF		BIT(0)
> > +#define SDW_SHIM_IOCTL_CO		BIT(1)
> > +#define SDW_SHIM_IOCTL_COE		BIT(2)
> > +#define SDW_SHIM_IOCTL_DO		BIT(3)
> > +#define SDW_SHIM_IOCTL_DOE		BIT(4)
> > +#define SDW_SHIM_IOCTL_BKE		BIT(5)
> > +#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> > +#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> > +#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> > +
> > +#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> > +#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> > +#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> > +
> > +#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> > +#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> > +
> > +/* Intel ALH Register definitions */
> > +#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> > +#define SDW_ALH_NUM_STREAMS		64
> > +
> > +#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> > +#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> > +#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> > +
> >  /**
> >   * struct sdw_intel_stream_params_data: configuration passed during
> >   * the @params_stream callback, e.g. for interaction with DSP
> > --
> > 2.17.1
> 
> --
> ~Vinod

RE: [PATCH 1/6] soundwire: move intel sdw register definitions to sdw_intel.h

[Liao, Bard]

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Thursday, July 22, 2021 10:25 PM
> To: Bard Liao <yung-chuan.liao@linux.intel.com>
> Cc: alsa-devel@alsa-project.org; linux-kernel@vger.kernel.org; tiwai@suse.de;
> broonie@kernel.org; gregkh@linuxfoundation.org;
> srinivas.kandagatla@linaro.org; pierre-louis.bossart@linux.intel.com; Kale,
> Sanyog R <sanyog.r.kale@intel.com>; Liao, Bard <bard.liao@intel.com>
> Subject: Re: [PATCH 1/6] soundwire: move intel sdw register definitions to
> sdw_intel.h
> 
> On 14-07-21, 10:46, Bard Liao wrote:
> > So it is visible to other drivers.
> 
> More detailed log please, who are others...

Thanks. I will send v2 to update the commit message.

> 
> Otherwise the changes look fine to me, how do you wnat this to be picked? I
> guess asoc parts are dependent on this
> 

Yes, ASoC parts are dependent on this. Maybe you can add an ACK if the
SoundWire parts look good to you. And Mark can apply the series when he
think the ASoC parts are ready to merge. The  opposite way also works for
me.

Thanks.

> >
> > Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
> > Reviewed-by: Pierre-Louis Bossart
> > <pierre-louis.bossart@linux.intel.com>
> > Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
> > ---
> >  drivers/soundwire/intel.c           | 74 ---------------------------
> >  drivers/soundwire/intel_init.c      |  6 ---
> >  include/linux/soundwire/sdw_intel.h | 79
> > +++++++++++++++++++++++++++++
> >  3 files changed, 79 insertions(+), 80 deletions(-)
> >
> > diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
> > index c11e3d8cd308..15668d6fecd6 100644
> > --- a/drivers/soundwire/intel.c
> > +++ b/drivers/soundwire/intel.c
> > @@ -40,80 +40,6 @@ static int md_flags;
> > module_param_named(sdw_md_flags, md_flags, int, 0444);
> > MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags
> > (0x0 all off)");
> >
> > -/* Intel SHIM Registers Definition */
> > -#define SDW_SHIM_LCAP			0x0
> > -#define SDW_SHIM_LCTL			0x4
> > -#define SDW_SHIM_IPPTR			0x8
> > -#define SDW_SHIM_SYNC			0xC
> > -
> > -#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> > -#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> > -#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> > -
> > -#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 *
> (y)))
> > -#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 *
> (y)))
> > -#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> > -#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> > -#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> > -
> > -#define SDW_SHIM_WAKEEN			0x190
> > -#define SDW_SHIM_WAKESTS		0x192
> > -
> > -#define SDW_SHIM_LCTL_SPA		BIT(0)
> > -#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> > -#define SDW_SHIM_LCTL_CPA		BIT(8)
> > -#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> > -
> > -#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > -#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > -#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> > -#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> > -#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> > -#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> > -#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> > -
> > -#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> > -#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> > -#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> > -
> > -#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> > -#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> > -#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> > -#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> > -
> > -#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> > -#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> > -#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> > -#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> > -
> > -#define SDW_SHIM_IOCTL_MIF		BIT(0)
> > -#define SDW_SHIM_IOCTL_CO		BIT(1)
> > -#define SDW_SHIM_IOCTL_COE		BIT(2)
> > -#define SDW_SHIM_IOCTL_DO		BIT(3)
> > -#define SDW_SHIM_IOCTL_DOE		BIT(4)
> > -#define SDW_SHIM_IOCTL_BKE		BIT(5)
> > -#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> > -#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> > -#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> > -
> > -#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> > -#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> > -#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> > -
> > -#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> > -#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> > -
> > -/* Intel ALH Register definitions */
> > -#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> > -#define SDW_ALH_NUM_STREAMS		64
> > -
> > -#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> > -#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> > -#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> > -
> >  enum intel_pdi_type {
> >  	INTEL_PDI_IN = 0,
> >  	INTEL_PDI_OUT = 1,
> > diff --git a/drivers/soundwire/intel_init.c
> > b/drivers/soundwire/intel_init.c index 9e283bef53d2..03ff69ab1797
> > 100644
> > --- a/drivers/soundwire/intel_init.c
> > +++ b/drivers/soundwire/intel_init.c
> > @@ -18,12 +18,6 @@
> >  #include "cadence_master.h"
> >  #include "intel.h"
> >
> > -#define SDW_SHIM_LCAP		0x0
> > -#define SDW_SHIM_BASE		0x2C000
> > -#define SDW_ALH_BASE		0x2C800
> > -#define SDW_LINK_BASE		0x30000
> > -#define SDW_LINK_SIZE		0x10000
> > -
> >  static void intel_link_dev_release(struct device *dev)  {
> >  	struct auxiliary_device *auxdev = to_auxiliary_dev(dev); diff --git
> > a/include/linux/soundwire/sdw_intel.h
> > b/include/linux/soundwire/sdw_intel.h
> > index 1ebea7764011..7fce6aee0c36 100644
> > --- a/include/linux/soundwire/sdw_intel.h
> > +++ b/include/linux/soundwire/sdw_intel.h
> > @@ -7,6 +7,85 @@
> >  #include <linux/irqreturn.h>
> >  #include <linux/soundwire/sdw.h>
> >
> > +#define SDW_SHIM_BASE			0x2C000
> > +#define SDW_ALH_BASE			0x2C800
> > +#define SDW_LINK_BASE			0x30000
> > +#define SDW_LINK_SIZE			0x10000
> > +
> > +/* Intel SHIM Registers Definition */
> > +#define SDW_SHIM_LCAP			0x0
> > +#define SDW_SHIM_LCTL			0x4
> > +#define SDW_SHIM_IPPTR			0x8
> > +#define SDW_SHIM_SYNC			0xC
> > +
> > +#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
> > +#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
> > +#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
> > +
> > +#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 *
> (y)))
> > +#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 *
> (y)))
> > +#define SDW_SHIM_PDMSCAP(x)		(0x062 + 0x60 * (x))
> > +#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
> > +#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
> > +
> > +#define SDW_SHIM_WAKEEN			0x190
> > +#define SDW_SHIM_WAKESTS		0x192
> > +
> > +#define SDW_SHIM_LCTL_SPA		BIT(0)
> > +#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
> > +#define SDW_SHIM_LCTL_CPA		BIT(8)
> > +#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)
> > +
> > +#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > +#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 /
> SDW_CADENCE_GSYNC_KHZ - 1)
> > +#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
> > +#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
> > +#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
> > +#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
> > +#define SDW_SHIM_SYNC_SYNCGO		BIT(24)
> > +
> > +#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
> > +#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
> > +#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
> > +
> > +#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
> > +#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
> > +#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
> > +#define SDW_SHIM_PCMSYCM_DIR		BIT(15)
> > +
> > +#define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
> > +#define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
> > +#define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
> > +#define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
> > +
> > +#define SDW_SHIM_IOCTL_MIF		BIT(0)
> > +#define SDW_SHIM_IOCTL_CO		BIT(1)
> > +#define SDW_SHIM_IOCTL_COE		BIT(2)
> > +#define SDW_SHIM_IOCTL_DO		BIT(3)
> > +#define SDW_SHIM_IOCTL_DOE		BIT(4)
> > +#define SDW_SHIM_IOCTL_BKE		BIT(5)
> > +#define SDW_SHIM_IOCTL_WPDD		BIT(6)
> > +#define SDW_SHIM_IOCTL_CIBD		BIT(8)
> > +#define SDW_SHIM_IOCTL_DIBD		BIT(9)
> > +
> > +#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
> > +#define SDW_SHIM_CTMCTL_DODS		BIT(1)
> > +#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
> > +
> > +#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
> > +#define SDW_SHIM_WAKESTS_STATUS		BIT(0)
> > +
> > +/* Intel ALH Register definitions */
> > +#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
> > +#define SDW_ALH_NUM_STREAMS		64
> > +
> > +#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
> > +#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
> > +#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
> > +
> >  /**
> >   * struct sdw_intel_stream_params_data: configuration passed during
> >   * the @params_stream callback, e.g. for interaction with DSP
> > --
> > 2.17.1
> 
> --
> ~Vinod

[PATCH 2/6] ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc

[Bard Liao]

sdw_shim_base and sdw_alh_base are platform-dependent. This change allow
us to define different sdw shim/alh base for each platform.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/cnl.c  | 4 ++++
 sound/soc/sof/intel/icl.c  | 2 ++
 sound/soc/sof/intel/shim.h | 2 ++
 sound/soc/sof/intel/tgl.c  | 8 ++++++++
 4 files changed, 16 insertions(+)

diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
index 821f25fbcf08..acc07cfbc8e3 100644
--- a/sound/soc/sof/intel/cnl.c
+++ b/sound/soc/sof/intel/cnl.c
@@ -347,6 +347,8 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = CNL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -363,5 +365,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/icl.c b/sound/soc/sof/intel/icl.c
index 88a74be8a0c1..74a14b24794c 100644
--- a/sound/soc/sof/intel/icl.c
+++ b/sound/soc/sof/intel/icl.c
@@ -142,5 +142,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index 529f68d0ca47..ee031248d834 100644
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -164,6 +164,8 @@ struct sof_intel_dsp_desc {
 	int rom_init_timeout;
 	int ssp_count;			/* ssp count of the platform */
 	int ssp_base_offset;		/* base address of the SSPs */
+	u32 sdw_shim_base;
+	u32 sdw_alh_base;
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 2ed788304414..73aa45bc6f2b 100644
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -137,6 +137,8 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -153,6 +155,8 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -169,6 +173,8 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -185,5 +191,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
-- 
2.17.1

[PATCH 2/6] ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc

[Bard Liao]

sdw_shim_base and sdw_alh_base are platform-dependent. This change allow
us to define different sdw shim/alh base for each platform.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/cnl.c  | 4 ++++
 sound/soc/sof/intel/icl.c  | 2 ++
 sound/soc/sof/intel/shim.h | 2 ++
 sound/soc/sof/intel/tgl.c  | 8 ++++++++
 4 files changed, 16 insertions(+)

diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
index 821f25fbcf08..acc07cfbc8e3 100644
--- a/sound/soc/sof/intel/cnl.c
+++ b/sound/soc/sof/intel/cnl.c
@@ -347,6 +347,8 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = CNL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -363,5 +365,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/icl.c b/sound/soc/sof/intel/icl.c
index 88a74be8a0c1..74a14b24794c 100644
--- a/sound/soc/sof/intel/icl.c
+++ b/sound/soc/sof/intel/icl.c
@@ -142,5 +142,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index 529f68d0ca47..ee031248d834 100644
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -164,6 +164,8 @@ struct sof_intel_dsp_desc {
 	int rom_init_timeout;
 	int ssp_count;			/* ssp count of the platform */
 	int ssp_base_offset;		/* base address of the SSPs */
+	u32 sdw_shim_base;
+	u32 sdw_alh_base;
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 2ed788304414..73aa45bc6f2b 100644
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -137,6 +137,8 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -153,6 +155,8 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -169,6 +173,8 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -185,5 +191,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
 	.rom_init_timeout	= 300,
 	.ssp_count = ICL_SSP_COUNT,
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
+	.sdw_shim_base = SDW_SHIM_BASE,
+	.sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
-- 
2.17.1

[PATCH 3/6] ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition

[Bard Liao]

HDA_DSP_REG_SNDW_WAKE_STS is actually (SDW_SHIM_BASE + SDW_SHIM_WAKESTS)
and SDW_SHIM_BASE is platform-dependent. Removing HDA_DSP_REG_SNDW_WAKE_STS
and use (hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS) instead.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/hda.c | 2 +-
 sound/soc/sof/intel/hda.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index e1e368ff2b12..e48e030f6005 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -249,7 +249,7 @@ static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 	hdev = sdev->pdata->hw_pdata;
 	if (hdev->sdw &&
 	    snd_sof_dsp_read(sdev, HDA_DSP_BAR,
-			     HDA_DSP_REG_SNDW_WAKE_STS))
+			     hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS))
 		return true;
 
 	return false;
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 4d44f8910393..06ea0006999a 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -233,7 +233,6 @@
 #define HDA_DSP_REG_ADSPIS2		(HDA_DSP_GEN_BASE + 0x14)
 
 #define HDA_DSP_REG_ADSPIS2_SNDW	BIT(5)
-#define HDA_DSP_REG_SNDW_WAKE_STS      0x2C192
 
 /* Intel HD Audio Inter-Processor Communication Registers */
 #define HDA_DSP_IPC_BASE		0x40
-- 
2.17.1

[PATCH 3/6] ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition

[Bard Liao]

HDA_DSP_REG_SNDW_WAKE_STS is actually (SDW_SHIM_BASE + SDW_SHIM_WAKESTS)
and SDW_SHIM_BASE is platform-dependent. Removing HDA_DSP_REG_SNDW_WAKE_STS
and use (hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS) instead.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/hda.c | 2 +-
 sound/soc/sof/intel/hda.h | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index e1e368ff2b12..e48e030f6005 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -249,7 +249,7 @@ static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 	hdev = sdev->pdata->hw_pdata;
 	if (hdev->sdw &&
 	    snd_sof_dsp_read(sdev, HDA_DSP_BAR,
-			     HDA_DSP_REG_SNDW_WAKE_STS))
+			     hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS))
 		return true;
 
 	return false;
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 4d44f8910393..06ea0006999a 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -233,7 +233,6 @@
 #define HDA_DSP_REG_ADSPIS2		(HDA_DSP_GEN_BASE + 0x14)
 
 #define HDA_DSP_REG_ADSPIS2_SNDW	BIT(5)
-#define HDA_DSP_REG_SNDW_WAKE_STS      0x2C192
 
 /* Intel HD Audio Inter-Processor Communication Registers */
 #define HDA_DSP_IPC_BASE		0x40
-- 
2.17.1

[PATCH 4/6] ASoC: SOF: intel: move sof_intel_dsp_desc() forward

[Bard Liao]

sof_intel_dsp_desc() will be used by hda_dsp_check_sdw_irq() in the
following commit.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/hda.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index e48e030f6005..79388489c4e2 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -41,6 +41,17 @@
 #define EXCEPT_MAX_HDR_SIZE	0x400
 #define HDA_EXT_ROM_STATUS_SIZE 8
 
+static const struct sof_intel_dsp_desc
+	*get_chip_info(struct snd_sof_pdata *pdata)
+{
+	const struct sof_dev_desc *desc = pdata->desc;
+	const struct sof_intel_dsp_desc *chip_info;
+
+	chip_info = desc->chip_info;
+
+	return chip_info;
+}
+
 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
 
 /*
@@ -668,17 +679,6 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
 	return 0;
 }
 
-static const struct sof_intel_dsp_desc
-	*get_chip_info(struct snd_sof_pdata *pdata)
-{
-	const struct sof_dev_desc *desc = pdata->desc;
-	const struct sof_intel_dsp_desc *chip_info;
-
-	chip_info = desc->chip_info;
-
-	return chip_info;
-}
-
 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
 {
 	struct snd_sof_dev *sdev = context;
-- 
2.17.1

[PATCH 4/6] ASoC: SOF: intel: move sof_intel_dsp_desc() forward

[Bard Liao]

sof_intel_dsp_desc() will be used by hda_dsp_check_sdw_irq() in the
following commit.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/hda.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index e48e030f6005..79388489c4e2 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -41,6 +41,17 @@
 #define EXCEPT_MAX_HDR_SIZE	0x400
 #define HDA_EXT_ROM_STATUS_SIZE 8
 
+static const struct sof_intel_dsp_desc
+	*get_chip_info(struct snd_sof_pdata *pdata)
+{
+	const struct sof_dev_desc *desc = pdata->desc;
+	const struct sof_intel_dsp_desc *chip_info;
+
+	chip_info = desc->chip_info;
+
+	return chip_info;
+}
+
 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
 
 /*
@@ -668,17 +679,6 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
 	return 0;
 }
 
-static const struct sof_intel_dsp_desc
-	*get_chip_info(struct snd_sof_pdata *pdata)
-{
-	const struct sof_dev_desc *desc = pdata->desc;
-	const struct sof_intel_dsp_desc *chip_info;
-
-	chip_info = desc->chip_info;
-
-	return chip_info;
-}
-
 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
 {
 	struct snd_sof_dev *sdev = context;
-- 
2.17.1

[PATCH 5/6] ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops

[Bard Liao]

SoundWire IRQ status checks are platform-dependent, add new ops structure
to provide abstraction.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/cnl.c  |  2 ++
 sound/soc/sof/intel/hda.c  | 13 ++++++++++++-
 sound/soc/sof/intel/hda.h  |  7 +++++++
 sound/soc/sof/intel/icl.c  |  1 +
 sound/soc/sof/intel/shim.h |  1 +
 sound/soc/sof/intel/tgl.c  |  4 ++++
 6 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
index acc07cfbc8e3..e115e12a856f 100644
--- a/sound/soc/sof/intel/cnl.c
+++ b/sound/soc/sof/intel/cnl.c
@@ -349,6 +349,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -367,5 +368,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index 79388489c4e2..c979581c6812 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -222,7 +222,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev)
 	return 0;
 }
 
-static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
+bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
 {
 	struct sof_intel_hda_dev *hdev;
 	bool ret = false;
@@ -248,6 +248,17 @@ static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
 	return ret;
 }
 
+static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
+{
+	const struct sof_intel_dsp_desc *chip;
+
+	chip = get_chip_info(sdev->pdata);
+	if (chip && chip->check_sdw_irq)
+		return chip->check_sdw_irq(sdev);
+
+	return false;
+}
+
 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
 {
 	return sdw_intel_thread(irq, context);
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 06ea0006999a..4fdfb108645c 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -691,6 +691,7 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 int hda_sdw_startup(struct snd_sof_dev *sdev);
 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
+bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
 
 #else
 
@@ -736,6 +737,12 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
 {
 }
+
+static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
+{
+	return false;
+}
+
 #endif
 
 /* common dai driver */
diff --git a/sound/soc/sof/intel/icl.c b/sound/soc/sof/intel/icl.c
index 74a14b24794c..ee095b8f2d01 100644
--- a/sound/soc/sof/intel/icl.c
+++ b/sound/soc/sof/intel/icl.c
@@ -144,5 +144,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index ee031248d834..e9f7d4d7fcce 100644
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -166,6 +166,7 @@ struct sof_intel_dsp_desc {
 	int ssp_base_offset;		/* base address of the SSPs */
 	u32 sdw_shim_base;
 	u32 sdw_alh_base;
+	bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 73aa45bc6f2b..199d41a7dc9b 100644
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -157,6 +158,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -175,6 +177,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -193,5 +196,6 @@ const struct sof_intel_dsp_desc adls_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
-- 
2.17.1

[PATCH 5/6] ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops

[Bard Liao]

SoundWire IRQ status checks are platform-dependent, add new ops structure
to provide abstraction.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 sound/soc/sof/intel/cnl.c  |  2 ++
 sound/soc/sof/intel/hda.c  | 13 ++++++++++++-
 sound/soc/sof/intel/hda.h  |  7 +++++++
 sound/soc/sof/intel/icl.c  |  1 +
 sound/soc/sof/intel/shim.h |  1 +
 sound/soc/sof/intel/tgl.c  |  4 ++++
 6 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
index acc07cfbc8e3..e115e12a856f 100644
--- a/sound/soc/sof/intel/cnl.c
+++ b/sound/soc/sof/intel/cnl.c
@@ -349,6 +349,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -367,5 +368,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index 79388489c4e2..c979581c6812 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -222,7 +222,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev)
 	return 0;
 }
 
-static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
+bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
 {
 	struct sof_intel_hda_dev *hdev;
 	bool ret = false;
@@ -248,6 +248,17 @@ static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
 	return ret;
 }
 
+static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
+{
+	const struct sof_intel_dsp_desc *chip;
+
+	chip = get_chip_info(sdev->pdata);
+	if (chip && chip->check_sdw_irq)
+		return chip->check_sdw_irq(sdev);
+
+	return false;
+}
+
 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
 {
 	return sdw_intel_thread(irq, context);
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 06ea0006999a..4fdfb108645c 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -691,6 +691,7 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 int hda_sdw_startup(struct snd_sof_dev *sdev);
 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
+bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
 
 #else
 
@@ -736,6 +737,12 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
 {
 }
+
+static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
+{
+	return false;
+}
+
 #endif
 
 /* common dai driver */
diff --git a/sound/soc/sof/intel/icl.c b/sound/soc/sof/intel/icl.c
index 74a14b24794c..ee095b8f2d01 100644
--- a/sound/soc/sof/intel/icl.c
+++ b/sound/soc/sof/intel/icl.c
@@ -144,5 +144,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index ee031248d834..e9f7d4d7fcce 100644
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -166,6 +166,7 @@ struct sof_intel_dsp_desc {
 	int ssp_base_offset;		/* base address of the SSPs */
 	u32 sdw_shim_base;
 	u32 sdw_alh_base;
+	bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 73aa45bc6f2b..199d41a7dc9b 100644
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -157,6 +158,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -175,6 +177,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -193,5 +196,6 @@ const struct sof_intel_dsp_desc adls_chip_info = {
 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
 	.sdw_shim_base = SDW_SHIM_BASE,
 	.sdw_alh_base = SDW_ALH_BASE,
+	.check_sdw_irq	= hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
-- 
2.17.1

[PATCH 6/6] soundwire: intel: introduce shim and alh base

[Bard Liao]

shim base and alh base are platform-dependent. Adding these two
parameters allows us to use different shim/alh base for each
platform.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 drivers/soundwire/intel_init.c      | 8 +++++---
 include/linux/soundwire/sdw_intel.h | 8 ++++++++
 sound/soc/sof/intel/hda.c           | 2 ++
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
index 03ff69ab1797..e329022e1669 100644
--- a/drivers/soundwire/intel_init.c
+++ b/drivers/soundwire/intel_init.c
@@ -63,8 +63,8 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res *
 	link->mmio_base = res->mmio_base;
 	link->registers = res->mmio_base + SDW_LINK_BASE
 		+ (SDW_LINK_SIZE * link_id);
-	link->shim = res->mmio_base + SDW_SHIM_BASE;
-	link->alh = res->mmio_base + SDW_ALH_BASE;
+	link->shim = res->mmio_base + res->shim_base;
+	link->alh = res->mmio_base + res->alh_base;
 
 	link->ops = res->ops;
 	link->dev = res->dev;
@@ -214,6 +214,8 @@ static struct sdw_intel_ctx
 	}
 
 	ctx->mmio_base = res->mmio_base;
+	ctx->shim_base = res->shim_base;
+	ctx->alh_base = res->alh_base;
 	ctx->link_mask = res->link_mask;
 	ctx->handle = res->handle;
 	mutex_init(&ctx->shim_lock);
@@ -302,7 +304,7 @@ sdw_intel_startup_controller(struct sdw_intel_ctx *ctx)
 		return -EINVAL;
 
 	/* Check SNDWLCAP.LCOUNT */
-	caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);
+	caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);
 	caps &= GENMASK(2, 0);
 
 	/* Check HW supported vs property value */
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 7fce6aee0c36..8a463b8fc12a 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -195,6 +195,8 @@ struct sdw_intel_slave_id {
  * @link_list: list to handle interrupts across all links
  * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
  * @shim_mask: flags to track initialization of SHIM shared registers
+ * @shim_base: sdw shim base.
+ * @alh_base: sdw alh base.
  */
 struct sdw_intel_ctx {
 	int count;
@@ -207,6 +209,8 @@ struct sdw_intel_ctx {
 	struct list_head link_list;
 	struct mutex shim_lock; /* lock for access to shared SHIM registers */
 	u32 shim_mask;
+	u32 shim_base;
+	u32 alh_base;
 };
 
 /**
@@ -225,6 +229,8 @@ struct sdw_intel_ctx {
  * machine-specific quirks are handled in the DSP driver.
  * @clock_stop_quirks: mask array of possible behaviors requested by the
  * DSP driver. The quirks are common for all links for now.
+ * @shim_base: sdw shim base.
+ * @alh_base: sdw alh base.
  */
 struct sdw_intel_res {
 	int count;
@@ -236,6 +242,8 @@ struct sdw_intel_res {
 	struct device *dev;
 	u32 link_mask;
 	u32 clock_stop_quirks;
+	u32 shim_base;
+	u32 alh_base;
 };
 
 /*
diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index c979581c6812..b4e35fbbe693 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -166,6 +166,8 @@ static int hda_sdw_probe(struct snd_sof_dev *sdev)
 	memset(&res, 0, sizeof(res));
 
 	res.mmio_base = sdev->bar[HDA_DSP_BAR];
+	res.shim_base = hdev->desc->sdw_shim_base;
+	res.alh_base = hdev->desc->sdw_alh_base;
 	res.irq = sdev->ipc_irq;
 	res.handle = hdev->info.handle;
 	res.parent = sdev->dev;
-- 
2.17.1

[PATCH 6/6] soundwire: intel: introduce shim and alh base

[Bard Liao]

shim base and alh base are platform-dependent. Adding these two
parameters allows us to use different shim/alh base for each
platform.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
---
 drivers/soundwire/intel_init.c      | 8 +++++---
 include/linux/soundwire/sdw_intel.h | 8 ++++++++
 sound/soc/sof/intel/hda.c           | 2 ++
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
index 03ff69ab1797..e329022e1669 100644
--- a/drivers/soundwire/intel_init.c
+++ b/drivers/soundwire/intel_init.c
@@ -63,8 +63,8 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res *
 	link->mmio_base = res->mmio_base;
 	link->registers = res->mmio_base + SDW_LINK_BASE
 		+ (SDW_LINK_SIZE * link_id);
-	link->shim = res->mmio_base + SDW_SHIM_BASE;
-	link->alh = res->mmio_base + SDW_ALH_BASE;
+	link->shim = res->mmio_base + res->shim_base;
+	link->alh = res->mmio_base + res->alh_base;
 
 	link->ops = res->ops;
 	link->dev = res->dev;
@@ -214,6 +214,8 @@ static struct sdw_intel_ctx
 	}
 
 	ctx->mmio_base = res->mmio_base;
+	ctx->shim_base = res->shim_base;
+	ctx->alh_base = res->alh_base;
 	ctx->link_mask = res->link_mask;
 	ctx->handle = res->handle;
 	mutex_init(&ctx->shim_lock);
@@ -302,7 +304,7 @@ sdw_intel_startup_controller(struct sdw_intel_ctx *ctx)
 		return -EINVAL;
 
 	/* Check SNDWLCAP.LCOUNT */
-	caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);
+	caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);
 	caps &= GENMASK(2, 0);
 
 	/* Check HW supported vs property value */
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 7fce6aee0c36..8a463b8fc12a 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -195,6 +195,8 @@ struct sdw_intel_slave_id {
  * @link_list: list to handle interrupts across all links
  * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
  * @shim_mask: flags to track initialization of SHIM shared registers
+ * @shim_base: sdw shim base.
+ * @alh_base: sdw alh base.
  */
 struct sdw_intel_ctx {
 	int count;
@@ -207,6 +209,8 @@ struct sdw_intel_ctx {
 	struct list_head link_list;
 	struct mutex shim_lock; /* lock for access to shared SHIM registers */
 	u32 shim_mask;
+	u32 shim_base;
+	u32 alh_base;
 };
 
 /**
@@ -225,6 +229,8 @@ struct sdw_intel_ctx {
  * machine-specific quirks are handled in the DSP driver.
  * @clock_stop_quirks: mask array of possible behaviors requested by the
  * DSP driver. The quirks are common for all links for now.
+ * @shim_base: sdw shim base.
+ * @alh_base: sdw alh base.
  */
 struct sdw_intel_res {
 	int count;
@@ -236,6 +242,8 @@ struct sdw_intel_res {
 	struct device *dev;
 	u32 link_mask;
 	u32 clock_stop_quirks;
+	u32 shim_base;
+	u32 alh_base;
 };
 
 /*
diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index c979581c6812..b4e35fbbe693 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -166,6 +166,8 @@ static int hda_sdw_probe(struct snd_sof_dev *sdev)
 	memset(&res, 0, sizeof(res));
 
 	res.mmio_base = sdev->bar[HDA_DSP_BAR];
+	res.shim_base = hdev->desc->sdw_shim_base;
+	res.alh_base = hdev->desc->sdw_alh_base;
 	res.irq = sdev->ipc_irq;
 	res.handle = hdev->info.handle;
 	res.parent = sdev->dev;
-- 
2.17.1