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From: Oliver Graute <oliver.graute@kococonnector.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: shawnguo@kernel.org, devicetree@vger.kernel.org,
	aisheng.dong@nxp.com, fabio.estevam@nxp.com,
	Rob Herring <robh+dt@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] arm64: dts: imx8qm: added System MMU
Date: Thu, 15 Jul 2021 10:46:44 +0200	[thread overview]
Message-ID: <20210715084644.GA28307@optiplex> (raw)
In-Reply-To: <d10b6230-6a7d-05c9-47ec-6defe840d827@arm.com>

On 14/07/21, Robin Murphy wrote:
> On 2021-07-14 13:09, Oliver Graute wrote:
> > added node for System MMU
> 
> Note that it's a bit of a dangerous game to enable an SMMU without the
> complete Stream ID topology for *all* its upstream devices also described,
> since CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT will ruin peoples' day. It
> might be more polite to add it in a disabled state until every "iommus"
> property has been filled in, so that people who do want to play with it for
> specific devices in the meantime can easily just flip the status (while
> taking the necessary precautions), but people who don't care won't be
> inadvertently affected regardless of their kernel config. I'm assuming an
> SMMU with 32 contexts has more than a single USB controller behind it...

thx for the explanation. So I will set this node to disabled state in
next version of this patch.
> 
> >   	};
> > +	smmu: iommu@51400000 {
> > +		compatible = "arm,mmu-500";
> > +		interrupt-parent = <&gic>;
> > +		reg = <0 0x51400000 0 0x40000>;
> > +		#global-interrupts = <1>;
> > +		#iommu-cells = <2>;
> > +		interrupts = <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
		status = "disabled";
> > +	};

Best regards,

Oliver

WARNING: multiple messages have this Message-ID (diff)
From: Oliver Graute <oliver.graute@kococonnector.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: shawnguo@kernel.org, devicetree@vger.kernel.org,
	aisheng.dong@nxp.com, fabio.estevam@nxp.com,
	Rob Herring <robh+dt@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] arm64: dts: imx8qm: added System MMU
Date: Thu, 15 Jul 2021 10:46:44 +0200	[thread overview]
Message-ID: <20210715084644.GA28307@optiplex> (raw)
In-Reply-To: <d10b6230-6a7d-05c9-47ec-6defe840d827@arm.com>

On 14/07/21, Robin Murphy wrote:
> On 2021-07-14 13:09, Oliver Graute wrote:
> > added node for System MMU
> 
> Note that it's a bit of a dangerous game to enable an SMMU without the
> complete Stream ID topology for *all* its upstream devices also described,
> since CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT will ruin peoples' day. It
> might be more polite to add it in a disabled state until every "iommus"
> property has been filled in, so that people who do want to play with it for
> specific devices in the meantime can easily just flip the status (while
> taking the necessary precautions), but people who don't care won't be
> inadvertently affected regardless of their kernel config. I'm assuming an
> SMMU with 32 contexts has more than a single USB controller behind it...

thx for the explanation. So I will set this node to disabled state in
next version of this patch.
> 
> >   	};
> > +	smmu: iommu@51400000 {
> > +		compatible = "arm,mmu-500";
> > +		interrupt-parent = <&gic>;
> > +		reg = <0 0x51400000 0 0x40000>;
> > +		#global-interrupts = <1>;
> > +		#iommu-cells = <2>;
> > +		interrupts = <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
		status = "disabled";
> > +	};

Best regards,

Oliver

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  reply	other threads:[~2021-07-15  8:47 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-14 12:09 [PATCH v2] arm64: dts: imx8qm: add compatible string for usdhc3 Oliver Graute
2021-07-14 12:09 ` Oliver Graute
2021-07-14 12:09 ` [PATCH v1] arm64: dts: imx8qm: enabled watchdog Oliver Graute
2021-07-14 12:09   ` Oliver Graute
2021-07-14 12:09 ` [PATCH v1] arm64: dts: imx8qm: added System MMU Oliver Graute
2021-07-14 12:09   ` Oliver Graute
2021-07-14 14:37   ` Robin Murphy
2021-07-14 14:37     ` Robin Murphy
2021-07-15  8:46     ` Oliver Graute [this message]
2021-07-15  8:46       ` Oliver Graute
2021-07-14 12:09 ` [PATCH v1] arm64: dts: imx8qm: added pinctrl for pciea Oliver Graute
2021-07-14 12:09   ` Oliver Graute
2021-07-14 12:09 ` [PATCH v1] arm64: dts: imx8: added usb nodes to imx8-ss-conn.dtsi Oliver Graute
2021-07-14 12:09   ` Oliver Graute
2021-07-14 12:09 ` [PATCH v1] arm64: dts: imx8: added usbotg3 node to imx8qm-ss-conn.dtsi Oliver Graute
2021-07-14 12:09   ` Oliver Graute
2021-07-14 12:09 ` [PATCH v1] arm64: dts: imx8qm: added usb nodes to imx8qm.dtsi Oliver Graute
2021-07-14 12:09   ` Oliver Graute

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