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* [PATCH] drm/amdgpu: Add error message when programing registers fails
@ 2021-07-15 12:14 Roy Sun
  0 siblings, 0 replies; 4+ messages in thread
From: Roy Sun @ 2021-07-15 12:14 UTC (permalink / raw)
  To: amd-gfx; +Cc: Roy Sun

Signed-off-by: Roy Sun <Roy.Sun@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bc4347a72301..3ac0d27e8ad1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,6 +56,10 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
 #define GFX10_MEC_HPD_SIZE	2048
 
+#define RLCG_INTERFACE_NOT_ENABLED	0x4000000
+#define RLCG_WRONG_OPERATION_TYPE	0x2000000
+#define RLCG_NOT_IN_RANGE	0x1000000
+
 #define F32_CE_PROGRAM_RAM_SIZE		65536
 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
 
@@ -1523,9 +1527,9 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 		writel(v, scratch_reg0);
 		writel(offset | flag, scratch_reg1);
 		writel(1, spare_int);
-		for (i = 0; i < retries; i++) {
-			u32 tmp;
+		u32 tmp;
 
+		for (i = 0; i < retries; i++) {
 			tmp = readl(scratch_reg1);
 			if (!(tmp & flag))
 				break;
@@ -1533,8 +1537,20 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 			udelay(10);
 		}
 
-		if (i >= retries)
-			pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
+		if (i >= retries) {
+			if (amdgpu_sriov_reg_indirect_mmhub(adev) ||
+					amdgpu_sriov_reg_indirect_gc(adev)) {
+				if (tmp & RLCG_INTERFACE_NOT_ENABLED)
+					pr_err("The interface is not enabled, program reg:0x%05x failed!\n", offset);
+				else if (tmp & RLCG_WRONG_OPERATION_TYPE)
+					pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
+				else if (tmp & RLCG_NOT_IN_RANGE)
+					pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
+				else
+					pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
+			} else
+				pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
+		}
 	}
 
 	ret = readl(scratch_reg0);
-- 
2.32.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu: Add error message when programing registers fails
  2021-07-20  5:57 Roy Sun
@ 2021-07-20 10:22 ` Zhou, Peng Ju
  0 siblings, 0 replies; 4+ messages in thread
From: Zhou, Peng Ju @ 2021-07-20 10:22 UTC (permalink / raw)
  To: Sun, Roy, amd-gfx; +Cc: Sun, Roy

[AMD Official Use Only]

Update inline

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Roy Sun
> Sent: Tuesday, July 20, 2021 1:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Sun, Roy <Roy.Sun@amd.com>
> Subject: [PATCH] drm/amdgpu: Add error message when programing registers
> fails
> 
> Signed-off-by: Roy Sun <Roy.Sun@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 ++++++++++++++++++++++----
>  1 file changed, 22 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bc4347a72301..67a6fffd528b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -56,6 +56,10 @@
>  #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
>  #define GFX10_MEC_HPD_SIZE	2048
> 
> +#define RLCG_INTERFACE_NOT_ENABLED	0x4000000
> +#define RLCG_WRONG_OPERATION_TYPE	0x2000000
> +#define RLCG_NOT_IN_RANGE	0x1000000
> +
>  #define F32_CE_PROGRAM_RAM_SIZE		65536
>  #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
> 
> @@ -185,6 +189,9 @@
>  #define GFX_RLCG_GC_READ	(0x1 << 28)
>  #define GFX_RLCG_MMHUB_WRITE	(0x2 << 28)
> 
> +#define RLCG_ERROR_REPORT_ENABLED(adev) \
> +	(amdgpu_sriov_reg_indirect_mmhub(adev) ||
> amdgpu_sriov_reg_indirect_gc(adev))
> +
>  MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
>  MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
>  MODULE_FIRMWARE("amdgpu/navi10_me.bin");
> @@ -1523,9 +1530,9 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device
> *adev, u32 offset, u32 v, uint32
>  		writel(v, scratch_reg0);
>  		writel(offset | flag, scratch_reg1);
>  		writel(1, spare_int);
> -		for (i = 0; i < retries; i++) {
> -			u32 tmp;
> +		u32 tmp;
> 
> +		for (i = 0; i < retries; i++) {
>  			tmp = readl(scratch_reg1);
>  			if (!(tmp & flag))
>  				break;
> @@ -1533,8 +1540,19 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device
> *adev, u32 offset, u32 v, uint32
>  			udelay(10);
>  		}
> 
> -		if (i >= retries)
> -			pr_err("timeout: rlcg program reg:0x%05x failed !\n",
> offset);
> +		if (i >= retries) {
> +			if (RLCG_ERROR_REPORT_ENABLED(adev)) {
> +				if (tmp & RLCG_INTERFACE_NOT_ENABLED)
> +					pr_err("The interface is not enabled,
> program reg:0x%05x failed!\n", offset);
Rlcg interface is here, but rlcg vfgate is closed, Can we print rlcg vfgate is disabled?
> +				else if (tmp &
> RLCG_WRONG_OPERATION_TYPE)
> +					pr_err("Wrong operation type,
> program reg:0x%05x failed!\n", offset);
> +				else if (tmp & RLCG_NOT_IN_RANGE)
> +					pr_err("The register is not in range,
> program reg:0x%05x failed!\n", offset);
> +				else
> +					pr_err("Unknown error type, program
> reg:0x%05x failed!\n", offset);
> +			} else
> +				pr_err("timeout: rlcg program reg:0x%05x
> failed!\n", offset);
> +		}
>  	}
> 
>  	ret = readl(scratch_reg0);
> --
> 2.32.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.fr
> eedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&amp;data=04%7C01%7CPengju.Zhou%40amd.com%7Ca462e6a099324085
> 069308d94b438cb4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> 37623575771035281%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Hn
> AyuX7Zx7fg0jN4d61Up48dimBSKRMomfN44UFEliE%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH] drm/amdgpu: Add error message when programing registers fails
@ 2021-07-20  5:57 Roy Sun
  2021-07-20 10:22 ` Zhou, Peng Ju
  0 siblings, 1 reply; 4+ messages in thread
From: Roy Sun @ 2021-07-20  5:57 UTC (permalink / raw)
  To: amd-gfx; +Cc: Roy Sun

Signed-off-by: Roy Sun <Roy.Sun@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bc4347a72301..67a6fffd528b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,6 +56,10 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
 #define GFX10_MEC_HPD_SIZE	2048
 
+#define RLCG_INTERFACE_NOT_ENABLED	0x4000000
+#define RLCG_WRONG_OPERATION_TYPE	0x2000000
+#define RLCG_NOT_IN_RANGE	0x1000000
+
 #define F32_CE_PROGRAM_RAM_SIZE		65536
 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
 
@@ -185,6 +189,9 @@
 #define GFX_RLCG_GC_READ	(0x1 << 28)
 #define GFX_RLCG_MMHUB_WRITE	(0x2 << 28)
 
+#define RLCG_ERROR_REPORT_ENABLED(adev) \
+	(amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
+
 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -1523,9 +1530,9 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 		writel(v, scratch_reg0);
 		writel(offset | flag, scratch_reg1);
 		writel(1, spare_int);
-		for (i = 0; i < retries; i++) {
-			u32 tmp;
+		u32 tmp;
 
+		for (i = 0; i < retries; i++) {
 			tmp = readl(scratch_reg1);
 			if (!(tmp & flag))
 				break;
@@ -1533,8 +1540,19 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 			udelay(10);
 		}
 
-		if (i >= retries)
-			pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
+		if (i >= retries) {
+			if (RLCG_ERROR_REPORT_ENABLED(adev)) {
+				if (tmp & RLCG_INTERFACE_NOT_ENABLED)
+					pr_err("The interface is not enabled, program reg:0x%05x failed!\n", offset);
+				else if (tmp & RLCG_WRONG_OPERATION_TYPE)
+					pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
+				else if (tmp & RLCG_NOT_IN_RANGE)
+					pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
+				else
+					pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
+			} else
+				pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
+		}
 	}
 
 	ret = readl(scratch_reg0);
-- 
2.32.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] drm/amdgpu: Add error message when programing registers fails
@ 2021-07-13 11:14 Roy Sun
  0 siblings, 0 replies; 4+ messages in thread
From: Roy Sun @ 2021-07-13 11:14 UTC (permalink / raw)
  To: amd-gfx; +Cc: Roy Sun

Signed-off-by: Roy Sun <Roy.Sun@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bc4347a72301..a7e03bba72b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,6 +56,10 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
 #define GFX10_MEC_HPD_SIZE	2048
 
+#define INTERFACE_NOT_ENABLED_FLAG	0x4000000
+#define WRONG_OPERATION_TYPE_FLAG	0x2000000
+#define NOT_IN_RANGE_FLAG	0x1000000
+
 #define F32_CE_PROGRAM_RAM_SIZE		65536
 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
 
@@ -1523,9 +1527,9 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 		writel(v, scratch_reg0);
 		writel(offset | flag, scratch_reg1);
 		writel(1, spare_int);
-		for (i = 0; i < retries; i++) {
-			u32 tmp;
+		u32 tmp;
 
+		for (i = 0; i < retries; i++) {
 			tmp = readl(scratch_reg1);
 			if (!(tmp & flag))
 				break;
@@ -1533,8 +1537,18 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 			udelay(10);
 		}
 
-		if (i >= retries)
-			pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
+		if (i >= retries) {
+			pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
+			if (amdgpu_sriov_reg_indirect_mmhub(adev) ||
+					amdgpu_sriov_reg_indirect_gc(adev)) {
+				if (tmp & INTERFACE_NOT_ENABLED_FLAG)
+					pr_err("The interface is not eabled!\n");
+				if (tmp & WRONG_OPERATION_TYPE_FLAG)
+					pr_err("Wrong operation type!\n");
+				if (tmp & NOT_IN_RANGE_FLAG)
+					pr_err("The register is not in range!\n");
+			}
+		}
 	}
 
 	ret = readl(scratch_reg0);
-- 
2.32.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-07-20 10:22 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-07-15 12:14 [PATCH] drm/amdgpu: Add error message when programing registers fails Roy Sun
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2021-07-20  5:57 Roy Sun
2021-07-20 10:22 ` Zhou, Peng Ju
2021-07-13 11:14 Roy Sun

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