From: Christoph Hellwig <hch@lst.de> To: Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com>, Zhenyu Wang <zhenyuw@linux.intel.com>, Zhi Wang <zhi.a.wang@intel.com> Cc: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/21] drm/i915/gvt: remove the map_gfn_to_mfn and set_trap_area ops Date: Wed, 21 Jul 2021 17:53:40 +0200 [thread overview] Message-ID: <20210721155355.173183-7-hch@lst.de> (raw) In-Reply-To: <20210721155355.173183-1-hch@lst.de> The map_gfn_to_mfn and set_trap_area ops are never defined, so remove them and clean up code that depends on them in the callers. Signed-off-by: Christoph Hellwig <hch@lst.de> --- drivers/gpu/drm/i915/gvt/cfg_space.c | 89 ++++++---------------------- drivers/gpu/drm/i915/gvt/hypercall.h | 4 -- drivers/gpu/drm/i915/gvt/mpt.h | 44 -------------- 3 files changed, 17 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index b490e3db2e38..dad3a6054335 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -129,60 +129,16 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, return 0; } -static int map_aperture(struct intel_vgpu *vgpu, bool map) +static void map_aperture(struct intel_vgpu *vgpu, bool map) { - phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu); - unsigned long aperture_sz = vgpu_aperture_sz(vgpu); - u64 first_gfn; - u64 val; - int ret; - - if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) - return 0; - - val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2]; - if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) - val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); - else - val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); - - first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; - - ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, - aperture_pa >> PAGE_SHIFT, - aperture_sz >> PAGE_SHIFT, - map); - if (ret) - return ret; - - vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; - return 0; + if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; } -static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap) +static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap) { - u64 start, end; - u64 val; - int ret; - - if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) - return 0; - - val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0]; - if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) - start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); - else - start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); - - start &= ~GENMASK(3, 0); - end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1; - - ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap); - if (ret) - return ret; - - vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; - return 0; + if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; } static int emulate_pci_command_write(struct intel_vgpu *vgpu, @@ -191,26 +147,17 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, u8 old = vgpu_cfg_space(vgpu)[offset]; u8 new = *(u8 *)p_data; u8 changed = old ^ new; - int ret; vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); if (!(changed & PCI_COMMAND_MEMORY)) return 0; if (old & PCI_COMMAND_MEMORY) { - ret = trap_gttmmio(vgpu, false); - if (ret) - return ret; - ret = map_aperture(vgpu, false); - if (ret) - return ret; + trap_gttmmio(vgpu, false); + map_aperture(vgpu, false); } else { - ret = trap_gttmmio(vgpu, true); - if (ret) - return ret; - ret = map_aperture(vgpu, true); - if (ret) - return ret; + trap_gttmmio(vgpu, true); + map_aperture(vgpu, true); } return 0; @@ -230,13 +177,12 @@ static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, return 0; } -static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, +static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { u32 new = *(u32 *)(p_data); bool lo = IS_ALIGNED(offset, 8); u64 size; - int ret = 0; bool mmio_enabled = vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; @@ -259,14 +205,14 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, * Untrap the BAR, since guest hasn't configured a * valid GPA */ - ret = trap_gttmmio(vgpu, false); + trap_gttmmio(vgpu, false); break; case PCI_BASE_ADDRESS_2: case PCI_BASE_ADDRESS_3: size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); intel_vgpu_write_pci_bar(vgpu, offset, size >> (lo ? 0 : 32), lo); - ret = map_aperture(vgpu, false); + map_aperture(vgpu, false); break; default: /* Unimplemented BARs */ @@ -282,19 +228,18 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, */ trap_gttmmio(vgpu, false); intel_vgpu_write_pci_bar(vgpu, offset, new, lo); - ret = trap_gttmmio(vgpu, mmio_enabled); + trap_gttmmio(vgpu, mmio_enabled); break; case PCI_BASE_ADDRESS_2: case PCI_BASE_ADDRESS_3: map_aperture(vgpu, false); intel_vgpu_write_pci_bar(vgpu, offset, new, lo); - ret = map_aperture(vgpu, mmio_enabled); + map_aperture(vgpu, mmio_enabled); break; default: intel_vgpu_write_pci_bar(vgpu, offset, new, lo); } } - return ret; } /** @@ -336,8 +281,8 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) return -EINVAL; - return emulate_pci_bar_write(vgpu, offset, p_data, bytes); - + emulate_pci_bar_write(vgpu, offset, p_data, bytes); + break; case INTEL_GVT_PCI_SWSCI: if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) return -EINVAL; diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h index 395bce9633fa..f1a4926f6f1b 100644 --- a/drivers/gpu/drm/i915/gvt/hypercall.h +++ b/drivers/gpu/drm/i915/gvt/hypercall.h @@ -62,10 +62,6 @@ struct intel_gvt_mpt { int (*dma_pin_guest_page)(unsigned long handle, dma_addr_t dma_addr); - int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn, - unsigned long mfn, unsigned int nr, bool map); - int (*set_trap_area)(unsigned long handle, u64 start, u64 end, - bool map); int (*set_opregion)(void *vgpu); int (*set_edid)(void *vgpu, int port_num); int (*get_vfio_device)(void *vgpu); diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h index 0e3966e1fec8..bb0e9e71d13e 100644 --- a/drivers/gpu/drm/i915/gvt/mpt.h +++ b/drivers/gpu/drm/i915/gvt/mpt.h @@ -270,50 +270,6 @@ intel_gvt_hypervisor_dma_pin_guest_page(struct intel_vgpu *vgpu, return intel_gvt_host.mpt->dma_pin_guest_page(vgpu->handle, dma_addr); } -/** - * intel_gvt_hypervisor_map_gfn_to_mfn - map a GFN region to MFN - * @vgpu: a vGPU - * @gfn: guest PFN - * @mfn: host PFN - * @nr: amount of PFNs - * @map: map or unmap - * - * Returns: - * Zero on success, negative error code if failed. - */ -static inline int intel_gvt_hypervisor_map_gfn_to_mfn( - struct intel_vgpu *vgpu, unsigned long gfn, - unsigned long mfn, unsigned int nr, - bool map) -{ - /* a MPT implementation could have MMIO mapped elsewhere */ - if (!intel_gvt_host.mpt->map_gfn_to_mfn) - return 0; - - return intel_gvt_host.mpt->map_gfn_to_mfn(vgpu->handle, gfn, mfn, nr, - map); -} - -/** - * intel_gvt_hypervisor_set_trap_area - Trap a guest PA region - * @vgpu: a vGPU - * @start: the beginning of the guest physical address region - * @end: the end of the guest physical address region - * @map: map or unmap - * - * Returns: - * Zero on success, negative error code if failed. - */ -static inline int intel_gvt_hypervisor_set_trap_area( - struct intel_vgpu *vgpu, u64 start, u64 end, bool map) -{ - /* a MPT implementation could have MMIO trapped elsewhere */ - if (!intel_gvt_host.mpt->set_trap_area) - return 0; - - return intel_gvt_host.mpt->set_trap_area(vgpu->handle, start, end, map); -} - /** * intel_gvt_hypervisor_set_opregion - Set opregion for guest * @vgpu: a vGPU -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de> To: Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com>, Zhenyu Wang <zhenyuw@linux.intel.com>, Zhi Wang <zhi.a.wang@intel.com> Cc: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 06/21] drm/i915/gvt: remove the map_gfn_to_mfn and set_trap_area ops Date: Wed, 21 Jul 2021 17:53:40 +0200 [thread overview] Message-ID: <20210721155355.173183-7-hch@lst.de> (raw) In-Reply-To: <20210721155355.173183-1-hch@lst.de> The map_gfn_to_mfn and set_trap_area ops are never defined, so remove them and clean up code that depends on them in the callers. Signed-off-by: Christoph Hellwig <hch@lst.de> --- drivers/gpu/drm/i915/gvt/cfg_space.c | 89 ++++++---------------------- drivers/gpu/drm/i915/gvt/hypercall.h | 4 -- drivers/gpu/drm/i915/gvt/mpt.h | 44 -------------- 3 files changed, 17 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index b490e3db2e38..dad3a6054335 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -129,60 +129,16 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, return 0; } -static int map_aperture(struct intel_vgpu *vgpu, bool map) +static void map_aperture(struct intel_vgpu *vgpu, bool map) { - phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu); - unsigned long aperture_sz = vgpu_aperture_sz(vgpu); - u64 first_gfn; - u64 val; - int ret; - - if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) - return 0; - - val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2]; - if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) - val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); - else - val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); - - first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; - - ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, - aperture_pa >> PAGE_SHIFT, - aperture_sz >> PAGE_SHIFT, - map); - if (ret) - return ret; - - vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; - return 0; + if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; } -static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap) +static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap) { - u64 start, end; - u64 val; - int ret; - - if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) - return 0; - - val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0]; - if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) - start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); - else - start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); - - start &= ~GENMASK(3, 0); - end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1; - - ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap); - if (ret) - return ret; - - vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; - return 0; + if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; } static int emulate_pci_command_write(struct intel_vgpu *vgpu, @@ -191,26 +147,17 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, u8 old = vgpu_cfg_space(vgpu)[offset]; u8 new = *(u8 *)p_data; u8 changed = old ^ new; - int ret; vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); if (!(changed & PCI_COMMAND_MEMORY)) return 0; if (old & PCI_COMMAND_MEMORY) { - ret = trap_gttmmio(vgpu, false); - if (ret) - return ret; - ret = map_aperture(vgpu, false); - if (ret) - return ret; + trap_gttmmio(vgpu, false); + map_aperture(vgpu, false); } else { - ret = trap_gttmmio(vgpu, true); - if (ret) - return ret; - ret = map_aperture(vgpu, true); - if (ret) - return ret; + trap_gttmmio(vgpu, true); + map_aperture(vgpu, true); } return 0; @@ -230,13 +177,12 @@ static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, return 0; } -static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, +static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { u32 new = *(u32 *)(p_data); bool lo = IS_ALIGNED(offset, 8); u64 size; - int ret = 0; bool mmio_enabled = vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; @@ -259,14 +205,14 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, * Untrap the BAR, since guest hasn't configured a * valid GPA */ - ret = trap_gttmmio(vgpu, false); + trap_gttmmio(vgpu, false); break; case PCI_BASE_ADDRESS_2: case PCI_BASE_ADDRESS_3: size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); intel_vgpu_write_pci_bar(vgpu, offset, size >> (lo ? 0 : 32), lo); - ret = map_aperture(vgpu, false); + map_aperture(vgpu, false); break; default: /* Unimplemented BARs */ @@ -282,19 +228,18 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, */ trap_gttmmio(vgpu, false); intel_vgpu_write_pci_bar(vgpu, offset, new, lo); - ret = trap_gttmmio(vgpu, mmio_enabled); + trap_gttmmio(vgpu, mmio_enabled); break; case PCI_BASE_ADDRESS_2: case PCI_BASE_ADDRESS_3: map_aperture(vgpu, false); intel_vgpu_write_pci_bar(vgpu, offset, new, lo); - ret = map_aperture(vgpu, mmio_enabled); + map_aperture(vgpu, mmio_enabled); break; default: intel_vgpu_write_pci_bar(vgpu, offset, new, lo); } } - return ret; } /** @@ -336,8 +281,8 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) return -EINVAL; - return emulate_pci_bar_write(vgpu, offset, p_data, bytes); - + emulate_pci_bar_write(vgpu, offset, p_data, bytes); + break; case INTEL_GVT_PCI_SWSCI: if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) return -EINVAL; diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h index 395bce9633fa..f1a4926f6f1b 100644 --- a/drivers/gpu/drm/i915/gvt/hypercall.h +++ b/drivers/gpu/drm/i915/gvt/hypercall.h @@ -62,10 +62,6 @@ struct intel_gvt_mpt { int (*dma_pin_guest_page)(unsigned long handle, dma_addr_t dma_addr); - int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn, - unsigned long mfn, unsigned int nr, bool map); - int (*set_trap_area)(unsigned long handle, u64 start, u64 end, - bool map); int (*set_opregion)(void *vgpu); int (*set_edid)(void *vgpu, int port_num); int (*get_vfio_device)(void *vgpu); diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h index 0e3966e1fec8..bb0e9e71d13e 100644 --- a/drivers/gpu/drm/i915/gvt/mpt.h +++ b/drivers/gpu/drm/i915/gvt/mpt.h @@ -270,50 +270,6 @@ intel_gvt_hypervisor_dma_pin_guest_page(struct intel_vgpu *vgpu, return intel_gvt_host.mpt->dma_pin_guest_page(vgpu->handle, dma_addr); } -/** - * intel_gvt_hypervisor_map_gfn_to_mfn - map a GFN region to MFN - * @vgpu: a vGPU - * @gfn: guest PFN - * @mfn: host PFN - * @nr: amount of PFNs - * @map: map or unmap - * - * Returns: - * Zero on success, negative error code if failed. - */ -static inline int intel_gvt_hypervisor_map_gfn_to_mfn( - struct intel_vgpu *vgpu, unsigned long gfn, - unsigned long mfn, unsigned int nr, - bool map) -{ - /* a MPT implementation could have MMIO mapped elsewhere */ - if (!intel_gvt_host.mpt->map_gfn_to_mfn) - return 0; - - return intel_gvt_host.mpt->map_gfn_to_mfn(vgpu->handle, gfn, mfn, nr, - map); -} - -/** - * intel_gvt_hypervisor_set_trap_area - Trap a guest PA region - * @vgpu: a vGPU - * @start: the beginning of the guest physical address region - * @end: the end of the guest physical address region - * @map: map or unmap - * - * Returns: - * Zero on success, negative error code if failed. - */ -static inline int intel_gvt_hypervisor_set_trap_area( - struct intel_vgpu *vgpu, u64 start, u64 end, bool map) -{ - /* a MPT implementation could have MMIO trapped elsewhere */ - if (!intel_gvt_host.mpt->set_trap_area) - return 0; - - return intel_gvt_host.mpt->set_trap_area(vgpu->handle, start, end, map); -} - /** * intel_gvt_hypervisor_set_opregion - Set opregion for guest * @vgpu: a vGPU -- 2.30.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-21 15:56 UTC|newest] Thread overview: 156+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-21 15:53 refactor the i915 GVT support Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 01/21] drm/i915/gvt: integrate into the main Makefile Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-08-03 9:27 ` Zhenyu Wang 2021-08-03 9:27 ` [Intel-gfx] " Zhenyu Wang 2021-07-21 15:53 ` [PATCH 02/21] drm/i915/gvt: remove module refcounting in intel_gvt_{,un}register_hypervisor Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] [PATCH 02/21] drm/i915/gvt: remove module refcounting in intel_gvt_{, un}register_hypervisor Christoph Hellwig 2021-07-21 15:53 ` [PATCH 03/21] drm/i915/gvt: remove enum hypervisor_type Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 04/21] drm/i915/gvt: move the gvt code into kvmgt.ko Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-08-09 11:29 ` Joonas Lahtinen 2021-08-09 11:29 ` [Intel-gfx] " Joonas Lahtinen 2021-08-09 14:29 ` Christoph Hellwig 2021-08-09 14:29 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 05/21] drm/i915/gvt: remove intel_gvt_ops Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` Christoph Hellwig [this message] 2021-07-21 15:53 ` [Intel-gfx] [PATCH 06/21] drm/i915/gvt: remove the map_gfn_to_mfn and set_trap_area ops Christoph Hellwig 2021-07-21 15:53 ` [PATCH 07/21] drm/i915/gvt: remove the unused from_virt_to_mfn op Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 08/21] drm/i915/gvt: merge struct kvmgt_vdev into struct intel_vgpu Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 09/21] drm/i915/gvt: merge struct kvmgt_guest_info into strut intel_vgpu Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 10/21] drm/i915/gvt: remove vgpu->handle Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 11/21] drm/i915/gvt: devirtualize ->{read,write}_gpa Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] [PATCH 11/21] drm/i915/gvt: devirtualize ->{read, write}_gpa Christoph Hellwig 2021-07-21 15:53 ` [PATCH 12/21] drm/i915/gvt: devirtualize ->{get,put}_vfio_device Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] [PATCH 12/21] drm/i915/gvt: devirtualize ->{get, put}_vfio_device Christoph Hellwig 2021-07-21 15:53 ` [PATCH 13/21] drm/i915/gvt: devirtualize ->set_edid and ->set_opregion Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 14/21] drm/i915/gvt: devirtualize ->detach_vgpu Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 15/21] drm/i915/gvt: devirtualize ->inject_msi Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 16/21] drm/i915/gvt: devirtualize ->is_valid_gfn Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 17/21] drm/i915/gvt: devirtualize ->gfn_to_mfn Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 18/21] drm/i915/gvt: devirtualize ->{enable,disable}_page_track Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] [PATCH 18/21] drm/i915/gvt: devirtualize ->{enable, disable}_page_track Christoph Hellwig 2021-07-21 15:53 ` [PATCH 19/21] drm/i915/gvt: devirtualize ->dma_{,un}map_guest_page Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] [PATCH 19/21] drm/i915/gvt: devirtualize ->dma_{, un}map_guest_page Christoph Hellwig 2021-07-21 15:53 ` [PATCH 20/21] drm/i915/gvt: devirtualize dma_pin_guest_page Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 15:53 ` [PATCH 21/21] drm/i915/gvt: remove struct intel_gvt_mpt Christoph Hellwig 2021-07-21 15:53 ` [Intel-gfx] " Christoph Hellwig 2021-07-21 17:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/21] drm/i915/gvt: integrate into the main Makefile Patchwork 2021-07-21 17:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-21 18:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-21 21:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-22 9:45 ` refactor the i915 GVT support Zhenyu Wang 2021-07-22 9:45 ` [Intel-gfx] " Zhenyu Wang 2021-07-22 9:45 ` Zhenyu Wang 2021-07-22 12:55 ` Christoph Hellwig 2021-07-22 12:55 ` [Intel-gfx] " Christoph Hellwig 2021-07-22 10:49 ` Wang, Zhi A 2021-07-22 10:49 ` [Intel-gfx] " Wang, Zhi A 2021-07-22 10:49 ` Wang, Zhi A 2021-07-22 11:26 ` Gerd Hoffmann 2021-07-22 11:26 ` [Intel-gfx] " Gerd Hoffmann 2021-07-22 11:26 ` Gerd Hoffmann 2021-07-27 12:12 ` Jason Gunthorpe 2021-07-27 12:12 ` [Intel-gfx] " Jason Gunthorpe 2021-07-27 12:12 ` Jason Gunthorpe 2021-07-28 13:38 ` Wang, Zhi A 2021-07-28 13:38 ` [Intel-gfx] " Wang, Zhi A 2021-07-28 13:38 ` Wang, Zhi A 2021-07-28 13:43 ` Greg KH 2021-07-28 13:43 ` [Intel-gfx] " Greg KH 2021-07-28 13:43 ` Greg KH 2021-07-28 17:59 ` Jason Gunthorpe 2021-07-28 17:59 ` [Intel-gfx] " Jason Gunthorpe 2021-07-28 17:59 ` Jason Gunthorpe 2021-07-29 7:20 ` Christoph Hellwig 2021-07-29 7:20 ` [Intel-gfx] " Christoph Hellwig 2021-07-29 7:30 ` Daniel Vetter 2021-07-29 7:30 ` Daniel Vetter 2021-07-29 7:30 ` Daniel Vetter 2021-08-03 9:43 ` Zhenyu Wang 2021-08-03 9:43 ` [Intel-gfx] " Zhenyu Wang 2021-08-03 9:43 ` Zhenyu Wang 2021-08-03 14:30 ` Jason Gunthorpe 2021-08-03 14:30 ` [Intel-gfx] " Jason Gunthorpe 2021-08-03 14:30 ` Jason Gunthorpe 2021-08-04 5:26 ` Zhenyu Wang 2021-08-04 5:26 ` [Intel-gfx] " Zhenyu Wang 2021-08-04 5:26 ` Zhenyu Wang 2021-08-16 17:34 ` Christoph Hellwig 2021-08-16 17:34 ` [Intel-gfx] " Christoph Hellwig 2021-08-17 1:08 ` Zhenyu Wang 2021-08-17 1:08 ` [Intel-gfx] " Zhenyu Wang 2021-08-17 1:08 ` Zhenyu Wang 2021-08-17 5:22 ` Zhenyu Wang 2021-08-17 5:22 ` [Intel-gfx] " Zhenyu Wang 2021-08-17 5:22 ` Zhenyu Wang 2021-08-19 8:29 ` Zhenyu Wang 2021-08-19 8:29 ` [Intel-gfx] " Zhenyu Wang 2021-08-19 8:29 ` Zhenyu Wang 2021-08-19 14:43 ` Joonas Lahtinen 2021-08-19 14:43 ` [Intel-gfx] " Joonas Lahtinen 2021-08-19 14:43 ` Joonas Lahtinen 2021-08-26 6:04 ` Zhenyu Wang 2021-08-26 6:04 ` [Intel-gfx] " Zhenyu Wang 2021-08-26 6:04 ` Zhenyu Wang 2021-08-20 14:17 ` Christoph Hellwig 2021-08-20 14:17 ` [Intel-gfx] " Christoph Hellwig 2021-08-20 19:56 ` Luis Chamberlain 2021-08-20 19:56 ` [Intel-gfx] " Luis Chamberlain 2021-08-20 19:56 ` Luis Chamberlain 2021-08-26 6:12 ` Zhenyu Wang 2021-08-26 6:12 ` [Intel-gfx] " Zhenyu Wang 2021-08-26 6:12 ` Zhenyu Wang 2021-09-28 7:41 ` Wang, Zhi A 2021-09-28 7:41 ` [Intel-gfx] " Wang, Zhi A 2021-09-28 7:41 ` Wang, Zhi A 2021-09-28 14:00 ` Luis Chamberlain 2021-09-28 14:00 ` [Intel-gfx] " Luis Chamberlain 2021-09-28 14:00 ` Luis Chamberlain 2021-09-28 14:35 ` Wang, Zhi A 2021-09-28 14:35 ` [Intel-gfx] " Wang, Zhi A 2021-09-28 14:35 ` Wang, Zhi A 2021-09-28 15:05 ` Jason Gunthorpe 2021-09-28 15:05 ` [Intel-gfx] " Jason Gunthorpe 2021-09-28 15:05 ` Jason Gunthorpe 2021-09-29 18:27 ` Wang, Zhi A 2021-09-29 18:27 ` [Intel-gfx] " Wang, Zhi A 2021-09-29 18:27 ` Wang, Zhi A 2021-09-29 18:55 ` Jason Gunthorpe 2021-09-29 18:55 ` [Intel-gfx] " Jason Gunthorpe 2021-09-29 18:55 ` Jason Gunthorpe 2021-10-01 13:01 ` Wang, Zhi A 2021-10-01 13:01 ` Wang, Zhi A 2021-10-01 13:01 ` [Intel-gfx] " Wang, Zhi A 2021-10-05 7:33 ` Wang, Zhi A 2021-10-05 7:33 ` [Intel-gfx] " Wang, Zhi A 2021-09-30 5:24 ` Christoph Hellwig 2021-09-30 5:24 ` [Intel-gfx] " Christoph Hellwig 2021-08-26 6:08 ` Zhenyu Wang 2021-08-26 6:08 ` [Intel-gfx] " Zhenyu Wang 2021-08-26 6:08 ` Zhenyu Wang 2021-08-04 5:40 ` Christoph Hellwig 2021-08-04 5:40 ` [Intel-gfx] " Christoph Hellwig 2021-09-28 14:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor the i915 GVT support (rev2) Patchwork 2021-09-28 14:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-28 16:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-29 8:19 ` refactor the i915 GVT support Wang, Zhi A 2021-07-29 8:19 ` [Intel-gfx] " Wang, Zhi A 2021-07-29 8:19 ` Wang, Zhi A 2021-08-19 9:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2021-07-22 13:16 ` Greg KH 2021-07-22 13:16 ` [Intel-gfx] " Greg KH 2021-07-22 13:16 ` Greg KH
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