* [Intel-gfx] [PATCH i-g-t 0/1] Add tests for new hw info query
@ 2021-07-27 0:28 John.C.Harrison
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: John.C.Harrison @ 2021-07-27 0:28 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interfaces.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Rodrigo Vivi (1):
tests/i915/query: Query, parse and validate the hwconfig table
include/drm-uapi/i915_drm.h | 1 +
lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-07-27 0:28 [Intel-gfx] [PATCH i-g-t 0/1] Add tests for new hw info query John.C.Harrison
@ 2021-07-27 0:28 ` John.C.Harrison
2021-09-15 3:47 ` Matthew Brost
2021-07-27 1:34 ` [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info query Patchwork
2021-07-27 5:42 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: John.C.Harrison @ 2021-07-27 0:28 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX, Slawomir Milczarek
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the query API. So add a test for it as both an example of
how to fetch the table and to validate the contents as much as
possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
---
include/drm-uapi/i915_drm.h | 1 +
lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c3..5c34ab759 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2233,6 +2233,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_TABLE 5
/* Must be kept compact -- no holes and well documented */
/**
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000..c9961e6bd
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ __INTEL_HWCONFIG_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+};
+
+enum {
+ INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
+ INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
+ INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
+};
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 3c791b8ba..1802287e3 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -842,6 +843,170 @@ static void engines(int fd)
free(engines);
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
+ };
+ uint32_t *data, value;
+ int i = 0;
+ int len, j, max_words, table_size;
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ table_size = item.length;
+ igt_require(table_size > 0);
+
+ data = malloc(table_size);
+ igt_assert(data);
+ memset(data, 0, table_size);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_assert(item.length == table_size);
+ igt_info("Table size = %d bytes\n", table_size);
+ igt_assert(table_size > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = table_size / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == table_size);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
+
+ len = data[i + 1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
+
+ value = data[i + 2];
+ switch (data[i]) {
+ case INTEL_HWCONFIG_MEMORY_TYPE:
+ igt_assert(len == 1);
+ switch (value) {
+ case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
+ igt_info("LPDDR4\n");
+ break;
+ case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
+ igt_info("LPDDR5\n");
+ break;
+ default:
+ igt_assert(0);
+ }
+ break;
+
+ case INTEL_HWCONFIG_CACHE_TYPES:
+ igt_assert(len == 1);
+
+#define TEST_CACHE_TYPE(type) \
+ if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
+ value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
+ igt_info(#type); \
+ if (value) \
+ igt_info(", "); \
+ }
+
+ TEST_CACHE_TYPE(L3);
+ TEST_CACHE_TYPE(LLC);
+ TEST_CACHE_TYPE(EDRAM);
+#undef TEST_CACHE_TYPE
+
+ igt_assert(value == 0);
+ igt_info("\n");
+ break;
+
+ default:
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info("%d, ", data[j]);
+ igt_info("%d\n", data[j]);
+ }
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -911,6 +1076,9 @@ igt_main
engines(fd);
}
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info query
2021-07-27 0:28 [Intel-gfx] [PATCH i-g-t 0/1] Add tests for new hw info query John.C.Harrison
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2021-07-27 1:34 ` Patchwork
2021-07-27 5:42 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-07-27 1:34 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 2936 bytes --]
== Series Details ==
Series: Add tests for new hw info query
URL : https://patchwork.freedesktop.org/series/93038/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10399 -> IGTPW_6061
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/index.html
Known issues
------------
Here are the changes found in IGTPW_6061 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][3] ([fdo#109271]) +48 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@gem_exec_parallel@engines@userptr:
- fi-pnv-d510: [INCOMPLETE][4] ([i915#299]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/fi-pnv-d510/igt@gem_exec_parallel@engines@userptr.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/fi-pnv-d510/igt@gem_exec_parallel@engines@userptr.html
* igt@kms_flip@basic-flip-vs-dpms@a-dsi1:
- {fi-tgl-dsi}: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-dpms@a-dsi1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-dpms@a-dsi1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299
Participating hosts (39 -> 33)
------------------------------
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6151 -> IGTPW_6061
CI-20190529: 20190529
CI_DRM_10399: 669037414c99bf454019d7e2497fe29995e31e61 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6061: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/index.html
IGT_6151: c3170c2d3744521b8351a4b9c579792bc9a5f835 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@i915_query@hwconfig_table
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/index.html
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add tests for new hw info query
2021-07-27 0:28 [Intel-gfx] [PATCH i-g-t 0/1] Add tests for new hw info query John.C.Harrison
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2021-07-27 1:34 ` [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info query Patchwork
@ 2021-07-27 5:42 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-07-27 5:42 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
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== Series Details ==
Series: Add tests for new hw info query
URL : https://patchwork.freedesktop.org/series/93038/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10399_full -> IGTPW_6061_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_6061_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_6061_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_6061_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_query@hwconfig_table} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@i915_query@hwconfig_table.html
- shard-iclb: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb4/igt@i915_query@hwconfig_table.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-tglb7/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb6/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
New tests
---------
New tests have been introduced between CI_DRM_10399_full and IGTPW_6061_full:
### New IGT tests (1) ###
* igt@i915_query@hwconfig_table:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_6061_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-iclb2/igt@feature_discovery@psr2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb1/igt@feature_discovery@psr2.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#280])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb6/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#3063] / [i915#3648])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-tglb2/igt@gem_eio@unwedge-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2846])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk1/igt@gem_exec_fair@basic-deadline.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][16] ([i915#2842]) +5 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][17] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842]) +4 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-kbl: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-kbl4/igt@gem_exec_fair@basic-throttle@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#2190])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl6/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: NOTRUN -> [FAIL][24] ([i915#2428])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#1888] / [i915#307])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk1/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk7/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][27] ([i915#2658])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#768]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-kbl1/igt@gem_softpin@noreloc-s3.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl7/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#3297])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen7_exec_parse@basic-allocation:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109289])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb5/igt@gen7_exec_parse@basic-allocation.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109289]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb4/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@batch-without-end:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#2856])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: NOTRUN -> [FAIL][35] ([i915#454])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@gem-idle:
- shard-iclb: NOTRUN -> [SKIP][36] ([i915#579]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb5/igt@i915_pm_rpm@gem-idle.html
* igt@i915_pm_rpm@pm-caching:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#579]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb3/igt@i915_pm_rpm@pm-caching.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][38] ([i915#2782])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#1769])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#1769])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][41] -> [DMESG-WARN][42] ([i915#118] / [i915#95])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk3/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#110725] / [fdo#111614])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111614])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3777])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3777]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#111615]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#110723]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#2705])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][50] ([i915#2705])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb5/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109278]) +27 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3689]) +9 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][53] ([fdo#109271]) +394 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-snb7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271]) +188 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl1/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs.html
* igt@kms_chamelium@common-hpd-after-suspend:
- shard-glk: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk9/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +24 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +21 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl4/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109284] / [fdo#111827]) +10 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109278] / [i915#1149]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb3/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +6 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb6/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +22 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][63] ([i915#1319]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#3116])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb2/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109278] / [fdo#109279])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-random:
- shard-kbl: NOTRUN -> [FAIL][66] ([i915#3444])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
- shard-apl: [PASS][67] -> [FAIL][68] ([i915#3444])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#3319]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-onscreen:
- shard-tglb: NOTRUN -> [SKIP][70] ([fdo#109279] / [i915#3359]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x512-onscreen.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-tglb: NOTRUN -> [SKIP][71] ([fdo#111825]) +19 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109274] / [fdo#109278]) +5 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109274]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb2/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-kbl: NOTRUN -> [FAIL][74] ([i915#79])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][75] -> [DMESG-WARN][76] ([i915#180]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-glk: [PASS][77] -> [FAIL][78] ([i915#2546])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109280]) +20 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271]) +53 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_hdr@static-swap:
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#1187])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_hdr@static-swap.html
* igt@kms_invalid_dotclock:
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#110577])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb7/igt@kms_invalid_dotclock.html
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109310])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_invalid_dotclock.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#533])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl2/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
- shard-glk: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#533])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk1/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533]) +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265]) +5 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-glk: NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][89] ([fdo#108145] / [i915#265]) +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][90] ([i915#265])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#3536])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_lowres@pipe-b-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#3536]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-x.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#112054])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb5/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping:
- shard-iclb: [PASS][94] -> [DMESG-WARN][95] ([i915#1226])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-iclb4/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_properties@plane-properties-atomic:
- shard-tglb: [PASS][96] -> [DMESG-WARN][97] ([i915#2868]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-tglb6/igt@kms_properties@plane-properties-atomic.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb5/igt@kms_properties@plane-properties-atomic.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#658]) +4 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: NOTRUN -> [SKIP][99] ([i915#658]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
- shard-glk: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#658])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#2920]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#2920])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#658]) +3 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109441]) +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][105] -> [SKIP][106] ([fdo#109441]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-tglb: NOTRUN -> [FAIL][107] ([i915#132] / [i915#3467]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#3841])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb1/igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][109] ([fdo#109271]) +291 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl8/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2437]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl7/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2437])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-b-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][112] ([i915#2530]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb5/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
* igt@nouveau_crc@pipe-d-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][113] ([i915#2530]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb7/igt@nouveau_crc@pipe-d-ctx-flip-detection.html
- shard-iclb: NOTRUN -> [SKIP][114] ([fdo#109278] / [i915#2530]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb4/igt@nouveau_crc@pipe-d-ctx-flip-detection.html
* igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109291]) +4 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb2/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][116] ([fdo#109291]) +3 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb3/igt@prime_nv_pcopy@test3_1.html
* igt@sysfs_clients@fair-1:
- shard-kbl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#2994]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl4/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@fair-3:
- shard-tglb: NOTRUN -> [SKIP][118] ([i915#2994]) +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb5/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2994]) +2 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl2/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][120] ([i915#2842]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [FAIL][122] ([i915#2842]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-iclb2/igt@gem_exec_fair@basic-pace@bcs0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb8/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_schedule@u-independent@vecs0:
- shard-tglb: [FAIL][124] ([i915#3795]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-tglb2/igt@gem_exec_schedule@u-independent@vecs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-tglb6/igt@gem_exec_schedule@u-independent@vecs0.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [DMESG-WARN][126] ([i915#118] / [i915#95]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-glk9/igt@gem_exec_whisper@basic-fds-forked-all.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-glk3/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-iclb: [DMESG-WARN][128] ([i915#3621]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-iclb1/igt@kms_big_fb@linear-64bpp-rotate-180.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-iclb6/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][130] ([i915#180]) -> [PASS][131] +4 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: [DMESG-WARN][132] ([i915#180]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10399/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/shard-apl6/igt@kms_pipe_crc_basic@suspend-rea
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6061/index.html
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2021-09-15 3:47 ` Matthew Brost
0 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2021-09-15 3:47 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
On Mon, Jul 26, 2021 at 05:28:12PM -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the query API. So add a test for it as both an example of
> how to fetch the table and to validate the contents as much as
> possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 275 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index a1c0030c3..5c34ab759 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2233,6 +2233,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> /* Must be kept compact -- no holes and well documented */
>
> /**
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000..c9961e6bd
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,106 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + __INTEL_HWCONFIG_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
> + INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 3c791b8ba..1802287e3 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -842,6 +843,170 @@ static void engines(int fd)
> free(engines);
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + switch (value) {
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
> + igt_info("LPDDR4\n");
> + break;
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
> + igt_info("LPDDR5\n");
> + break;
> + default:
> + igt_assert(0);
> + }
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> +#define TEST_CACHE_TYPE(type) \
> + if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
> + value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
> + igt_info(#type); \
> + if (value) \
> + igt_info(", "); \
> + }
> +
> + TEST_CACHE_TYPE(L3);
> + TEST_CACHE_TYPE(LLC);
> + TEST_CACHE_TYPE(EDRAM);
> +#undef TEST_CACHE_TYPE
> +
> + igt_assert(value == 0);
> + igt_info("\n");
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +1076,9 @@ igt_main
> engines(fd);
> }
>
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
@ 2021-09-15 3:47 ` Matthew Brost
0 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2021-09-15 3:47 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
On Mon, Jul 26, 2021 at 05:28:12PM -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the query API. So add a test for it as both an example of
> how to fetch the table and to validate the contents as much as
> possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 275 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index a1c0030c3..5c34ab759 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2233,6 +2233,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> /* Must be kept compact -- no holes and well documented */
>
> /**
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000..c9961e6bd
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,106 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + __INTEL_HWCONFIG_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
> + INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 3c791b8ba..1802287e3 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -842,6 +843,170 @@ static void engines(int fd)
> free(engines);
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + switch (value) {
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
> + igt_info("LPDDR4\n");
> + break;
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
> + igt_info("LPDDR5\n");
> + break;
> + default:
> + igt_assert(0);
> + }
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> +#define TEST_CACHE_TYPE(type) \
> + if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
> + value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
> + igt_info(#type); \
> + if (value) \
> + igt_info(", "); \
> + }
> +
> + TEST_CACHE_TYPE(L3);
> + TEST_CACHE_TYPE(LLC);
> + TEST_CACHE_TYPE(EDRAM);
> +#undef TEST_CACHE_TYPE
> +
> + igt_assert(value == 0);
> + igt_info("\n");
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +1076,9 @@ igt_main
> engines(fd);
> }
>
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-09-15 3:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-27 0:28 [Intel-gfx] [PATCH i-g-t 0/1] Add tests for new hw info query John.C.Harrison
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2021-09-15 3:47 ` [Intel-gfx] [igt-dev] " Matthew Brost
2021-09-15 3:47 ` Matthew Brost
2021-07-27 1:34 ` [igt-dev] ✓ Fi.CI.BAT: success for Add tests for new hw info query Patchwork
2021-07-27 5:42 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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