* [PATCH] arm: dts: stm32mp15: alignment with v5.14
@ 2021-07-27 10:15 Patrick Delaunay
2021-08-02 12:41 ` Patrice CHOTARD
0 siblings, 1 reply; 3+ messages in thread
From: Patrick Delaunay @ 2021-07-27 10:15 UTC (permalink / raw)
To: u-boot
Cc: Patrick Delaunay, Christophe Kerello, Etienne Carriere,
Jagan Teki, Patrice Chotard, Tom Rini, uboot-stm32
Device tree alignment with Linux kernel v5.14-rc3
- ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15
- ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151
- ARM: dts: stm32: add a new DCMI pins group on stm32mp15
- ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
arch/arm/dts/stm32mp15-pinctrl.dtsi | 33 +++++++++++++++++++
arch/arm/dts/stm32mp151.dtsi | 16 ++++-----
...157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +-
3 files changed, 42 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 060baa8b7e..5b60ecbd71 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -118,6 +118,39 @@
};
};
+ dcmi_pins_b: dcmi-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_b: dcmi-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 177927d14e..8e0a0bc1dd 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1399,8 +1399,8 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
- <&mdma1 22 0x2 0x100008 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+ <&mdma1 22 0x2 0x10100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@@ -1446,12 +1446,6 @@
status = "disabled";
};
- stmmac_axi_config_0: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
@@ -1477,6 +1471,12 @@
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
+
+ stmmac_axi_config_0: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
};
usbh_ohci: usb@5800c000 {
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index 674b2d330d..5670b23812 100644
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -89,7 +89,7 @@
};
&pinctrl {
- ltdc_pins: ltdc {
+ ltdc_pins: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
<STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] arm: dts: stm32mp15: alignment with v5.14
2021-07-27 10:15 [PATCH] arm: dts: stm32mp15: alignment with v5.14 Patrick Delaunay
@ 2021-08-02 12:41 ` Patrice CHOTARD
2021-08-16 11:34 ` [Uboot-stm32] " Patrice CHOTARD
0 siblings, 1 reply; 3+ messages in thread
From: Patrice CHOTARD @ 2021-08-02 12:41 UTC (permalink / raw)
To: Patrick Delaunay, u-boot
Cc: Christophe Kerello, Etienne Carriere, Jagan Teki, Tom Rini, uboot-stm32
Hi Patrick
On 7/27/21 12:15 PM, Patrick Delaunay wrote:
> Device tree alignment with Linux kernel v5.14-rc3
> - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15
> - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151
> - ARM: dts: stm32: add a new DCMI pins group on stm32mp15
> - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
> ---
>
> arch/arm/dts/stm32mp15-pinctrl.dtsi | 33 +++++++++++++++++++
> arch/arm/dts/stm32mp151.dtsi | 16 ++++-----
> ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +-
> 3 files changed, 42 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
> index 060baa8b7e..5b60ecbd71 100644
> --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
> @@ -118,6 +118,39 @@
> };
> };
>
> + dcmi_pins_b: dcmi-1 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
> + bias-disable;
> + };
> + };
> +
> + dcmi_sleep_pins_b: dcmi-sleep-1 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
> + };
> + };
> +
> ethernet0_rgmii_pins_a: rgmii-0 {
> pins1 {
> pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
> diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
> index 177927d14e..8e0a0bc1dd 100644
> --- a/arch/arm/dts/stm32mp151.dtsi
> +++ b/arch/arm/dts/stm32mp151.dtsi
> @@ -1399,8 +1399,8 @@
> reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
> reg-names = "qspi", "qspi_mm";
> interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> - dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
> - <&mdma1 22 0x2 0x100008 0x0 0x0>;
> + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
> + <&mdma1 22 0x2 0x10100008 0x0 0x0>;
> dma-names = "tx", "rx";
> clocks = <&rcc QSPI_K>;
> resets = <&rcc QSPI_R>;
> @@ -1446,12 +1446,6 @@
> status = "disabled";
> };
>
> - stmmac_axi_config_0: stmmac-axi-config {
> - snps,wr_osr_lmt = <0x7>;
> - snps,rd_osr_lmt = <0x7>;
> - snps,blen = <0 0 0 0 16 8 4>;
> - };
> -
> ethernet0: ethernet@5800a000 {
> compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
> reg = <0x5800a000 0x2000>;
> @@ -1477,6 +1471,12 @@
> snps,axi-config = <&stmmac_axi_config_0>;
> snps,tso;
> status = "disabled";
> +
> + stmmac_axi_config_0: stmmac-axi-config {
> + snps,wr_osr_lmt = <0x7>;
> + snps,rd_osr_lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> };
>
> usbh_ohci: usb@5800c000 {
> diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> index 674b2d330d..5670b23812 100644
> --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> @@ -89,7 +89,7 @@
> };
>
> &pinctrl {
> - ltdc_pins: ltdc {
> + ltdc_pins: ltdc-0 {
> pins {
> pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
> <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Thanks
Patrice
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Uboot-stm32] [PATCH] arm: dts: stm32mp15: alignment with v5.14
2021-08-02 12:41 ` Patrice CHOTARD
@ 2021-08-16 11:34 ` Patrice CHOTARD
0 siblings, 0 replies; 3+ messages in thread
From: Patrice CHOTARD @ 2021-08-16 11:34 UTC (permalink / raw)
To: Patrick Delaunay, u-boot
Cc: Etienne Carriere, Tom Rini, uboot-stm32, Christophe Kerello, Jagan Teki
Hi Patrick
On 8/2/21 2:41 PM, Patrice CHOTARD wrote:
> Hi Patrick
>
> On 7/27/21 12:15 PM, Patrick Delaunay wrote:
>> Device tree alignment with Linux kernel v5.14-rc3
>> - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15
>> - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151
>> - ARM: dts: stm32: add a new DCMI pins group on stm32mp15
>> - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7
>>
>> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
>> ---
>>
>> arch/arm/dts/stm32mp15-pinctrl.dtsi | 33 +++++++++++++++++++
>> arch/arm/dts/stm32mp151.dtsi | 16 ++++-----
>> ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +-
>> 3 files changed, 42 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
>> index 060baa8b7e..5b60ecbd71 100644
>> --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
>> +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
>> @@ -118,6 +118,39 @@
>> };
>> };
>>
>> + dcmi_pins_b: dcmi-1 {
>> + pins {
>> + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
>> + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
>> + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
>> + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
>> + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
>> + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
>> + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
>> + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
>> + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
>> + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
>> + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
>> + bias-disable;
>> + };
>> + };
>> +
>> + dcmi_sleep_pins_b: dcmi-sleep-1 {
>> + pins {
>> + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
>> + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
>> + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
>> + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
>> + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
>> + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
>> + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
>> + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
>> + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
>> + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
>> + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
>> + };
>> + };
>> +
>> ethernet0_rgmii_pins_a: rgmii-0 {
>> pins1 {
>> pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
>> diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
>> index 177927d14e..8e0a0bc1dd 100644
>> --- a/arch/arm/dts/stm32mp151.dtsi
>> +++ b/arch/arm/dts/stm32mp151.dtsi
>> @@ -1399,8 +1399,8 @@
>> reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
>> reg-names = "qspi", "qspi_mm";
>> interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> - dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
>> - <&mdma1 22 0x2 0x100008 0x0 0x0>;
>> + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
>> + <&mdma1 22 0x2 0x10100008 0x0 0x0>;
>> dma-names = "tx", "rx";
>> clocks = <&rcc QSPI_K>;
>> resets = <&rcc QSPI_R>;
>> @@ -1446,12 +1446,6 @@
>> status = "disabled";
>> };
>>
>> - stmmac_axi_config_0: stmmac-axi-config {
>> - snps,wr_osr_lmt = <0x7>;
>> - snps,rd_osr_lmt = <0x7>;
>> - snps,blen = <0 0 0 0 16 8 4>;
>> - };
>> -
>> ethernet0: ethernet@5800a000 {
>> compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
>> reg = <0x5800a000 0x2000>;
>> @@ -1477,6 +1471,12 @@
>> snps,axi-config = <&stmmac_axi_config_0>;
>> snps,tso;
>> status = "disabled";
>> +
>> + stmmac_axi_config_0: stmmac-axi-config {
>> + snps,wr_osr_lmt = <0x7>;
>> + snps,rd_osr_lmt = <0x7>;
>> + snps,blen = <0 0 0 0 16 8 4>;
>> + };
>> };
>>
>> usbh_ohci: usb@5800c000 {
>> diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
>> index 674b2d330d..5670b23812 100644
>> --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
>> +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
>> @@ -89,7 +89,7 @@
>> };
>>
>> &pinctrl {
>> - ltdc_pins: ltdc {
>> + ltdc_pins: ltdc-0 {
>> pins {
>> pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
>> <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
>>
>
> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
>
> Thanks
> Patrice
> _______________________________________________
> Uboot-stm32 mailing list
> Uboot-stm32@st-md-mailman.stormreply.com
> https://st-md-mailman.stormreply.com/mailman/listinfo/uboot-stm32
>
Applied to u-boot-stm/master
Thanks
Patrice
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-08-16 11:34 UTC | newest]
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2021-07-27 10:15 [PATCH] arm: dts: stm32mp15: alignment with v5.14 Patrick Delaunay
2021-08-02 12:41 ` Patrice CHOTARD
2021-08-16 11:34 ` [Uboot-stm32] " Patrice CHOTARD
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