* [PATCH v11 1/5] arm64: mte: rename gcr_user_excl to mte_ctrl
2021-07-27 20:52 [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Peter Collingbourne
@ 2021-07-27 20:52 ` Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 2/5] arm64: mte: change ASYNC and SYNC TCF settings into bitfields Peter Collingbourne
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Peter Collingbourne @ 2021-07-27 20:52 UTC (permalink / raw)
To: Catalin Marinas, Vincenzo Frascino, Will Deacon
Cc: Peter Collingbourne, Evgenii Stepanov, Szabolcs Nagy,
Tejas Belagod, linux-arm-kernel, Greg Kroah-Hartman
We are going to use this field to store more data. To prepare for
that, rename it and change the users to rely on the bit position of
gcr_user_excl in mte_ctrl.
Link: https://linux-review.googlesource.com/id/Ie1fd18e480100655f5d22137f5b22f4f3a9f9e2e
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/processor.h | 5 ++++-
arch/arm64/kernel/asm-offsets.c | 2 +-
arch/arm64/kernel/entry.S | 4 ++--
arch/arm64/kernel/mte.c | 14 ++++++++------
4 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index b6517fd03d7b..54d34276fa91 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -16,6 +16,9 @@
*/
#define NET_IP_ALIGN 0
+#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
+#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
+
#ifndef __ASSEMBLY__
#include <linux/build_bug.h>
@@ -153,7 +156,7 @@ struct thread_struct {
#endif
#endif
#ifdef CONFIG_ARM64_MTE
- u64 gcr_user_excl;
+ u64 mte_ctrl;
#endif
u64 sctlr_user;
};
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index c85670692afa..551427ae8cc5 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -52,7 +52,7 @@ int main(void)
DEFINE(THREAD_KEYS_KERNEL, offsetof(struct task_struct, thread.keys_kernel));
#endif
#ifdef CONFIG_ARM64_MTE
- DEFINE(THREAD_GCR_EL1_USER, offsetof(struct task_struct, thread.gcr_user_excl));
+ DEFINE(THREAD_MTE_CTRL, offsetof(struct task_struct, thread.mte_ctrl));
#endif
BLANK();
DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 863d44f73028..40c3543de3bc 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -167,7 +167,7 @@ alternative_else_nop_endif
* the RRND (bit[16]) setting.
*/
mrs_s \tmp2, SYS_GCR_EL1
- bfi \tmp2, \tmp, #0, #16
+ bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
msr_s SYS_GCR_EL1, \tmp2
#endif
.endm
@@ -190,7 +190,7 @@ alternative_else_nop_endif
alternative_if_not ARM64_MTE
b 1f
alternative_else_nop_endif
- ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER]
+ ldr \tmp, [\tsk, #THREAD_MTE_CTRL]
mte_set_gcr \tmp, \tmp2
1:
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index 36f51b0e438a..a5269558210c 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -195,7 +195,7 @@ void mte_check_tfsr_el1(void)
static void set_gcr_el1_excl(u64 excl)
{
- current->thread.gcr_user_excl = excl;
+ current->thread.mte_ctrl = excl;
/*
* SYS_GCR_EL1 will be set to current->thread.gcr_user_excl value
@@ -260,8 +260,8 @@ void mte_suspend_exit(void)
long set_mte_ctrl(struct task_struct *task, unsigned long arg)
{
u64 sctlr = task->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK;
- u64 gcr_excl = ~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
- SYS_GCR_EL1_EXCL_MASK;
+ u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
+ SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT;
if (!system_supports_mte())
return 0;
@@ -282,10 +282,10 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg)
if (task != current) {
task->thread.sctlr_user = sctlr;
- task->thread.gcr_user_excl = gcr_excl;
+ task->thread.mte_ctrl = mte_ctrl;
} else {
set_task_sctlr_el1(sctlr);
- set_gcr_el1_excl(gcr_excl);
+ set_gcr_el1_excl(mte_ctrl);
}
return 0;
@@ -294,7 +294,9 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg)
long get_mte_ctrl(struct task_struct *task)
{
unsigned long ret;
- u64 incl = ~task->thread.gcr_user_excl & SYS_GCR_EL1_EXCL_MASK;
+ u64 mte_ctrl = task->thread.mte_ctrl;
+ u64 incl = (~mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
+ SYS_GCR_EL1_EXCL_MASK;
if (!system_supports_mte())
return 0;
--
2.32.0.432.gabb21c7263-goog
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v11 2/5] arm64: mte: change ASYNC and SYNC TCF settings into bitfields
2021-07-27 20:52 [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 1/5] arm64: mte: rename gcr_user_excl to mte_ctrl Peter Collingbourne
@ 2021-07-27 20:52 ` Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 3/5] arm64: move preemption disablement to prctl handlers Peter Collingbourne
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Peter Collingbourne @ 2021-07-27 20:52 UTC (permalink / raw)
To: Catalin Marinas, Vincenzo Frascino, Will Deacon
Cc: Peter Collingbourne, Evgenii Stepanov, Szabolcs Nagy,
Tejas Belagod, linux-arm-kernel, Greg Kroah-Hartman
Allow the user program to specify both ASYNC and SYNC TCF modes by
repurposing the existing constants as bitfields. This will allow the
kernel to select one of the modes on behalf of the user program. With
this patch the kernel will always select async mode, but a subsequent
patch will make this configurable.
Link: https://linux-review.googlesource.com/id/Icc5923c85a8ea284588cc399ae74fd19ec291230
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
v11:
- rebased to 5.14rc3
v9:
- make mte_update_sctlr_user static
arch/arm64/include/asm/processor.h | 3 ++
arch/arm64/kernel/mte.c | 70 ++++++++++++------------------
include/uapi/linux/prctl.h | 11 ++---
3 files changed, 37 insertions(+), 47 deletions(-)
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 54d34276fa91..ee82ebbb5e5a 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -19,6 +19,9 @@
#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
+#define MTE_CTRL_TCF_SYNC (1UL << 16)
+#define MTE_CTRL_TCF_ASYNC (1UL << 17)
+
#ifndef __ASSEMBLY__
#include <linux/build_bug.h>
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index a5269558210c..3b6b68518003 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -193,14 +193,19 @@ void mte_check_tfsr_el1(void)
}
#endif
-static void set_gcr_el1_excl(u64 excl)
+static void mte_update_sctlr_user(struct task_struct *task)
{
- current->thread.mte_ctrl = excl;
+ unsigned long sctlr = task->thread.sctlr_user;
+ unsigned long pref = MTE_CTRL_TCF_ASYNC;
+ unsigned long mte_ctrl = task->thread.mte_ctrl;
+ unsigned long resolved_mte_tcf = (mte_ctrl & pref) ? pref : mte_ctrl;
- /*
- * SYS_GCR_EL1 will be set to current->thread.gcr_user_excl value
- * by mte_set_user_gcr() in kernel_exit,
- */
+ sctlr &= ~SCTLR_EL1_TCF0_MASK;
+ if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC)
+ sctlr |= SCTLR_EL1_TCF0_ASYNC;
+ else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC)
+ sctlr |= SCTLR_EL1_TCF0_SYNC;
+ task->thread.sctlr_user = sctlr;
}
void mte_thread_init_user(void)
@@ -212,15 +217,16 @@ void mte_thread_init_user(void)
dsb(ish);
write_sysreg_s(0, SYS_TFSRE0_EL1);
clear_thread_flag(TIF_MTE_ASYNC_FAULT);
- /* disable tag checking */
- set_task_sctlr_el1((current->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK) |
- SCTLR_EL1_TCF0_NONE);
- /* reset tag generation mask */
- set_gcr_el1_excl(SYS_GCR_EL1_EXCL_MASK);
+ /* disable tag checking and reset tag generation mask */
+ current->thread.mte_ctrl = MTE_CTRL_GCR_USER_EXCL_MASK;
+ mte_update_sctlr_user(current);
+ set_task_sctlr_el1(current->thread.sctlr_user);
}
void mte_thread_switch(struct task_struct *next)
{
+ mte_update_sctlr_user(next);
+
/*
* Check if an async tag exception occurred at EL1.
*
@@ -259,33 +265,21 @@ void mte_suspend_exit(void)
long set_mte_ctrl(struct task_struct *task, unsigned long arg)
{
- u64 sctlr = task->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK;
u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT;
if (!system_supports_mte())
return 0;
- switch (arg & PR_MTE_TCF_MASK) {
- case PR_MTE_TCF_NONE:
- sctlr |= SCTLR_EL1_TCF0_NONE;
- break;
- case PR_MTE_TCF_SYNC:
- sctlr |= SCTLR_EL1_TCF0_SYNC;
- break;
- case PR_MTE_TCF_ASYNC:
- sctlr |= SCTLR_EL1_TCF0_ASYNC;
- break;
- default:
- return -EINVAL;
- }
+ if (arg & PR_MTE_TCF_ASYNC)
+ mte_ctrl |= MTE_CTRL_TCF_ASYNC;
+ if (arg & PR_MTE_TCF_SYNC)
+ mte_ctrl |= MTE_CTRL_TCF_SYNC;
- if (task != current) {
- task->thread.sctlr_user = sctlr;
- task->thread.mte_ctrl = mte_ctrl;
- } else {
- set_task_sctlr_el1(sctlr);
- set_gcr_el1_excl(mte_ctrl);
+ task->thread.mte_ctrl = mte_ctrl;
+ if (task == current) {
+ mte_update_sctlr_user(task);
+ set_task_sctlr_el1(task->thread.sctlr_user);
}
return 0;
@@ -302,18 +296,10 @@ long get_mte_ctrl(struct task_struct *task)
return 0;
ret = incl << PR_MTE_TAG_SHIFT;
-
- switch (task->thread.sctlr_user & SCTLR_EL1_TCF0_MASK) {
- case SCTLR_EL1_TCF0_NONE:
- ret |= PR_MTE_TCF_NONE;
- break;
- case SCTLR_EL1_TCF0_SYNC:
- ret |= PR_MTE_TCF_SYNC;
- break;
- case SCTLR_EL1_TCF0_ASYNC:
+ if (mte_ctrl & MTE_CTRL_TCF_ASYNC)
ret |= PR_MTE_TCF_ASYNC;
- break;
- }
+ if (mte_ctrl & MTE_CTRL_TCF_SYNC)
+ ret |= PR_MTE_TCF_SYNC;
return ret;
}
diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h
index 967d9c55323d..89de78a14b9b 100644
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@ -234,14 +234,15 @@ struct prctl_mm_map {
#define PR_GET_TAGGED_ADDR_CTRL 56
# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
/* MTE tag check fault modes */
-# define PR_MTE_TCF_SHIFT 1
-# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
-# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
-# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
-# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_NONE 0
+# define PR_MTE_TCF_SYNC (1UL << 1)
+# define PR_MTE_TCF_ASYNC (1UL << 2)
+# define PR_MTE_TCF_MASK (PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC)
/* MTE tag inclusion mask */
# define PR_MTE_TAG_SHIFT 3
# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
+/* Unused; kept only for source compatibility */
+# define PR_MTE_TCF_SHIFT 1
/* Control reclaim behavior when allocating memory */
#define PR_SET_IO_FLUSHER 57
--
2.32.0.432.gabb21c7263-goog
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v11 3/5] arm64: move preemption disablement to prctl handlers
2021-07-27 20:52 [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 1/5] arm64: mte: rename gcr_user_excl to mte_ctrl Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 2/5] arm64: mte: change ASYNC and SYNC TCF settings into bitfields Peter Collingbourne
@ 2021-07-27 20:52 ` Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 4/5] arm64: mte: introduce a per-CPU tag checking mode preference Peter Collingbourne
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Peter Collingbourne @ 2021-07-27 20:52 UTC (permalink / raw)
To: Catalin Marinas, Vincenzo Frascino, Will Deacon
Cc: Peter Collingbourne, Evgenii Stepanov, Szabolcs Nagy,
Tejas Belagod, linux-arm-kernel, Greg Kroah-Hartman
In the next patch, we will start reading sctlr_user from
mte_update_sctlr_user and subsequently writing a new value based on the
task's TCF setting and potentially the per-CPU TCF preference. This
means that we need to be careful to disable preemption around any
code sequences that read from sctlr_user and subsequently write to
sctlr_user and/or SCTLR_EL1, so that we don't end up writing a stale
value (based on the previous CPU's TCF preference) to either of them.
We currently have four such sequences, in the prctl handlers for
PR_SET_TAGGED_ADDR_CTRL and PR_PAC_SET_ENABLED_KEYS, as well as in
the task initialization code that resets the prctl settings. Change
the prctl handlers to disable preemption in the handlers themselves
rather than the functions that they call, and change the task
initialization code to call the respective prctl handlers instead of
setting sctlr_user directly.
As a result of this change, we no longer need the helper function
set_task_sctlr_el1, nor does its behavior make sense any more, so
remove it.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Link: https://linux-review.googlesource.com/id/Ic0e8a0c00bb47d786c1e8011df0b7fe99bee4bb5
---
arch/arm64/include/asm/pointer_auth.h | 12 ++++++------
arch/arm64/include/asm/processor.h | 2 +-
arch/arm64/kernel/mte.c | 8 ++++----
arch/arm64/kernel/pointer_auth.c | 10 ++++++----
arch/arm64/kernel/process.c | 21 +++++++--------------
5 files changed, 24 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/include/asm/pointer_auth.h b/arch/arm64/include/asm/pointer_auth.h
index 28a78b67d9b4..efb098de3a84 100644
--- a/arch/arm64/include/asm/pointer_auth.h
+++ b/arch/arm64/include/asm/pointer_auth.h
@@ -10,6 +10,9 @@
#include <asm/memory.h>
#include <asm/sysreg.h>
+#define PR_PAC_ENABLED_KEYS_MASK \
+ (PR_PAC_APIAKEY | PR_PAC_APIBKEY | PR_PAC_APDAKEY | PR_PAC_APDBKEY)
+
#ifdef CONFIG_ARM64_PTR_AUTH
/*
* Each key is a 128-bit quantity which is split across a pair of 64-bit
@@ -117,9 +120,9 @@ static __always_inline void ptrauth_enable(void)
\
/* enable all keys */ \
if (system_supports_address_auth()) \
- set_task_sctlr_el1(current->thread.sctlr_user | \
- SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \
- SCTLR_ELx_ENDA | SCTLR_ELx_ENDB); \
+ ptrauth_set_enabled_keys(current, \
+ PR_PAC_ENABLED_KEYS_MASK, \
+ PR_PAC_ENABLED_KEYS_MASK); \
} while (0)
#define ptrauth_thread_switch_user(tsk) \
@@ -146,7 +149,4 @@ static __always_inline void ptrauth_enable(void)
#define ptrauth_thread_switch_kernel(tsk)
#endif /* CONFIG_ARM64_PTR_AUTH_KERNEL */
-#define PR_PAC_ENABLED_KEYS_MASK \
- (PR_PAC_APIAKEY | PR_PAC_APIBKEY | PR_PAC_APDAKEY | PR_PAC_APDBKEY)
-
#endif /* __ASM_POINTER_AUTH_H */
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index ee82ebbb5e5a..ee2bdc1b9f5b 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -259,7 +259,7 @@ extern void release_thread(struct task_struct *);
unsigned long get_wchan(struct task_struct *p);
-void set_task_sctlr_el1(u64 sctlr);
+void update_sctlr_el1(u64 sctlr);
/* Thread switching */
extern struct task_struct *cpu_switch_to(struct task_struct *prev,
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index 3b6b68518003..737503a148bb 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -218,9 +218,7 @@ void mte_thread_init_user(void)
write_sysreg_s(0, SYS_TFSRE0_EL1);
clear_thread_flag(TIF_MTE_ASYNC_FAULT);
/* disable tag checking and reset tag generation mask */
- current->thread.mte_ctrl = MTE_CTRL_GCR_USER_EXCL_MASK;
- mte_update_sctlr_user(current);
- set_task_sctlr_el1(current->thread.sctlr_user);
+ set_mte_ctrl(current, 0);
}
void mte_thread_switch(struct task_struct *next)
@@ -278,8 +276,10 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg)
task->thread.mte_ctrl = mte_ctrl;
if (task == current) {
+ preempt_disable();
mte_update_sctlr_user(task);
- set_task_sctlr_el1(task->thread.sctlr_user);
+ update_sctlr_el1(task->thread.sctlr_user);
+ preempt_enable();
}
return 0;
diff --git a/arch/arm64/kernel/pointer_auth.c b/arch/arm64/kernel/pointer_auth.c
index 60901ab0a7fe..2708b620b4ae 100644
--- a/arch/arm64/kernel/pointer_auth.c
+++ b/arch/arm64/kernel/pointer_auth.c
@@ -67,7 +67,7 @@ static u64 arg_to_enxx_mask(unsigned long arg)
int ptrauth_set_enabled_keys(struct task_struct *tsk, unsigned long keys,
unsigned long enabled)
{
- u64 sctlr = tsk->thread.sctlr_user;
+ u64 sctlr;
if (!system_supports_address_auth())
return -EINVAL;
@@ -78,12 +78,14 @@ int ptrauth_set_enabled_keys(struct task_struct *tsk, unsigned long keys,
if ((keys & ~PR_PAC_ENABLED_KEYS_MASK) || (enabled & ~keys))
return -EINVAL;
+ preempt_disable();
+ sctlr = tsk->thread.sctlr_user;
sctlr &= ~arg_to_enxx_mask(keys);
sctlr |= arg_to_enxx_mask(enabled);
+ tsk->thread.sctlr_user = sctlr;
if (tsk == current)
- set_task_sctlr_el1(sctlr);
- else
- tsk->thread.sctlr_user = sctlr;
+ update_sctlr_el1(sctlr);
+ preempt_enable();
return 0;
}
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index c8989b999250..8811c303608b 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -477,7 +477,13 @@ static void compat_thread_switch(struct task_struct *next)
set_tsk_thread_flag(next, TIF_NOTIFY_RESUME);
}
-static void update_sctlr_el1(u64 sctlr)
+/*
+ * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
+ * this function must be called with preemption disabled and the update to
+ * sctlr_user must be made in the same preemption disabled block so that
+ * __switch_to() does not see the variable update before the SCTLR_EL1 one.
+ */
+void update_sctlr_el1(u64 sctlr)
{
/*
* EnIA must not be cleared while in the kernel as this is necessary for
@@ -489,19 +495,6 @@ static void update_sctlr_el1(u64 sctlr)
isb();
}
-void set_task_sctlr_el1(u64 sctlr)
-{
- /*
- * __switch_to() checks current->thread.sctlr as an
- * optimisation. Disable preemption so that it does not see
- * the variable update before the SCTLR_EL1 one.
- */
- preempt_disable();
- current->thread.sctlr_user = sctlr;
- update_sctlr_el1(sctlr);
- preempt_enable();
-}
-
/*
* Thread switching.
*/
--
2.32.0.432.gabb21c7263-goog
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v11 4/5] arm64: mte: introduce a per-CPU tag checking mode preference
2021-07-27 20:52 [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Peter Collingbourne
` (2 preceding siblings ...)
2021-07-27 20:52 ` [PATCH v11 3/5] arm64: move preemption disablement to prctl handlers Peter Collingbourne
@ 2021-07-27 20:52 ` Peter Collingbourne
2021-07-27 20:52 ` [PATCH v11 5/5] Documentation: document the preferred tag checking mode feature Peter Collingbourne
2021-07-28 17:46 ` [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Catalin Marinas
5 siblings, 0 replies; 9+ messages in thread
From: Peter Collingbourne @ 2021-07-27 20:52 UTC (permalink / raw)
To: Catalin Marinas, Vincenzo Frascino, Will Deacon
Cc: Peter Collingbourne, Evgenii Stepanov, Szabolcs Nagy,
Tejas Belagod, linux-arm-kernel, Greg Kroah-Hartman
Add a per-CPU sysfs node, mte_tcf_preferred, that allows the preferred
tag checking mode to be configured. The current possible values are
async and sync.
Link: https://linux-review.googlesource.com/id/I7493dcd533a2785a1437b16c3f6b50919f840854
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
v10:
- stop calling smp_call_function_single
arch/arm64/kernel/mte.c | 65 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 63 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index 737503a148bb..20a40e5a14fa 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -4,6 +4,7 @@
*/
#include <linux/bitops.h>
+#include <linux/cpu.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/prctl.h>
@@ -26,6 +27,8 @@ u64 gcr_kernel_excl __ro_after_init;
static bool report_fault_once = true;
+static DEFINE_PER_CPU_READ_MOSTLY(u64, mte_tcf_preferred);
+
#ifdef CONFIG_KASAN_HW_TAGS
/* Whether the MTE asynchronous mode is enabled. */
DEFINE_STATIC_KEY_FALSE(mte_async_mode);
@@ -195,11 +198,18 @@ void mte_check_tfsr_el1(void)
static void mte_update_sctlr_user(struct task_struct *task)
{
+ /*
+ * This must be called with preemption disabled and can only be called
+ * on the current or next task since the CPU must match where the thread
+ * is going to run. The caller is responsible for calling
+ * update_sctlr_el1() later in the same preemption disabled block.
+ */
unsigned long sctlr = task->thread.sctlr_user;
- unsigned long pref = MTE_CTRL_TCF_ASYNC;
unsigned long mte_ctrl = task->thread.mte_ctrl;
- unsigned long resolved_mte_tcf = (mte_ctrl & pref) ? pref : mte_ctrl;
+ unsigned long pref, resolved_mte_tcf;
+ pref = __this_cpu_read(mte_tcf_preferred);
+ resolved_mte_tcf = (mte_ctrl & pref) ? pref : mte_ctrl;
sctlr &= ~SCTLR_EL1_TCF0_MASK;
if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC)
sctlr |= SCTLR_EL1_TCF0_ASYNC;
@@ -438,3 +448,54 @@ int mte_ptrace_copy_tags(struct task_struct *child, long request,
return ret;
}
+
+static ssize_t mte_tcf_preferred_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ switch (per_cpu(mte_tcf_preferred, dev->id)) {
+ case MTE_CTRL_TCF_ASYNC:
+ return sysfs_emit(buf, "async\n");
+ case MTE_CTRL_TCF_SYNC:
+ return sysfs_emit(buf, "sync\n");
+ default:
+ return sysfs_emit(buf, "???\n");
+ }
+}
+
+static ssize_t mte_tcf_preferred_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u64 tcf;
+
+ if (sysfs_streq(buf, "async"))
+ tcf = MTE_CTRL_TCF_ASYNC;
+ else if (sysfs_streq(buf, "sync"))
+ tcf = MTE_CTRL_TCF_SYNC;
+ else
+ return -EINVAL;
+
+ device_lock(dev);
+ per_cpu(mte_tcf_preferred, dev->id) = tcf;
+ device_unlock(dev);
+
+ return count;
+}
+static DEVICE_ATTR_RW(mte_tcf_preferred);
+
+static int register_mte_tcf_preferred_sysctl(void)
+{
+ unsigned int cpu;
+
+ if (!system_supports_mte())
+ return 0;
+
+ for_each_possible_cpu(cpu) {
+ per_cpu(mte_tcf_preferred, cpu) = MTE_CTRL_TCF_ASYNC;
+ device_create_file(get_cpu_device(cpu),
+ &dev_attr_mte_tcf_preferred);
+ }
+
+ return 0;
+}
+subsys_initcall(register_mte_tcf_preferred_sysctl);
--
2.32.0.432.gabb21c7263-goog
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v11 5/5] Documentation: document the preferred tag checking mode feature
2021-07-27 20:52 [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Peter Collingbourne
` (3 preceding siblings ...)
2021-07-27 20:52 ` [PATCH v11 4/5] arm64: mte: introduce a per-CPU tag checking mode preference Peter Collingbourne
@ 2021-07-27 20:52 ` Peter Collingbourne
2021-07-28 6:11 ` Greg Kroah-Hartman
2021-07-28 17:46 ` [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Catalin Marinas
5 siblings, 1 reply; 9+ messages in thread
From: Peter Collingbourne @ 2021-07-27 20:52 UTC (permalink / raw)
To: Catalin Marinas, Vincenzo Frascino, Will Deacon
Cc: Peter Collingbourne, Evgenii Stepanov, Szabolcs Nagy,
Tejas Belagod, linux-arm-kernel, Greg Kroah-Hartman
Document the functionality added in the previous patches.
Link: https://linux-review.googlesource.com/id/I48217cc3e8b8da33abc08cbaddc11cf4360a1b86
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will@kernel.org>
---
v10:
- document that setting the sysfs node may not take effect
immediately
- unabbreviate month name
v9:
- add documentation for sysfs node under Documentation/ABI
.../ABI/testing/sysfs-devices-system-cpu | 18 +++++++
.../arm64/memory-tagging-extension.rst | 48 ++++++++++++++++---
2 files changed, 59 insertions(+), 7 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 160b10c029c0..5f87b146deb9 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -640,3 +640,21 @@ Description: SPURR ticks for cpuX when it was idle.
This sysfs interface exposes the number of SPURR ticks
for cpuX when it was idle.
+
+What: /sys/devices/system/cpu/cpuX/mte_tcf_preferred
+Date: July 2021
+Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
+Description: Preferred MTE tag checking mode
+
+ When a user program specifies more than one MTE tag checking
+ mode, this sysfs node is used to specify which mode should
+ be preferred when running on that CPU. Possible values:
+
+ ================ ==============================================
+ "sync" Prefer synchronous mode
+ "async" Prefer asynchronous mode
+ ================ ==============================================
+
+ Changes to this sysfs node may not take effect immediately.
+
+ See also: Documentation/arm64/memory-tagging-extension.rst
diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arm64/memory-tagging-extension.rst
index b540178a93f8..7b99c8f428eb 100644
--- a/Documentation/arm64/memory-tagging-extension.rst
+++ b/Documentation/arm64/memory-tagging-extension.rst
@@ -77,14 +77,20 @@ configurable behaviours:
address is unknown).
The user can select the above modes, per thread, using the
-``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where
-``flags`` contain one of the following values in the ``PR_MTE_TCF_MASK``
+``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where ``flags``
+contains any number of the following values in the ``PR_MTE_TCF_MASK``
bit-field:
-- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
+- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
+ (ignored if combined with other options)
- ``PR_MTE_TCF_SYNC`` - *Synchronous* tag check fault mode
- ``PR_MTE_TCF_ASYNC`` - *Asynchronous* tag check fault mode
+If no modes are specified, tag check faults are ignored. If a single
+mode is specified, the program will run in that mode. If multiple
+modes are specified, the mode is selected as described in the "Per-CPU
+preferred tag checking modes" section below.
+
The current tag check fault mode can be read using the
``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call.
@@ -120,13 +126,39 @@ in the ``PR_MTE_TAG_MASK`` bit-field.
interface provides an include mask. An include mask of ``0`` (exclusion
mask ``0xffff``) results in the CPU always generating tag ``0``.
+Per-CPU preferred tag checking mode
+-----------------------------------
+
+On some CPUs the performance of MTE in stricter tag checking modes
+is similar to that of less strict tag checking modes. This makes it
+worthwhile to enable stricter checks on those CPUs when a less strict
+checking mode is requested, in order to gain the error detection
+benefits of the stricter checks without the performance downsides. To
+support this scenario, a privileged user may configure a stricter
+tag checking mode as the CPU's preferred tag checking mode.
+
+The preferred tag checking mode for each CPU is controlled by
+``/sys/devices/system/cpu/cpu<N>/mte_tcf_preferred``, to which a
+privileged user may write the value ``async`` or ``sync``. The default
+preferred mode for each CPU is ``async``.
+
+To allow a program to potentially run in the CPU's preferred tag
+checking mode, the user program may set multiple tag check fault mode
+bits in the ``flags`` argument to the ``prctl(PR_SET_TAGGED_ADDR_CTRL,
+flags, 0, 0, 0)`` system call. If the CPU's preferred tag checking
+mode is in the task's set of provided tag checking modes (this will
+always be the case at present because the kernel only supports two
+tag checking modes, but future kernels may support more modes), that
+mode will be selected. Otherwise, one of the modes in the task's mode
+set will be selected in a currently unspecified manner.
+
Initial process state
---------------------
On ``execve()``, the new process has the following configuration:
- ``PR_TAGGED_ADDR_ENABLE`` set to 0 (disabled)
-- Tag checking mode set to ``PR_MTE_TCF_NONE``
+- No tag checking modes are selected (tag check faults ignored)
- ``PR_MTE_TAG_MASK`` set to 0 (all tags excluded)
- ``PSTATE.TCO`` set to 0
- ``PROT_MTE`` not set on any of the initial memory maps
@@ -251,11 +283,13 @@ Example of correct usage
return EXIT_FAILURE;
/*
- * Enable the tagged address ABI, synchronous MTE tag check faults and
- * allow all non-zero tags in the randomly generated set.
+ * Enable the tagged address ABI, synchronous or asynchronous MTE
+ * tag check faults (based on per-CPU preference) and allow all
+ * non-zero tags in the randomly generated set.
*/
if (prctl(PR_SET_TAGGED_ADDR_CTRL,
- PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | (0xfffe << PR_MTE_TAG_SHIFT),
+ PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC |
+ (0xfffe << PR_MTE_TAG_SHIFT),
0, 0, 0)) {
perror("prctl() failed");
return EXIT_FAILURE;
--
2.32.0.432.gabb21c7263-goog
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v11 5/5] Documentation: document the preferred tag checking mode feature
2021-07-27 20:52 ` [PATCH v11 5/5] Documentation: document the preferred tag checking mode feature Peter Collingbourne
@ 2021-07-28 6:11 ` Greg Kroah-Hartman
2021-07-28 17:38 ` Catalin Marinas
0 siblings, 1 reply; 9+ messages in thread
From: Greg Kroah-Hartman @ 2021-07-28 6:11 UTC (permalink / raw)
To: Peter Collingbourne
Cc: Catalin Marinas, Vincenzo Frascino, Will Deacon,
Evgenii Stepanov, Szabolcs Nagy, Tejas Belagod, linux-arm-kernel
On Tue, Jul 27, 2021 at 01:52:59PM -0700, Peter Collingbourne wrote:
> Document the functionality added in the previous patches.
>
> Link: https://linux-review.googlesource.com/id/I48217cc3e8b8da33abc08cbaddc11cf4360a1b86
> Signed-off-by: Peter Collingbourne <pcc@google.com>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> Acked-by: Will Deacon <will@kernel.org>
> ---
> v10:
> - document that setting the sysfs node may not take effect
> immediately
> - unabbreviate month name
>
> v9:
> - add documentation for sysfs node under Documentation/ABI
>
> .../ABI/testing/sysfs-devices-system-cpu | 18 +++++++
> .../arm64/memory-tagging-extension.rst | 48 ++++++++++++++++---
> 2 files changed, 59 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
> index 160b10c029c0..5f87b146deb9 100644
> --- a/Documentation/ABI/testing/sysfs-devices-system-cpu
> +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
> @@ -640,3 +640,21 @@ Description: SPURR ticks for cpuX when it was idle.
>
> This sysfs interface exposes the number of SPURR ticks
> for cpuX when it was idle.
> +
> +What: /sys/devices/system/cpu/cpuX/mte_tcf_preferred
> +Date: July 2021
> +Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
> +Description: Preferred MTE tag checking mode
> +
> + When a user program specifies more than one MTE tag checking
> + mode, this sysfs node is used to specify which mode should
> + be preferred when running on that CPU. Possible values:
> +
> + ================ ==============================================
> + "sync" Prefer synchronous mode
> + "async" Prefer asynchronous mode
> + ================ ==============================================
> +
> + Changes to this sysfs node may not take effect immediately.
Ok, so when do they take effect? A hint would be nice :)
thanks,
greg k-h
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v11 5/5] Documentation: document the preferred tag checking mode feature
2021-07-28 6:11 ` Greg Kroah-Hartman
@ 2021-07-28 17:38 ` Catalin Marinas
0 siblings, 0 replies; 9+ messages in thread
From: Catalin Marinas @ 2021-07-28 17:38 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Peter Collingbourne, Vincenzo Frascino, Will Deacon,
Evgenii Stepanov, Szabolcs Nagy, Tejas Belagod, linux-arm-kernel
On Wed, Jul 28, 2021 at 08:11:00AM +0200, Greg Kroah-Hartman wrote:
> On Tue, Jul 27, 2021 at 01:52:59PM -0700, Peter Collingbourne wrote:
> > diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
> > index 160b10c029c0..5f87b146deb9 100644
> > --- a/Documentation/ABI/testing/sysfs-devices-system-cpu
> > +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
> > @@ -640,3 +640,21 @@ Description: SPURR ticks for cpuX when it was idle.
> >
> > This sysfs interface exposes the number of SPURR ticks
> > for cpuX when it was idle.
> > +
> > +What: /sys/devices/system/cpu/cpuX/mte_tcf_preferred
> > +Date: July 2021
> > +Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
> > +Description: Preferred MTE tag checking mode
> > +
> > + When a user program specifies more than one MTE tag checking
> > + mode, this sysfs node is used to specify which mode should
> > + be preferred when running on that CPU. Possible values:
> > +
> > + ================ ==============================================
> > + "sync" Prefer synchronous mode
> > + "async" Prefer asynchronous mode
> > + ================ ==============================================
> > +
> > + Changes to this sysfs node may not take effect immediately.
>
> Ok, so when do they take effect? A hint would be nice :)
I'll go with Will suggestion below and remove this line altogether (it
takes effect when scheduling a task on a CPU):
https://lore.kernel.org/r/20210714115018.GE31686@willie-the-truck
--
Catalin
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis
2021-07-27 20:52 [PATCH v11 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Peter Collingbourne
` (4 preceding siblings ...)
2021-07-27 20:52 ` [PATCH v11 5/5] Documentation: document the preferred tag checking mode feature Peter Collingbourne
@ 2021-07-28 17:46 ` Catalin Marinas
5 siblings, 0 replies; 9+ messages in thread
From: Catalin Marinas @ 2021-07-28 17:46 UTC (permalink / raw)
To: Vincenzo Frascino, Peter Collingbourne, Will Deacon
Cc: Greg Kroah-Hartman, Szabolcs Nagy, linux-arm-kernel,
Tejas Belagod, Evgenii Stepanov
On Tue, 27 Jul 2021 13:52:54 -0700, Peter Collingbourne wrote:
> On some CPUs the performance of MTE in synchronous mode is similar
> to that of asynchronous mode. This makes it worthwhile to enable
> synchronous mode on those CPUs when asynchronous mode is requested,
> in order to gain the error detection benefits of synchronous mode
> without the performance downsides. Therefore, make it possible for
> user programs to opt into upgrading to synchronous mode on those CPUs.
>
> [...]
Applied to arm64 (for-next/mte) but first added Will's acks from v10 an
changed the Documentation/ patch to state "when scheduling" instead of
"when running". Thanks!
[1/5] arm64: mte: rename gcr_user_excl to mte_ctrl
https://git.kernel.org/arm64/c/638982a03fbc
[2/5] arm64: mte: change ASYNC and SYNC TCF settings into bitfields
https://git.kernel.org/arm64/c/433c38f40f6a
[3/5] arm64: move preemption disablement to prctl handlers
https://git.kernel.org/arm64/c/d2e0d8f9746d
[4/5] arm64: mte: introduce a per-CPU tag checking mode preference
https://git.kernel.org/arm64/c/dd061616edcf
[5/5] Documentation: document the preferred tag checking mode feature
https://git.kernel.org/arm64/c/80c7c36fb3dd
--
Catalin
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^ permalink raw reply [flat|nested] 9+ messages in thread