From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Matthew Brost <matthew.brost@intel.com>, Vinay Belgaumkar <vinay.belgaumkar@intel.com> Subject: [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Date: Wed, 28 Jul 2021 14:11:40 -0700 [thread overview] Message-ID: <20210728211144.15322-11-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210728211144.15322-1-vinay.belgaumkar@intel.com> This interrupt is enabled during RPS initialization, and now needs to be done by SLPC code. It allows ARAT timer expiry interrupts to get forwarded to GuC. v2: Fix comment (Matthew Brost) Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 ++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index 2643d207009b..742918875593 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -403,6 +403,21 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val) return ret; } +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt) +{ + u32 pm_intrmsk_mbz = 0; + + /* + * Allow GuC to receive ARAT timer expiry event. + * This interrupt register is setup by RPS code + * when host based Turbo is enabled. + */ + pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; + + intel_uncore_rmw(gt->uncore, + GEN6_PMINTRMSK, pm_intrmsk_mbz, 0); +} + /* * intel_guc_slpc_enable() - Start SLPC * @slpc: pointer to intel_guc_slpc. @@ -436,6 +451,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) if (unlikely(ret < 0)) return ret; + intel_guc_pm_intrmsk_enable(&i915->gt); + return 0; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h index 3ffd4f2e3151..e45054d5b9b4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -9,6 +9,7 @@ #include "intel_guc_submission.h" #include "intel_guc_slpc_types.h" +struct intel_gt; struct drm_printer; static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc) @@ -36,5 +37,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val); int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val); int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val); int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p); +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt); #endif diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 3e0cd1f05e3b..b104fb7607eb 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -655,6 +655,7 @@ void intel_uc_suspend(struct intel_uc *uc) static int __uc_resume(struct intel_uc *uc, bool enable_communication) { struct intel_guc *guc = &uc->guc; + struct intel_gt *gt = guc_to_gt(guc); int err; if (!intel_guc_is_fw_running(guc)) @@ -666,6 +667,13 @@ static int __uc_resume(struct intel_uc *uc, bool enable_communication) if (enable_communication) guc_enable_communication(guc); + /* If we are only resuming GuC communication but not reloading + * GuC, we need to ensure the ARAT timer interrupt is enabled + * again. In case of GuC reload, it is enabled during SLPC enable. + */ + if (enable_communication && intel_uc_uses_guc_slpc(uc)) + intel_guc_pm_intrmsk_enable(gt); + err = intel_guc_resume(guc); if (err) { DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err); -- 2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Date: Wed, 28 Jul 2021 14:11:40 -0700 [thread overview] Message-ID: <20210728211144.15322-11-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210728211144.15322-1-vinay.belgaumkar@intel.com> This interrupt is enabled during RPS initialization, and now needs to be done by SLPC code. It allows ARAT timer expiry interrupts to get forwarded to GuC. v2: Fix comment (Matthew Brost) Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 ++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index 2643d207009b..742918875593 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -403,6 +403,21 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val) return ret; } +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt) +{ + u32 pm_intrmsk_mbz = 0; + + /* + * Allow GuC to receive ARAT timer expiry event. + * This interrupt register is setup by RPS code + * when host based Turbo is enabled. + */ + pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; + + intel_uncore_rmw(gt->uncore, + GEN6_PMINTRMSK, pm_intrmsk_mbz, 0); +} + /* * intel_guc_slpc_enable() - Start SLPC * @slpc: pointer to intel_guc_slpc. @@ -436,6 +451,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) if (unlikely(ret < 0)) return ret; + intel_guc_pm_intrmsk_enable(&i915->gt); + return 0; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h index 3ffd4f2e3151..e45054d5b9b4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -9,6 +9,7 @@ #include "intel_guc_submission.h" #include "intel_guc_slpc_types.h" +struct intel_gt; struct drm_printer; static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc) @@ -36,5 +37,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val); int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val); int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val); int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p); +void intel_guc_pm_intrmsk_enable(struct intel_gt *gt); #endif diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 3e0cd1f05e3b..b104fb7607eb 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -655,6 +655,7 @@ void intel_uc_suspend(struct intel_uc *uc) static int __uc_resume(struct intel_uc *uc, bool enable_communication) { struct intel_guc *guc = &uc->guc; + struct intel_gt *gt = guc_to_gt(guc); int err; if (!intel_guc_is_fw_running(guc)) @@ -666,6 +667,13 @@ static int __uc_resume(struct intel_uc *uc, bool enable_communication) if (enable_communication) guc_enable_communication(guc); + /* If we are only resuming GuC communication but not reloading + * GuC, we need to ensure the ARAT timer interrupt is enabled + * again. In case of GuC reload, it is enabled during SLPC enable. + */ + if (enable_communication && intel_uc_uses_guc_slpc(uc)) + intel_guc_pm_intrmsk_enable(gt); + err = intel_guc_resume(guc); if (err) { DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err); -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-28 21:12 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-28 21:11 [PATCH v4 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 01/14] drm/i915/guc/slpc: Initial definitions for SLPC Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 15:28 ` Michal Wajdeczko 2021-07-29 15:28 ` [Intel-gfx] " Michal Wajdeczko 2021-07-28 21:11 ` [PATCH 02/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 03/14] drm/i915/guc/slpc: Adding SLPC communication interfaces Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 15:33 ` Michal Wajdeczko 2021-07-29 15:33 ` [Intel-gfx] " Michal Wajdeczko 2021-07-28 21:11 ` [PATCH 04/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 15:48 ` Michal Wajdeczko 2021-07-29 15:48 ` [Intel-gfx] " Michal Wajdeczko 2021-07-28 21:11 ` [PATCH 06/14] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 16:33 ` Michal Wajdeczko 2021-07-29 16:33 ` Michal Wajdeczko 2021-07-28 21:11 ` [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 21:11 ` Vinay Belgaumkar [this message] 2021-07-28 21:11 ` [Intel-gfx] [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 16:21 ` Michal Wajdeczko 2021-07-29 16:21 ` Michal Wajdeczko 2021-07-29 17:24 ` Belgaumkar, Vinay 2021-07-29 17:24 ` Belgaumkar, Vinay 2021-07-28 21:11 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 20:28 ` Michal Wajdeczko 2021-07-29 20:28 ` [Intel-gfx] " Michal Wajdeczko 2021-07-28 21:11 ` [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-29 23:40 ` Matthew Brost 2021-07-29 23:40 ` Matthew Brost 2021-07-30 1:12 ` Belgaumkar, Vinay 2021-07-30 1:12 ` Belgaumkar, Vinay 2021-07-30 1:45 ` kernel test robot 2021-07-30 1:45 ` kernel test robot 2021-07-30 1:45 ` kernel test robot 2021-07-28 21:11 ` [PATCH 14/14] drm/i915/guc/rc: Setup and enable GuCRC feature Vinay Belgaumkar 2021-07-28 21:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-28 22:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc/slpc: Enable GuC based power management features (rev2) Patchwork 2021-07-28 22:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-28 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-29 4:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2021-07-30 20:21 [PATCH v6 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar 2021-07-30 20:21 ` [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-30 2:00 [PATCH v5 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar 2021-07-30 2:01 ` [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-21 16:11 [PATCH v2 00/14] drm/i915/guc: Enable GuC based power management features Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar
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