* [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E
@ 2021-07-31 14:41 Philippe Mathieu-Daudé
2021-08-02 9:25 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-31 14:41 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Per the "Godson-2E User Manual v0.6", the Loongson 2E processor
does not implement the MOVZ/MOVN instructions
However it's enhanced version, the STLS2F01 processor, does.
See STLS2F01 User Manual (rev 1), chapter 13.1 "The compliance
overview":
The STLS2F01 processor implements several special MIPS IV
instructions as the supplement to the MIPS III instructions.
These instructions include two MIPS IV instructions (i.e. MOVZ
and MOVNZ) ...
Fixes: aa8f40090ab ("target-mips: enable movn/movz on loongson 2E & 2F")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index bf71724f3f0..34a96159d15 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -14156,8 +14156,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
- INSN_LOONGSON2E | INSN_LOONGSON2F);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E
2021-07-31 14:41 [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E Philippe Mathieu-Daudé
@ 2021-08-02 9:25 ` Philippe Mathieu-Daudé
2021-08-02 12:18 ` Maciej W. Rozycki
0 siblings, 1 reply; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-02 9:25 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Song Gao,
yangxiaojuan, Mark Shinwell, Aurelien Jarno, Maciej W. Rozycki
On 7/31/21 4:41 PM, Philippe Mathieu-Daudé wrote:
> Per the "Godson-2E User Manual v0.6", the Loongson 2E processor
> does not implement the MOVZ/MOVN instructions
I'm confused because I can't find MOVZ/MOVN in the 2E manual and
the 2F explicits the difference. However looking at binutils,
these opcodes are also emited on the 2E:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=350cc38db21f1cd651a6d46687542a0fce5e0303;hp=569502941afa825c5278b320ccedeefc82e8ed0e
Cc'ing Mark & Maciej in case they can enlighten me, and few
Loongson develeper in case they could check, because I don't
have 2E hardware to test.
> However it's enhanced version, the STLS2F01 processor, does.
> See STLS2F01 User Manual (rev 1), chapter 13.1 "The compliance
> overview":
>
> The STLS2F01 processor implements several special MIPS IV
> instructions as the supplement to the MIPS III instructions.
> These instructions include two MIPS IV instructions (i.e. MOVZ
> and MOVNZ) ...
>
> Fixes: aa8f40090ab ("target-mips: enable movn/movz on loongson 2E & 2F")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/tcg/translate.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index bf71724f3f0..34a96159d15 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -14156,8 +14156,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
> switch (op1) {
> case OPC_MOVN: /* Conditional move */
> case OPC_MOVZ:
> - check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
> - INSN_LOONGSON2E | INSN_LOONGSON2F);
> + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2F);
> gen_cond_move(ctx, op1, rd, rs, rt);
> break;
> case OPC_MFHI: /* Move from HI/LO */
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E
2021-08-02 9:25 ` Philippe Mathieu-Daudé
@ 2021-08-02 12:18 ` Maciej W. Rozycki
2021-08-02 13:17 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 5+ messages in thread
From: Maciej W. Rozycki @ 2021-08-02 12:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, qemu-devel,
yangxiaojuan, Song Gao, Mark Shinwell, Aurelien Jarno
On Mon, 2 Aug 2021, Philippe Mathieu-Daudé wrote:
> > Per the "Godson-2E User Manual v0.6", the Loongson 2E processor
> > does not implement the MOVZ/MOVN instructions
>
> I'm confused because I can't find MOVZ/MOVN in the 2E manual and
> the 2F explicits the difference. However looking at binutils,
> these opcodes are also emited on the 2E:
> https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=350cc38db21f1cd651a6d46687542a0fce5e0303;hp=569502941afa825c5278b320ccedeefc82e8ed0e
I find the manual a bit messy. It does say however:
"3.2.3 Instruction set mode
"Godson-2E processor implements a full feature MIPS III Instruction Set
Architecture (ISA) plus some MIPS IV ISA instructions, like paired single,
move condition and multiply add."
> Cc'ing Mark & Maciej in case they can enlighten me, and few
> Loongson develeper in case they could check, because I don't
> have 2E hardware to test.
At least this trivial program:
int main(void)
{
asm volatile(".set push; .set mips4; movn $0,$0,$0; .set pop");
return 0;
}
does not trap on actual hardware. I may not be able to find time right
now for a more exhaustive test.
Maciej
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E
2021-08-02 12:18 ` Maciej W. Rozycki
@ 2021-08-02 13:17 ` Philippe Mathieu-Daudé
2021-08-02 16:29 ` Maciej W. Rozycki
0 siblings, 1 reply; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-02 13:17 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, qemu-devel,
yangxiaojuan, Song Gao, Mark Shinwell, Aurelien Jarno
On 8/2/21 2:18 PM, Maciej W. Rozycki wrote:
> On Mon, 2 Aug 2021, Philippe Mathieu-Daudé wrote:
>
>>> Per the "Godson-2E User Manual v0.6", the Loongson 2E processor
>>> does not implement the MOVZ/MOVN instructions
>>
>> I'm confused because I can't find MOVZ/MOVN in the 2E manual and
>> the 2F explicits the difference. However looking at binutils,
>> these opcodes are also emited on the 2E:
>> https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=350cc38db21f1cd651a6d46687542a0fce5e0303;hp=569502941afa825c5278b320ccedeefc82e8ed0e
>
> I find the manual a bit messy. It does say however:
>
> "3.2.3 Instruction set mode
>
> "Godson-2E processor implements a full feature MIPS III Instruction Set
> Architecture (ISA) plus some MIPS IV ISA instructions, like paired single,
> move condition and multiply add."
>
>> Cc'ing Mark & Maciej in case they can enlighten me, and few
>> Loongson develeper in case they could check, because I don't
>> have 2E hardware to test.
>
> At least this trivial program:
>
> int main(void)
> {
> asm volatile(".set push; .set mips4; movn $0,$0,$0; .set pop");
> return 0;
> }
>
> does not trap on actual hardware.
Thank you very much for your time and testing!
> I may not be able to find time right
> now for a more exhaustive test.
This is fine for me now, I'll add documentation to justify while the
the documentation doesn't describe MOVZ/MOVN, it mentions "implements
MIPS IV ISA instructions like move condition" so we assume they are,
also with your test not trapping.
Regards,
Phil.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E
2021-08-02 13:17 ` Philippe Mathieu-Daudé
@ 2021-08-02 16:29 ` Maciej W. Rozycki
0 siblings, 0 replies; 5+ messages in thread
From: Maciej W. Rozycki @ 2021-08-02 16:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, qemu-devel,
yangxiaojuan, Song Gao, Aurelien Jarno
On Mon, 2 Aug 2021, Philippe Mathieu-Daudé wrote:
> > At least this trivial program:
> >
> > int main(void)
> > {
> > asm volatile(".set push; .set mips4; movn $0,$0,$0; .set pop");
> > return 0;
> > }
> >
> > does not trap on actual hardware.
>
> Thank you very much for your time and testing!
You're welcome! I'm glad to be of help.
Maciej
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-08-02 16:30 UTC | newest]
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2021-07-31 14:41 [PATCH-for-6.1?] target/mips: Remove MOVZ/MOVN opcodes from Loongson 2E Philippe Mathieu-Daudé
2021-08-02 9:25 ` Philippe Mathieu-Daudé
2021-08-02 12:18 ` Maciej W. Rozycki
2021-08-02 13:17 ` Philippe Mathieu-Daudé
2021-08-02 16:29 ` Maciej W. Rozycki
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