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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 51/55] target/alpha: Reorg fp memory operations
Date: Mon,  2 Aug 2021 18:14:39 -1000	[thread overview]
Message-ID: <20210803041443.55452-52-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210803041443.55452-1-richard.henderson@linaro.org>

Pass in the context to each mini-helper, instead of an
incorrectly named "flags".  Separate gen_load_fp and
gen_store_fp, away from the integer helpers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/translate.c | 83 +++++++++++++++++++++++++++-------------
 1 file changed, 57 insertions(+), 26 deletions(-)

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index de6c0a8439..607b6c3da7 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -267,30 +267,47 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
     return gen_excp(ctx, EXCP_OPCDEC, 0);
 }
 
-static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
+static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
 {
     TCGv_i32 tmp32 = tcg_temp_new_i32();
-    tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
-    gen_helper_memory_to_f(t0, tmp32);
+    tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+    gen_helper_memory_to_f(dest, tmp32);
     tcg_temp_free_i32(tmp32);
 }
 
-static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
+static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
 {
     TCGv tmp = tcg_temp_new();
-    tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ);
-    gen_helper_memory_to_g(t0, tmp);
+    tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+    gen_helper_memory_to_g(dest, tmp);
     tcg_temp_free(tmp);
 }
 
-static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
+static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
 {
     TCGv_i32 tmp32 = tcg_temp_new_i32();
-    tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);
-    gen_helper_memory_to_s(t0, tmp32);
+    tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+    gen_helper_memory_to_s(dest, tmp32);
     tcg_temp_free_i32(tmp32);
 }
 
+static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
+{
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
+}
+
+static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
+                        void (*func)(DisasContext *, TCGv, TCGv))
+{
+    /* Loads to $f31 are prefetches, which we can treat as nops. */
+    if (likely(ra != 31)) {
+        TCGv addr = tcg_temp_new();
+        tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
+        func(ctx, cpu_fir[ra], addr);
+        tcg_temp_free(addr);
+    }
+}
+
 static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
 {
     tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
@@ -338,30 +355,44 @@ static inline void gen_load_mem(DisasContext *ctx,
     tcg_temp_free(tmp);
 }
 
-static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
+static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
 {
     TCGv_i32 tmp32 = tcg_temp_new_i32();
-    gen_helper_f_to_memory(tmp32, t0);
-    tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
+    gen_helper_f_to_memory(tmp32, addr);
+    tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
     tcg_temp_free_i32(tmp32);
 }
 
-static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
+static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
 {
     TCGv tmp = tcg_temp_new();
-    gen_helper_g_to_memory(tmp, t0);
-    tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ);
+    gen_helper_g_to_memory(tmp, src);
+    tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
     tcg_temp_free(tmp);
 }
 
-static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
+static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
 {
     TCGv_i32 tmp32 = tcg_temp_new_i32();
-    gen_helper_s_to_memory(tmp32, t0);
-    tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);
+    gen_helper_s_to_memory(tmp32, src);
+    tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
     tcg_temp_free_i32(tmp32);
 }
 
+static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
+{
+    tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
+}
+
+static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
+                         void (*func)(DisasContext *, TCGv, TCGv))
+{
+    TCGv addr = tcg_temp_new();
+    tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
+    func(ctx, load_fpr(ctx, ra), addr);
+    tcg_temp_free(addr);
+}
+
 static inline void gen_store_mem(DisasContext *ctx,
                                  void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
                                                             int flags),
@@ -2776,42 +2807,42 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
     case 0x20:
         /* LDF */
         REQUIRE_FEN;
-        gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
+        gen_load_fp(ctx, ra, rb, disp16, gen_ldf);
         break;
     case 0x21:
         /* LDG */
         REQUIRE_FEN;
-        gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
+        gen_load_fp(ctx, ra, rb, disp16, gen_ldg);
         break;
     case 0x22:
         /* LDS */
         REQUIRE_FEN;
-        gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
+        gen_load_fp(ctx, ra, rb, disp16, gen_lds);
         break;
     case 0x23:
         /* LDT */
         REQUIRE_FEN;
-        gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
+        gen_load_fp(ctx, ra, rb, disp16, gen_ldt);
         break;
     case 0x24:
         /* STF */
         REQUIRE_FEN;
-        gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
+        gen_store_fp(ctx, ra, rb, disp16, gen_stf);
         break;
     case 0x25:
         /* STG */
         REQUIRE_FEN;
-        gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
+        gen_store_fp(ctx, ra, rb, disp16, gen_stg);
         break;
     case 0x26:
         /* STS */
         REQUIRE_FEN;
-        gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
+        gen_store_fp(ctx, ra, rb, disp16, gen_sts);
         break;
     case 0x27:
         /* STT */
         REQUIRE_FEN;
-        gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
+        gen_store_fp(ctx, ra, rb, disp16, gen_stt);
         break;
     case 0x28:
         /* LDL */
-- 
2.25.1



  parent reply	other threads:[~2021-08-03  4:42 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-03  4:13 [PATCH v2 00/55] Unaligned access for user-only Richard Henderson
2021-08-03  4:13 ` [PATCH v2 01/55] hw/core: Make do_unaligned_access noreturn Richard Henderson
2021-08-03 10:01   ` Philippe Mathieu-Daudé
2021-08-03 15:47   ` Alex Bennée
2021-08-03 18:02     ` Richard Henderson
2021-08-03  4:13 ` [PATCH v2 02/55] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-08-03  9:59   ` Philippe Mathieu-Daudé
2021-08-03 15:51   ` Alex Bennée
2021-08-03  4:13 ` [PATCH v2 03/55] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
2021-08-18  8:45   ` Philippe Mathieu-Daudé
2021-08-03  4:13 ` [PATCH v2 04/55] target/arm: " Richard Henderson
2021-08-03  4:13 ` [PATCH v2 05/55] target/hppa: " Richard Henderson
2021-08-18  8:46   ` Philippe Mathieu-Daudé
2021-08-03  4:13 ` [PATCH v2 06/55] target/microblaze: Do not set MO_ALIGN " Richard Henderson
2021-08-04  9:25   ` Edgar E. Iglesias
2021-08-03  4:13 ` [PATCH v2 07/55] target/mips: Implement do_unaligned_access " Richard Henderson
2021-08-19 19:33   ` Peter Maydell
2021-08-03  4:13 ` [PATCH v2 08/55] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-08-03  4:13 ` [PATCH v2 09/55] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-08-03  4:13 ` [PATCH v2 10/55] target/ppc: Implement do_unaligned_access for user-only Richard Henderson
2021-08-03  4:13 ` [PATCH v2 11/55] target/riscv: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 12/55] target/s390x: " Richard Henderson
2021-08-18  8:47   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 13/55] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-08-03  4:14 ` [PATCH v2 14/55] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
2021-08-03  4:14 ` [PATCH v2 15/55] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-08-18  8:36   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 16/55] target/sparc: Split out build_sfsr Richard Henderson
2021-08-18  8:38   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 17/55] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-08-18  8:47   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 18/55] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
2021-08-18  8:48   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 19/55] target/xtensa: " Richard Henderson
2021-08-03  5:38   ` Max Filippov
2021-08-18  8:48   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 20/55] accel/tcg: Report unaligned atomics " Richard Henderson
2021-08-03 15:54   ` Alex Bennée
2021-08-18  8:51   ` Philippe Mathieu-Daudé
2021-08-18 17:47     ` Richard Henderson
2021-08-03  4:14 ` [PATCH v2 21/55] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
2021-08-03 15:58   ` Alex Bennée
2021-08-03  4:14 ` [PATCH v2 22/55] tcg: Expand MO_SIZE to 3 bits Richard Henderson
2021-08-03  4:14 ` [PATCH v2 23/55] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
2021-08-03  4:14 ` [PATCH v2 24/55] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
2021-08-03  4:14 ` [PATCH v2 25/55] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
2021-08-03  4:14 ` [PATCH v2 26/55] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Richard Henderson
2021-08-03  4:14 ` [PATCH v2 27/55] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
2021-08-03  4:14 ` [PATCH v2 28/55] trace: Split guest_mem_before Richard Henderson
2021-08-18  8:58   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 29/55] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
2021-08-03  4:14 ` [PATCH v2 30/55] target/i386: " Richard Henderson
2021-08-18  8:59   ` Philippe Mathieu-Daudé
2021-08-03  4:14 ` [PATCH v2 31/55] target/ppc: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 32/55] target/s390x: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 33/55] target/hexagon: Implement cpu_mmu_index Richard Henderson
2021-08-03  4:14 ` [PATCH v2 34/55] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
2021-08-18  9:01   ` Philippe Mathieu-Daudé
2021-08-18 17:50     ` Richard Henderson
2021-08-03  4:14 ` [PATCH v2 35/55] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
2021-08-03  4:14 ` [PATCH v2 36/55] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
2021-08-03  4:14 ` [PATCH v2 37/55] target/mips: Use 8-byte memory ops " Richard Henderson
2021-08-18  9:21   ` Philippe Mathieu-Daudé
2021-08-18 17:55     ` Richard Henderson
2021-08-03  4:14 ` [PATCH v2 38/55] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
2021-08-03 11:44   ` David Hildenbrand
2021-08-03  4:14 ` [PATCH v2 39/55] target/sparc: " Richard Henderson
2021-08-03  9:55   ` Philippe Mathieu-Daudé
2021-08-18  8:51   ` Mark Cave-Ayland
2021-08-03  4:14 ` [PATCH v2 40/55] target/arm: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 41/55] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
2021-08-03  4:14 ` [PATCH v2 42/55] tcg: Add helper_unaligned_mmu for user-only sigbus Richard Henderson
2021-08-03  4:14 ` [PATCH v2 43/55] tcg/i386: Support raising sigbus for user-only Richard Henderson
2021-08-03  4:14 ` [PATCH v2 44/55] tests/tcg/multiarch: Add sigbus.c Richard Henderson
2021-08-03  4:14 ` [PATCH v2 45/55] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-08-03  4:14 ` [PATCH v2 46/55] linux-user: Disable more prctl subcodes Richard Henderson
2021-08-03  4:14 ` [PATCH v2 47/55] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass Richard Henderson
2021-08-03  4:14 ` [PATCH v2 48/55] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
2021-08-03  4:14 ` [PATCH v2 49/55] hw/core/cpu: Move cpu properties to cpu-sysemu.c Richard Henderson
2021-08-03  4:14 ` [PATCH v2 50/55] hw/core/cpu: Add prctl-unalign-sigbus property for user-only Richard Henderson
2021-08-03  4:14 ` Richard Henderson [this message]
2021-08-03  4:14 ` [PATCH v2 52/55] target/alpha: Reorg integer memory operations Richard Henderson
2021-08-03  4:14 ` [PATCH v2 53/55] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-08-03  4:14 ` [PATCH v2 54/55] target/hppa: " Richard Henderson
2021-08-03  4:14 ` [PATCH v2 55/55] target/sh4: " Richard Henderson

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