* [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync
@ 2021-08-04 9:05 Jagan Teki
2021-08-04 9:05 ` [PATCH 1/4] arm64: dts: rockchip: px30: Sync Linux PX30.Core files Jagan Teki
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Jagan Teki @ 2021-08-04 9:05 UTC (permalink / raw)
To: Kever Yang; +Cc: u-boot, linux-amarula, Jagan Teki
Series sync Linux-5.14-rc3 devicetree files for px30 SoC.
Any inputs?
Jagan.
Jagan Teki (4):
arm64: dts: rockchip: px30: Sync Linux PX30.Core files
arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi
arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i)
engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/px30-engicam-common.dtsi | 90 +++++++
arch/arm/dts/px30-engicam-ctouch2.dtsi | 22 ++
arch/arm/dts/px30-engicam-edimm2.2.dtsi | 59 +++++
.../px30-engicam-px30-core-ctouch2-of10.dts | 77 ++++++
...dts => px30-engicam-px30-core-ctouch2.dts} | 4 +-
.../dts/px30-engicam-px30-core-edimm2.2.dts | 43 ++++
arch/arm/dts/px30-engicam-px30-core.dtsi | 241 ++++++++++++++++++
arch/arm/dts/px30-evb.dts | 91 +++++--
arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 --
arch/arm/dts/px30-u-boot.dtsi | 10 +-
arch/arm/dts/px30.dtsi | 183 ++++++++-----
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 +-
arch/arm/mach-rockchip/px30/Kconfig | 8 +
board/engicam/px30_core/MAINTAINERS | 6 +
configs/px30-core-ctouch2-of10-px30_defconfig | 107 ++++++++
configs/px30-core-ctouch2-px30_defconfig | 4 +-
configs/px30-core-edimm2.2-px30_defconfig | 4 +-
18 files changed, 861 insertions(+), 124 deletions(-)
create mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%)
create mode 100644 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
create mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi
delete mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts
create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/4] arm64: dts: rockchip: px30: Sync Linux PX30.Core files
2021-08-04 9:05 [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
@ 2021-08-04 9:05 ` Jagan Teki
2021-08-04 9:05 ` [PATCH 2/4] arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi Jagan Teki
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Jagan Teki @ 2021-08-04 9:05 UTC (permalink / raw)
To: Kever Yang; +Cc: u-boot, linux-amarula, Jagan Teki
Engicam PX30.Core SoM and it's associated Carrier board device tree
files are different than the one it present in U-Boot.
Let's Sync the same from Linux-5.14-rc3 with removal of unneeded
nodes to satisfy the build.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/Makefile | 4 +-
...dts => px30-engicam-px30-core-ctouch2.dts} | 4 +-
...ts => px30-engicam-px30-core-edimm2.2.dts} | 4 +-
arch/arm/dts/px30-engicam-px30-core.dtsi | 241 ++++++++++++++++++
configs/px30-core-ctouch2-px30_defconfig | 4 +-
configs/px30-core-edimm2.2-px30_defconfig | 4 +-
6 files changed, 251 insertions(+), 10 deletions(-)
rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%)
rename arch/arm/dts/{px30-px30-core-edimm2.2.dts => px30-engicam-px30-core-edimm2.2.dts} (79%)
create mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 537c96bf5b..1d35411aa8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,8 +71,8 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
- px30-px30-core-ctouch2.dtb \
- px30-px30-core-edimm2.2.dtb \
+ px30-engicam-px30-core-ctouch2.dtb \
+ px30-engicam-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
similarity index 80%
rename from arch/arm/dts/px30-px30-core-ctouch2.dts
rename to arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
index 2da0128188..5a0ecb8fae 100644
--- a/arch/arm/dts/px30-px30-core-ctouch2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
@@ -9,11 +9,11 @@
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-ctouch2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core C.TOUCH 2.0";
- compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
"rockchip,px30";
chosen {
diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
similarity index 79%
rename from arch/arm/dts/px30-px30-core-edimm2.2.dts
rename to arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
index c36280ce7f..e54d1e480d 100644
--- a/arch/arm/dts/px30-px30-core-edimm2.2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
@@ -8,11 +8,11 @@
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-edimm2.2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
- compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
"rockchip,px30";
chosen {
diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi
new file mode 100644
index 0000000000..7249871530
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-px30-core.dtsi
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ compatible = "engicam,px30-core", "rockchip,px30";
+
+ aliases {
+ mmc0 = &emmc;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG5 {
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v0: LDO_REG1 {
+ regulator-name = "vcc_1v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-name = "vdd_1v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v0_pmu: LDO_REG4 {
+ regulator-name = "vcc3v0_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_lcd: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3_lcd";
+ };
+
+ vcc5v0_host: SWITCH_REG2 {
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vcc_3v3>;
+ vccio3-supply = <&vcc_3v3>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&pinctrl {
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc_3v3>;
+ pmuio2-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index aed790b6a6..16e4603859 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_PX30_CORE=y
@@ -21,7 +21,7 @@ CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 0340039ce7..1ac39055f6 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_PX30_CORE=y
@@ -21,7 +21,7 @@ CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi
2021-08-04 9:05 [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
2021-08-04 9:05 ` [PATCH 1/4] arm64: dts: rockchip: px30: Sync Linux PX30.Core files Jagan Teki
@ 2021-08-04 9:05 ` Jagan Teki
2021-08-04 9:05 ` [PATCH 3/4] arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i) Jagan Teki
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Jagan Teki @ 2021-08-04 9:05 UTC (permalink / raw)
To: Kever Yang; +Cc: u-boot, linux-amarula, Jagan Teki
dmc node is specific to U-Boot, it is always better practice
to maintain U-Boot specific nodes into -u-boot.dtsi files
in order to maintain Linux dts file sync compatibility.
Move the dmc into px30-u-boot.dtsi, also add dmc node
explicitly in rk3326-odroid-go2-u-boot.dtsi since it is
using px30.dts.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/px30-u-boot.dtsi | 10 ++++++----
arch/arm/dts/px30.dtsi | 5 -----
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++----
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 029c8fbd8d..bbed7dcde5 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -13,6 +13,12 @@
u-boot,spl-boot-order = &emmc, &sdmmc;
};
+ dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ };
+
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
@@ -20,10 +26,6 @@
};
};
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index b6c79e7ed3..e892d3b5a5 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -151,11 +151,6 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
- dmc: dmc {
- compatible = "rockchip,px30-dmc", "syscon";
- reg = <0x0 0xff2a0000 0x0 0x1000>;
- };
-
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopb_out>, <&vopl_out>;
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 00767d2abd..93bc399087 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -7,13 +7,15 @@
chosen {
u-boot,spl-boot-order = &sdmmc;
};
-};
-&cru {
- u-boot,dm-pre-reloc;
+ dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ };
};
-&dmc {
+&cru {
u-boot,dm-pre-reloc;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i)
2021-08-04 9:05 [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
2021-08-04 9:05 ` [PATCH 1/4] arm64: dts: rockchip: px30: Sync Linux PX30.Core files Jagan Teki
2021-08-04 9:05 ` [PATCH 2/4] arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi Jagan Teki
@ 2021-08-04 9:05 ` Jagan Teki
2021-08-04 9:05 ` [PATCH 4/4] engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF Jagan Teki
2021-10-08 21:10 ` [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
4 siblings, 0 replies; 7+ messages in thread
From: Jagan Teki @ 2021-08-04 9:05 UTC (permalink / raw)
To: Kever Yang; +Cc: u-boot, linux-amarula, Jagan Teki
Sync the px30 devicetree files from Linux-5.14-rc3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/px30-engicam-common.dtsi | 90 +++++++++
arch/arm/dts/px30-engicam-ctouch2.dtsi | 22 +++
arch/arm/dts/px30-engicam-edimm2.2.dtsi | 59 ++++++
.../px30-engicam-px30-core-ctouch2-of10.dts | 77 ++++++++
.../dts/px30-engicam-px30-core-edimm2.2.dts | 22 +++
arch/arm/dts/px30-evb.dts | 91 +++++++--
arch/arm/dts/px30.dtsi | 178 +++++++++++-------
7 files changed, 457 insertions(+), 82 deletions(-)
create mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi
index bd5bde989e..3429e124d9 100644
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ b/arch/arm/dts/px30-engicam-common.dtsi
@@ -6,6 +6,11 @@
*/
/ {
+ aliases {
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys"; /* +5V */
@@ -14,6 +19,63 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&xin32k>;
+ clock-names = "ext_clock";
+ post-power-on-delay-ms = <80>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ };
+
+ vcc3v3_btreg: vcc3v3-btreg {
+ compatible = "regulator-gpio";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable_h>;
+ regulator-name = "btreg-gpio-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ states = <3300000 0x0>;
+ };
+
+ vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rf_aux_mod";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
};
&gmac {
@@ -25,6 +87,10 @@
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sdmmc {
cap-sd-highspeed;
card-detect-delay = <800>;
@@ -33,7 +99,31 @@
status = "okay";
};
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
&uart2 {
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi
index 58425b1e55..bf10a3d29f 100644
--- a/arch/arm/dts/px30-engicam-ctouch2.dtsi
+++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi
@@ -6,3 +6,25 @@
*/
#include "px30-engicam-common.dtsi"
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
index cb00988953..449b8eb645 100644
--- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
+++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
@@ -5,3 +5,62 @@
*/
#include "px30-engicam-common.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ panel {
+ compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+ power-supply = <&vcc3v3_lcd>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+/* LVDS_B(secondary) */
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
new file mode 100644
index 0000000000..47aa30505a
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
+ "rockchip,px30";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ panel {
+ compatible = "ampire,am-1280800n3tzqw-t00h";
+ backlight = <&backlight>;
+ power-supply = <&vcc3v3_lcd>;
+ data-mapping = "vesa-24";
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
index e54d1e480d..d759478e1c 100644
--- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
@@ -19,3 +19,25 @@
stdout-path = "serial2:115200n8";
};
};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
index 4134e2ee13..c1ce9c295e 100644
--- a/arch/arm/dts/px30-evb.dts
+++ b/arch/arm/dts/px30-evb.dts
@@ -13,8 +13,14 @@
model = "Rockchip PX30 EVB";
compatible = "rockchip,px30-evb", "rockchip,px30";
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdio;
+ mmc2 = &emmc;
+ };
+
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = "serial5:115200n8";
};
adc-keys {
@@ -126,22 +132,15 @@
};
panel@0 {
- compatible = "sitronix,st7703";
+ compatible = "xinpeng,xpp055c272";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc_1v8>;
vci-supply = <&vcc3v3_lcd>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
};
};
};
@@ -152,7 +151,6 @@
};
&emmc {
- bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
@@ -171,6 +169,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_log>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -388,6 +391,43 @@
};
};
+&i2c1 {
+ status = "okay";
+
+ sensor@d {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0d>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&vcc3v0_pmu>;
+ mount-matrix = "1", /* x0 */
+ "0", /* y0 */
+ "0", /* z0 */
+ "0", /* x1 */
+ "1", /* y1 */
+ "0", /* z1 */
+ "0", /* x2 */
+ "0", /* y2 */
+ "1"; /* z2 */
+ };
+
+ touchscreen@14 {
+ compatible = "goodix,gt1151";
+ reg = <0x14>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ VDDIO-supply = <&vcc3v3_lcd>;
+ };
+
+ sensor@4c {
+ compatible = "fsl,mma7660";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
&i2s1_2ch {
status = "okay";
};
@@ -464,7 +504,6 @@
};
&sdmmc {
- bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
@@ -474,10 +513,10 @@
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
+ status = "okay";
};
&sdio {
- bus-width = <4>;
cap-sd-highspeed;
keep-power-in-suspend;
non-removable;
@@ -486,13 +525,27 @@
status = "okay";
};
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy {
status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
};
-&uart2 {
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index e892d3b5a5..248ebb61aa 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -143,7 +143,7 @@
};
arm-pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
@@ -244,28 +244,31 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+ #power-domain-cells = <0>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
<&cru SCLK_MAC_REF>,
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
@@ -277,15 +280,17 @@
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
+ #power-domain-cells = <0>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+ #power-domain-cells = <0>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
@@ -300,8 +305,9 @@
<&cru SCLK_VOPB_PWM>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
+ #power-domain-cells = <0>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
@@ -311,11 +317,13 @@
pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
+ #power-domain-cells = <0>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -600,7 +608,7 @@
};
wdt: watchdog@ff1e0000 {
- compatible = "snps,dw-wdt";
+ compatible = "rockchip,px30-wdt", "snps,dw-wdt";
reg = <0x0 0xff1e0000 0x0 0x100>;
clocks = <&cru PCLK_WDT_NS>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -703,21 +711,15 @@
clock-names = "pclk", "timer";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- dmac: dmac@ff240000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff240000 0x0 0x4000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
+ dmac: dmac@ff240000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff240000 0x0 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
tsadc: tsadc@ff280000 {
@@ -733,9 +735,9 @@
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <120000>;
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&tsadc_otp_gpio>;
+ pinctrl-0 = <&tsadc_otp_pin>;
pinctrl-1 = <&tsadc_otp_out>;
- pinctrl-2 = <&tsadc_otp_gpio>;
+ pinctrl-2 = <&tsadc_otp_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
@@ -784,6 +786,16 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <200000000>;
};
pmucru: clock-controller@ff2bc000 {
@@ -794,6 +806,13 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks =
+ <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
+ <&pmucru SCLK_WIFI_PMU>;
+ assigned-clock-rates =
+ <1200000000>, <100000000>,
+ <26000000>;
};
usb2phy_grf: syscon@ff2c0000 {
@@ -803,7 +822,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -856,7 +875,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
power-domains = <&power PX30_PD_USB>;
@@ -868,7 +886,6 @@
reg = <0x0 0xff340000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
- clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
@@ -880,7 +897,6 @@
reg = <0x0 0xff350000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
- clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
@@ -910,13 +926,14 @@
status = "disabled";
};
- sdmmc: dwmmc@ff370000 {
+ sdmmc: mmc@ff370000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff370000 0x0 0x4000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
@@ -925,13 +942,14 @@
status = "disabled";
};
- sdio: dwmmc@ff380000 {
+ sdio: mmc@ff380000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff380000 0x0 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
@@ -940,13 +958,14 @@
status = "disabled";
};
- emmc: dwmmc@ff390000 {
+ emmc: mmc@ff390000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff390000 0x0 0x4000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <8>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
@@ -955,6 +974,42 @@
status = "disabled";
};
+ nfc: nand-controller@ff3b0000 {
+ compatible = "rockchip,px30-nfc";
+ reg = <0x0 0xff3b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+ &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
gpu: gpu@ff400000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
@@ -965,6 +1020,7 @@
clocks = <&cru SCLK_GPU>;
#cooling-cells = <2>;
power-domains = <&power PX30_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
@@ -1017,7 +1073,6 @@
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
power-domains = <&power PX30_PD_VO>;
- rockchip,grf = <&grf>;
status = "disabled";
vopb_out: port {
@@ -1040,7 +1095,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1059,7 +1113,6 @@
reset-names = "axi", "ahb", "dclk";
iommus = <&vopl_mmu>;
power-domains = <&power PX30_PD_VO>;
- rockchip,grf = <&grf>;
status = "disabled";
vopl_out: port {
@@ -1081,8 +1134,7 @@
vopl_mmu: iommu@ff470f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1091,102 +1143,102 @@
};
qos_gmac: qos@ff518000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff518000 0x0 0x20>;
};
qos_gpu: qos@ff520000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff520000 0x0 0x20>;
};
qos_sdmmc: qos@ff52c000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff52c000 0x0 0x20>;
};
qos_emmc: qos@ff538000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538000 0x0 0x20>;
};
qos_nand: qos@ff538080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538080 0x0 0x20>;
};
qos_sdio: qos@ff538100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538100 0x0 0x20>;
};
qos_sfc: qos@ff538180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538180 0x0 0x20>;
};
qos_usb_host: qos@ff540000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff540000 0x0 0x20>;
};
qos_usb_otg: qos@ff540080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff540080 0x0 0x20>;
};
qos_isp_128: qos@ff548000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548000 0x0 0x20>;
};
qos_isp_rd: qos@ff548080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548080 0x0 0x20>;
};
qos_isp_wr: qos@ff548100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548100 0x0 0x20>;
};
qos_isp_m1: qos@ff548180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548180 0x0 0x20>;
};
qos_vip: qos@ff548200 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548200 0x0 0x20>;
};
qos_rga_rd: qos@ff550000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550000 0x0 0x20>;
};
qos_rga_wr: qos@ff550080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550080 0x0 0x20>;
};
qos_vop_m0: qos@ff550100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550100 0x0 0x20>;
};
qos_vop_m1: qos@ff550180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550180 0x0 0x20>;
};
qos_vpu: qos@ff558000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff558000 0x0 0x20>;
};
qos_vpu_r128: qos@ff558080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff558080 0x0 0x20>;
};
@@ -1358,7 +1410,7 @@
};
tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
2021-08-04 9:05 [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
` (2 preceding siblings ...)
2021-08-04 9:05 ` [PATCH 3/4] arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i) Jagan Teki
@ 2021-08-04 9:05 ` Jagan Teki
2021-10-08 21:10 ` [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
4 siblings, 0 replies; 7+ messages in thread
From: Jagan Teki @ 2021-08-04 9:05 UTC (permalink / raw)
To: Kever Yang; +Cc: u-boot, linux-amarula, Jagan Teki
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/mach-rockchip/px30/Kconfig | 8 ++
board/engicam/px30_core/MAINTAINERS | 6 +
configs/px30-core-ctouch2-of10-px30_defconfig | 107 ++++++++++++++++++
4 files changed, 122 insertions(+)
create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1d35411aa8..0c39cd1cf9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
px30-engicam-px30-core-ctouch2.dtb \
+ px30-engicam-px30-core-ctouch2-of10.dtb \
px30-engicam-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 16090f5b08..98e09019a2 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -27,6 +27,14 @@ config TARGET_PX30_CORE
* PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
PX30.Core C.TOUCH Carrier board.
+ PX30.Core CTOUCH2-OF10:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * CTOUCH2.0 is a general purpose Carrier board with capacitive
+ touch interface support.
+ * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
+ * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
+ 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS
index b87ca22207..77f0c2dba5 100644
--- a/board/engicam/px30_core/MAINTAINERS
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -4,6 +4,12 @@ M: Suniel Mahesh <sunil@amarulasolutions.com>
S: Maintained
F: configs/px30-core-ctouch2-px30_defconfig
+PX30-Core-CTOUCH2.0-OF10
+M: Jagan Teki <jagan@amarulasolutions.com>
+M: Suniel Mahesh <sunil@amarulasolutions.com>
+S: Maintained
+F: configs/px30-core-ctouch2-of10-px30_defconfig
+
PX30-Core-EDIMM2.2
M: Jagan Teki <jagan@amarulasolutions.com>
M: Suniel Mahesh <sunil@amarulasolutions.com>
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
new file mode 100644
index 0000000000..b92e876556
--- /dev/null
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SOUND=y
+CONFIG_SYSRESET=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LCD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync
2021-08-04 9:05 [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
` (3 preceding siblings ...)
2021-08-04 9:05 ` [PATCH 4/4] engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF Jagan Teki
@ 2021-10-08 21:10 ` Jagan Teki
2021-10-09 14:52 ` Kever Yang
4 siblings, 1 reply; 7+ messages in thread
From: Jagan Teki @ 2021-10-08 21:10 UTC (permalink / raw)
To: Kever Yang; +Cc: U-Boot-Denx, linux-amarula
Hi Kever,
Can you push these changes?
Jagan.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync
2021-10-08 21:10 ` [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
@ 2021-10-09 14:52 ` Kever Yang
0 siblings, 0 replies; 7+ messages in thread
From: Kever Yang @ 2021-10-09 14:52 UTC (permalink / raw)
To: Jagan Teki; +Cc: U-Boot-Denx, linux-amarula
Hi Jagan,
I'm sorry, I think I have miss this patch set, I can't find it in
my mailbox, and this also not delegate to me in patchwork for unknown
reason.
Who is the original author, and it's possible to send this again?
Thanks,
- Kever
On 2021/10/9 上午5:10, Jagan Teki wrote:
> Hi Kever,
>
> Can you push these changes?
>
> Jagan.
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-10-09 14:52 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-04 9:05 [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
2021-08-04 9:05 ` [PATCH 1/4] arm64: dts: rockchip: px30: Sync Linux PX30.Core files Jagan Teki
2021-08-04 9:05 ` [PATCH 2/4] arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi Jagan Teki
2021-08-04 9:05 ` [PATCH 3/4] arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i) Jagan Teki
2021-08-04 9:05 ` [PATCH 4/4] engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF Jagan Teki
2021-10-08 21:10 ` [PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync Jagan Teki
2021-10-09 14:52 ` Kever Yang
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