* [PATCH v2 1/4] dt-bindings: devfreq: event: convert Samsung Exynos NoCP to dtschema
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Convert Samsung Exynos NoC Probe bindings to DT schema format using
json-schema.
New bindings contain copied description from previous bindings document,
therefore the license is set as GPL-2.0-only.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Changes since v1:
1. New patch
---
.../bindings/devfreq/event/exynos-nocp.txt | 26 ----------
.../devfreq/event/samsung,exynos-nocp.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt b/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
deleted file mode 100644
index aeaebd425d1f..000000000000
--- a/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-
-* Samsung Exynos NoC (Network on Chip) Probe device
-
-The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
-NoC provides the primitive values to get the performance data. The packets
-that the Network on Chip (NoC) probes detects are transported over
-the network infrastructure to observer units. You can configure probes to
-capture packets with header or data on the data request response network,
-or as traffic debug or statistic collectors. Exynos542x bus has multiple
-NoC probes to provide bandwidth information about behavior of the SoC
-that you can use while analyzing system performance.
-
-Required properties:
-- compatible: Should be "samsung,exynos5420-nocp"
-- reg: physical base address of each NoC Probe and length of memory mapped region.
-
-Optional properties:
-- clock-names : the name of clock used by the NoC Probe, "nocp"
-- clocks : phandles for clock specified in "clock-names" property
-
-Example : NoC Probe nodes in Device Tree are listed below.
-
- nocp_mem0_0: nocp@10ca1000 {
- compatible = "samsung,exynos5420-nocp";
- reg = <0x10CA1000 0x200>;
- };
diff --git a/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml
new file mode 100644
index 000000000000..d318fccf78f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos NoC (Network on Chip) Probe
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
+ NoC provides the primitive values to get the performance data. The packets
+ that the Network on Chip (NoC) probes detects are transported over the
+ network infrastructure to observer units. You can configure probes to capture
+ packets with header or data on the data request response network, or as
+ traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
+ to provide bandwidth information about behavior of the SoC that you can use
+ while analyzing system performance.
+
+properties:
+ compatible:
+ const: samsung,exynos5420-nocp
+
+ clock-names:
+ items:
+ - const: nocp
+
+ clocks:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ nocp_mem0_0: nocp@10ca1000 {
+ compatible = "samsung,exynos5420-nocp";
+ reg = <0x10ca1000 0x200>;
+ };
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 2/4] dt-bindings: devfreq: event: convert Samsung Exynos PPMU to dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Convert Samsung Exynos PPMU bindings to DT schema format using
json-schema. The example is quite different due to the nature of
dtschema examples parsing (no overriding via-label allowed).
New bindings contain copied description from previous bindings document,
therefore the license is set as GPL-2.0-only.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Changes since v1:
1. New patch
---
.../bindings/devfreq/event/exynos-ppmu.txt | 169 -----------------
.../devfreq/event/samsung,exynos-ppmu.yaml | 174 ++++++++++++++++++
2 files changed, 174 insertions(+), 169 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt b/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
deleted file mode 100644
index fb46b491791c..000000000000
--- a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
+++ /dev/null
@@ -1,169 +0,0 @@
-
-* Samsung Exynos PPMU (Platform Performance Monitoring Unit) device
-
-The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
-each IP. PPMU provides the primitive values to get performance data. These
-PPMU events provide information of the SoC's behaviors so that you may
-use to analyze system performance, to make behaviors visible and to count
-usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
-The Exynos PPMU driver uses the devfreq-event class to provide event data
-to various devfreq devices. The devfreq devices would use the event data when
-derterming the current state of each IP.
-
-Required properties for PPMU device:
-- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
-- reg: physical base address of each PPMU and length of memory mapped region.
-
-Optional properties for PPMU device:
-- clock-names : the name of clock used by the PPMU, "ppmu"
-- clocks : phandles for clock specified in "clock-names" property
-
-Required properties for 'events' child node of PPMU device:
-- event-name : the unique event name among PPMU device
-Optional properties for 'events' child node of PPMU device:
-- event-data-type : Define the type of data which shell be counted
-by the counter. You can check include/dt-bindings/pmu/exynos_ppmu.h for
-all possible type, i.e. count read requests, count write data in bytes,
-etc. This field is optional and when it is missing, the driver code
-will use default data type.
-
-Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
-
- ppmu_dmc0: ppmu_dmc0@106a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106a0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_dmc1: ppmu_dmc1@106b0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106b0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_cpu: ppmu_cpu@106c0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106c0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_rightbus: ppmu_rightbus@112a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x112a0000 0x2000>;
- clocks = <&cmu CLK_PPMURIGHT>;
- clock-names = "ppmu";
- status = "disabled";
- };
-
- ppmu_leftbus: ppmu_leftbus0@116a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x116a0000 0x2000>;
- clocks = <&cmu CLK_PPMULEFT>;
- clock-names = "ppmu";
- status = "disabled";
- };
-
-Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
-
- &ppmu_dmc0 {
- status = "okay";
-
- events {
- ppmu_dmc0_3: ppmu-event3-dmc0 {
- event-name = "ppmu-event3-dmc0";
- };
-
- ppmu_dmc0_2: ppmu-event2-dmc0 {
- event-name = "ppmu-event2-dmc0";
- };
-
- ppmu_dmc0_1: ppmu-event1-dmc0 {
- event-name = "ppmu-event1-dmc0";
- };
-
- ppmu_dmc0_0: ppmu-event0-dmc0 {
- event-name = "ppmu-event0-dmc0";
- };
- };
- };
-
- &ppmu_dmc1 {
- status = "okay";
-
- events {
- ppmu_dmc1_3: ppmu-event3-dmc1 {
- event-name = "ppmu-event3-dmc1";
- };
- };
- };
-
- &ppmu_leftbus {
- status = "okay";
-
- events {
- ppmu_leftbus_3: ppmu-event3-leftbus {
- event-name = "ppmu-event3-leftbus";
- };
- };
- };
-
- &ppmu_rightbus {
- status = "okay";
-
- events {
- ppmu_rightbus_3: ppmu-event3-rightbus {
- event-name = "ppmu-event3-rightbus";
- };
- };
- };
-
-Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
-
- ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x10480000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d0_general: ppmu_d0_general@10490000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x10490000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d0_rt: ppmu_d0_rt@104a0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104a0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104b0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d1_general: ppmu_d1_general@104c0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104c0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d1_rt: ppmu_d1_rt@104d0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104d0000 0x2000>;
- status = "disabled";
- };
-
-Example4 : 'event-data-type' in exynos4412-ppmu-common.dtsi are listed below.
-
- &ppmu_dmc0 {
- status = "okay";
- events {
- ppmu_dmc0_3: ppmu-event3-dmc0 {
- event-name = "ppmu-event3-dmc0";
- event-data-type = <(PPMU_RO_DATA_CNT |
- PPMU_WO_DATA_CNT)>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
new file mode 100644
index 000000000000..d755f4ff1bea
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
+ each IP. PPMU provides the primitive values to get performance data. These
+ PPMU events provide information of the SoC's behaviors so that you may use to
+ analyze system performance, to make behaviors visible and to count usages of
+ each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
+ Exynos PPMU driver uses the devfreq-event class to provide event data to
+ various devfreq devices. The devfreq devices would use the event data when
+ derterming the current state of each IP.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos-ppmu
+ - samsung,exynos-ppmu-v2
+
+ clock-names:
+ items:
+ - const: ppmu
+
+ clocks:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ events:
+ type: object
+
+ patternProperties:
+ '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
+ type: object
+ properties:
+ event-name:
+ description: |
+ The unique event name among PPMU device
+ $ref: /schemas/types.yaml#/definitions/string
+
+ event-data-type:
+ description: |
+ Define the type of data which shell be counted by the counter.
+ You can check include/dt-bindings/pmu/exynos_ppmu.h for all
+ possible type, i.e. count read requests, count write data in
+ bytes, etc. This field is optional and when it is missing, the
+ driver code will use default data type.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - event-name
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ // PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
+ #include <dt-bindings/clock/exynos3250.h>
+
+ ppmu_dmc0: ppmu@106a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106a0000 0x2000>;
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ };
+
+ ppmu_dmc0_2: ppmu-event2-dmc0 {
+ event-name = "ppmu-event2-dmc0";
+ };
+
+ ppmu_dmc0_1: ppmu-event1-dmc0 {
+ event-name = "ppmu-event1-dmc0";
+ };
+
+ ppmu_dmc0_0: ppmu-event0-dmc0 {
+ event-name = "ppmu-event0-dmc0";
+ };
+ };
+ };
+
+ ppmu_rightbus: ppmu@112a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x112a0000 0x2000>;
+ clocks = <&cmu CLK_PPMURIGHT>;
+ clock-names = "ppmu";
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = "ppmu-event3-rightbus";
+ };
+ };
+ };
+
+ - |
+ // PPMUv2 nodes in Exynos5433
+ ppmu_d0_cpu: ppmu@10480000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x10480000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d0_general: ppmu@10490000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x10490000 0x2000>;
+
+ events {
+ ppmu_event0_d0_general: ppmu-event0-d0-general {
+ event-name = "ppmu-event0-d0-general";
+ };
+ };
+ };
+
+ ppmu_d0_rt: ppmu@104a0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104a0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_cpu: ppmu@104b0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104b0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_general: ppmu@104c0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104c0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_rt: ppmu@104d0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104d0000 0x2000>;
+ status = "disabled";
+ };
+
+ - |
+ // PPMUv1 nodes with event-data-type for Exynos4412
+ #include <dt-bindings/pmu/exynos_ppmu.h>
+
+ ppmu@106a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106a0000 0x2000>;
+ clocks = <&clock 400>;
+ clock-names = "ppmu";
+
+ events {
+ ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ event-data-type = <(PPMU_RO_DATA_CNT |
+ PPMU_WO_DATA_CNT)>;
+ };
+ };
+ };
--
2.30.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 2/4] dt-bindings: devfreq: event: convert Samsung Exynos PPMU to dtschema
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Convert Samsung Exynos PPMU bindings to DT schema format using
json-schema. The example is quite different due to the nature of
dtschema examples parsing (no overriding via-label allowed).
New bindings contain copied description from previous bindings document,
therefore the license is set as GPL-2.0-only.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Changes since v1:
1. New patch
---
.../bindings/devfreq/event/exynos-ppmu.txt | 169 -----------------
.../devfreq/event/samsung,exynos-ppmu.yaml | 174 ++++++++++++++++++
2 files changed, 174 insertions(+), 169 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt b/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
deleted file mode 100644
index fb46b491791c..000000000000
--- a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
+++ /dev/null
@@ -1,169 +0,0 @@
-
-* Samsung Exynos PPMU (Platform Performance Monitoring Unit) device
-
-The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
-each IP. PPMU provides the primitive values to get performance data. These
-PPMU events provide information of the SoC's behaviors so that you may
-use to analyze system performance, to make behaviors visible and to count
-usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
-The Exynos PPMU driver uses the devfreq-event class to provide event data
-to various devfreq devices. The devfreq devices would use the event data when
-derterming the current state of each IP.
-
-Required properties for PPMU device:
-- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
-- reg: physical base address of each PPMU and length of memory mapped region.
-
-Optional properties for PPMU device:
-- clock-names : the name of clock used by the PPMU, "ppmu"
-- clocks : phandles for clock specified in "clock-names" property
-
-Required properties for 'events' child node of PPMU device:
-- event-name : the unique event name among PPMU device
-Optional properties for 'events' child node of PPMU device:
-- event-data-type : Define the type of data which shell be counted
-by the counter. You can check include/dt-bindings/pmu/exynos_ppmu.h for
-all possible type, i.e. count read requests, count write data in bytes,
-etc. This field is optional and when it is missing, the driver code
-will use default data type.
-
-Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
-
- ppmu_dmc0: ppmu_dmc0@106a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106a0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_dmc1: ppmu_dmc1@106b0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106b0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_cpu: ppmu_cpu@106c0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106c0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_rightbus: ppmu_rightbus@112a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x112a0000 0x2000>;
- clocks = <&cmu CLK_PPMURIGHT>;
- clock-names = "ppmu";
- status = "disabled";
- };
-
- ppmu_leftbus: ppmu_leftbus0@116a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x116a0000 0x2000>;
- clocks = <&cmu CLK_PPMULEFT>;
- clock-names = "ppmu";
- status = "disabled";
- };
-
-Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
-
- &ppmu_dmc0 {
- status = "okay";
-
- events {
- ppmu_dmc0_3: ppmu-event3-dmc0 {
- event-name = "ppmu-event3-dmc0";
- };
-
- ppmu_dmc0_2: ppmu-event2-dmc0 {
- event-name = "ppmu-event2-dmc0";
- };
-
- ppmu_dmc0_1: ppmu-event1-dmc0 {
- event-name = "ppmu-event1-dmc0";
- };
-
- ppmu_dmc0_0: ppmu-event0-dmc0 {
- event-name = "ppmu-event0-dmc0";
- };
- };
- };
-
- &ppmu_dmc1 {
- status = "okay";
-
- events {
- ppmu_dmc1_3: ppmu-event3-dmc1 {
- event-name = "ppmu-event3-dmc1";
- };
- };
- };
-
- &ppmu_leftbus {
- status = "okay";
-
- events {
- ppmu_leftbus_3: ppmu-event3-leftbus {
- event-name = "ppmu-event3-leftbus";
- };
- };
- };
-
- &ppmu_rightbus {
- status = "okay";
-
- events {
- ppmu_rightbus_3: ppmu-event3-rightbus {
- event-name = "ppmu-event3-rightbus";
- };
- };
- };
-
-Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
-
- ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x10480000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d0_general: ppmu_d0_general@10490000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x10490000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d0_rt: ppmu_d0_rt@104a0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104a0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104b0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d1_general: ppmu_d1_general@104c0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104c0000 0x2000>;
- status = "disabled";
- };
-
- ppmu_d1_rt: ppmu_d1_rt@104d0000 {
- compatible = "samsung,exynos-ppmu-v2";
- reg = <0x104d0000 0x2000>;
- status = "disabled";
- };
-
-Example4 : 'event-data-type' in exynos4412-ppmu-common.dtsi are listed below.
-
- &ppmu_dmc0 {
- status = "okay";
- events {
- ppmu_dmc0_3: ppmu-event3-dmc0 {
- event-name = "ppmu-event3-dmc0";
- event-data-type = <(PPMU_RO_DATA_CNT |
- PPMU_WO_DATA_CNT)>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
new file mode 100644
index 000000000000..d755f4ff1bea
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+
+description: |
+ The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
+ each IP. PPMU provides the primitive values to get performance data. These
+ PPMU events provide information of the SoC's behaviors so that you may use to
+ analyze system performance, to make behaviors visible and to count usages of
+ each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
+ Exynos PPMU driver uses the devfreq-event class to provide event data to
+ various devfreq devices. The devfreq devices would use the event data when
+ derterming the current state of each IP.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos-ppmu
+ - samsung,exynos-ppmu-v2
+
+ clock-names:
+ items:
+ - const: ppmu
+
+ clocks:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ events:
+ type: object
+
+ patternProperties:
+ '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
+ type: object
+ properties:
+ event-name:
+ description: |
+ The unique event name among PPMU device
+ $ref: /schemas/types.yaml#/definitions/string
+
+ event-data-type:
+ description: |
+ Define the type of data which shell be counted by the counter.
+ You can check include/dt-bindings/pmu/exynos_ppmu.h for all
+ possible type, i.e. count read requests, count write data in
+ bytes, etc. This field is optional and when it is missing, the
+ driver code will use default data type.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - event-name
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ // PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
+ #include <dt-bindings/clock/exynos3250.h>
+
+ ppmu_dmc0: ppmu@106a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106a0000 0x2000>;
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ };
+
+ ppmu_dmc0_2: ppmu-event2-dmc0 {
+ event-name = "ppmu-event2-dmc0";
+ };
+
+ ppmu_dmc0_1: ppmu-event1-dmc0 {
+ event-name = "ppmu-event1-dmc0";
+ };
+
+ ppmu_dmc0_0: ppmu-event0-dmc0 {
+ event-name = "ppmu-event0-dmc0";
+ };
+ };
+ };
+
+ ppmu_rightbus: ppmu@112a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x112a0000 0x2000>;
+ clocks = <&cmu CLK_PPMURIGHT>;
+ clock-names = "ppmu";
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = "ppmu-event3-rightbus";
+ };
+ };
+ };
+
+ - |
+ // PPMUv2 nodes in Exynos5433
+ ppmu_d0_cpu: ppmu@10480000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x10480000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d0_general: ppmu@10490000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x10490000 0x2000>;
+
+ events {
+ ppmu_event0_d0_general: ppmu-event0-d0-general {
+ event-name = "ppmu-event0-d0-general";
+ };
+ };
+ };
+
+ ppmu_d0_rt: ppmu@104a0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104a0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_cpu: ppmu@104b0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104b0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_general: ppmu@104c0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104c0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_rt: ppmu@104d0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104d0000 0x2000>;
+ status = "disabled";
+ };
+
+ - |
+ // PPMUv1 nodes with event-data-type for Exynos4412
+ #include <dt-bindings/pmu/exynos_ppmu.h>
+
+ ppmu@106a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106a0000 0x2000>;
+ clocks = <&clock 400>;
+ clock-names = "ppmu";
+
+ events {
+ ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ event-data-type = <(PPMU_RO_DATA_CNT |
+ PPMU_WO_DATA_CNT)>;
+ };
+ };
+ };
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 2/4] dt-bindings: devfreq: event: convert Samsung Exynos PPMU to dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-08-24 13:02 ` Rob Herring
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 13:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lukasz Luba, linux-arm-kernel, linux-samsung-soc, devicetree,
Kyungmin Park, linux-pm, MyungJoo Ham, Rob Herring, Chanwoo Choi,
linux-kernel
On Fri, 20 Aug 2021 17:03:51 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos PPMU bindings to DT schema format using
> json-schema. The example is quite different due to the nature of
> dtschema examples parsing (no overriding via-label allowed).
>
> New bindings contain copied description from previous bindings document,
> therefore the license is set as GPL-2.0-only.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. New patch
> ---
> .../bindings/devfreq/event/exynos-ppmu.txt | 169 -----------------
> .../devfreq/event/samsung,exynos-ppmu.yaml | 174 ++++++++++++++++++
> 2 files changed, 174 insertions(+), 169 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: devfreq: event: convert Samsung Exynos PPMU to dtschema
@ 2021-08-24 13:02 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 13:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lukasz Luba, linux-arm-kernel, linux-samsung-soc, devicetree,
Kyungmin Park, linux-pm, MyungJoo Ham, Rob Herring, Chanwoo Choi,
linux-kernel
On Fri, 20 Aug 2021 17:03:51 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos PPMU bindings to DT schema format using
> json-schema. The example is quite different due to the nature of
> dtschema examples parsing (no overriding via-label allowed).
>
> New bindings contain copied description from previous bindings document,
> therefore the license is set as GPL-2.0-only.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. New patch
> ---
> .../bindings/devfreq/event/exynos-ppmu.txt | 169 -----------------
> .../devfreq/event/samsung,exynos-ppmu.yaml | 174 ++++++++++++++++++
> 2 files changed, 174 insertions(+), 169 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 3/4] dt-bindings: memory: convert Samsung Exynos DMC to dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Convert Samsung Exynos5422 SoC frequency and voltage scaling for
Dynamic Memory Controller to DT schema format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Lukasz Luba <lukasz.luba@arm.com>
---
Changes since v1:
1. Corrent PPMU event node name (remove underscore).
2. Add Ack.
---
.../memory-controllers/exynos5422-dmc.txt | 84 -----------
.../samsung,exynos5422-dmc.yaml | 137 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 138 insertions(+), 85 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
deleted file mode 100644
index 02e4a1f862f1..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
-
-The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
-memory chips are connected. The driver is to monitor the controller in runtime
-and switch frequency and voltage. To monitor the usage of the controller in
-runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
-is able to measure the current load of the memory.
-When 'userspace' governor is used for the driver, an application is able to
-switch the DMC and memory frequency.
-
-Required properties for DMC device for Exynos5422:
-- compatible: Should be "samsung,exynos5422-dmc".
-- clocks : list of clock specifiers, must contain an entry for each
- required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
- CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
- CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
-- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
- "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
- "mout_mclk_cdrex" entries
-- devfreq-events : phandles for PPMU devices connected to this DMC.
-- vdd-supply : phandle for voltage regulator which is connected.
-- reg : registers of two CDREX controllers.
-- operating-points-v2 : phandle for OPPs described in v2 definition.
-- device-handle : phandle of the connected DRAM memory device. For more
- information please refer to documentation file:
- Documentation/devicetree/bindings/ddr/lpddr3.txt
-- devfreq-events : phandles of the PPMU events used by the controller.
-- samsung,syscon-clk : phandle of the clock register set used by the controller,
- these registers are used for enabling a 'pause' feature and are not
- exposed by clock framework but they must be used in a safe way.
- The register offsets are in the driver code and specyfic for this SoC
- type.
-
-Optional properties for DMC device for Exynos5422:
-- interrupt-parent : The parent interrupt controller.
-- interrupts : Contains the IRQ line numbers for the DMC internal performance
- event counters in DREX0 and DREX1 channels. Align with specification of the
- interrupt line(s) in the interrupt-parent controller.
-- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
- same as in the 'interrupts' list above.
-
-Example:
-
- ppmu_dmc0_0: ppmu@10d00000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x10d00000 0x2000>;
- clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
- clock-names = "ppmu";
- events {
- ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
- event-name = "ppmu-event3-dmc0_0";
- };
- };
- };
-
- dmc: memory-controller@10c20000 {
- compatible = "samsung,exynos5422-dmc";
- reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
- clocks = <&clock CLK_FOUT_SPLL>,
- <&clock CLK_MOUT_SCLK_SPLL>,
- <&clock CLK_FF_DOUT_SPLL2>,
- <&clock CLK_FOUT_BPLL>,
- <&clock CLK_MOUT_BPLL>,
- <&clock CLK_SCLK_BPLL>,
- <&clock CLK_MOUT_MX_MSPLL_CCORE>,
- <&clock CLK_MOUT_MCLK_CDREX>;
- clock-names = "fout_spll",
- "mout_sclk_spll",
- "ff_dout_spll2",
- "fout_bpll",
- "mout_bpll",
- "sclk_bpll",
- "mout_mx_mspll_ccore",
- "mout_mclk_cdrex";
- operating-points-v2 = <&dmc_opp_table>;
- devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
- <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
- device-handle = <&samsung_K3QF2F20DB>;
- vdd-supply = <&buck1_reg>;
- samsung,syscon-clk = <&clock>;
- interrupt-parent = <&combiner>;
- interrupts = <16 0>, <16 1>;
- interrupt-names = "drex_0", "drex_1";
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
new file mode 100644
index 000000000000..6f4fd5814bf4
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: |
+ Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
+ Controller device
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Lukasz Luba <lukasz.luba@arm.com>
+
+description: |
+ The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
+ DRAM memory chips are connected. The driver is to monitor the controller in
+ runtime and switch frequency and voltage. To monitor the usage of the
+ controller in runtime, the driver uses the PPMU (Platform Performance
+ Monitoring Unit), which is able to measure the current load of the memory.
+ When 'userspace' governor is used for the driver, an application is able to
+ switch the DMC and memory frequency.
+
+properties:
+ compatible:
+ items:
+ - const: samsung,exynos5422-dmc
+
+ clock-names:
+ items:
+ - const: fout_spll
+ - const: mout_sclk_spll
+ - const: ff_dout_spll2
+ - const: fout_bpll
+ - const: mout_bpll
+ - const: sclk_bpll
+ - const: mout_mx_mspll_ccore
+ - const: mout_mclk_cdrex
+
+ clocks:
+ minItems: 8
+ maxItems: 8
+
+ devfreq-events:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ minItems: 1
+ maxItems: 16
+ description: phandles of the PPMU events used by the controller.
+
+ device-handle:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ phandle of the connected DRAM memory device. For more information please
+ refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
+
+ operating-points-v2: true
+
+ interrupts:
+ items:
+ - description: DMC internal performance event counters in DREX0
+ - description: DMC internal performance event counters in DREX1
+
+ interrupt-names:
+ items:
+ - const: drex_0
+ - const: drex_1
+
+ reg:
+ items:
+ - description: registers of DREX0
+ - description: registers of DREX1
+
+ samsung,syscon-clk:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Phandle of the clock register set used by the controller, these registers
+ are used for enabling a 'pause' feature and are not exposed by clock
+ framework but they must be used in a safe way. The register offsets are
+ in the driver code and specyfic for this SoC type.
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - clock-names
+ - clocks
+ - devfreq-events
+ - device-handle
+ - reg
+ - samsung,syscon-clk
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5420.h>
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ operating-points-v2 = <&dmc_opp_table>;
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ vdd-supply = <&buck1_reg>;
+ samsung,syscon-clk = <&clock>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index ebdb07a49b02..eb4ada858826 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5570,7 +5570,7 @@ M: Lukasz Luba <lukasz.luba@arm.com>
L: linux-pm@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
+F: Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
F: drivers/memory/samsung/exynos5422-dmc.c
DME1737 HARDWARE MONITOR DRIVER
--
2.30.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 3/4] dt-bindings: memory: convert Samsung Exynos DMC to dtschema
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Convert Samsung Exynos5422 SoC frequency and voltage scaling for
Dynamic Memory Controller to DT schema format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Lukasz Luba <lukasz.luba@arm.com>
---
Changes since v1:
1. Corrent PPMU event node name (remove underscore).
2. Add Ack.
---
.../memory-controllers/exynos5422-dmc.txt | 84 -----------
.../samsung,exynos5422-dmc.yaml | 137 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 138 insertions(+), 85 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
deleted file mode 100644
index 02e4a1f862f1..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
-
-The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
-memory chips are connected. The driver is to monitor the controller in runtime
-and switch frequency and voltage. To monitor the usage of the controller in
-runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
-is able to measure the current load of the memory.
-When 'userspace' governor is used for the driver, an application is able to
-switch the DMC and memory frequency.
-
-Required properties for DMC device for Exynos5422:
-- compatible: Should be "samsung,exynos5422-dmc".
-- clocks : list of clock specifiers, must contain an entry for each
- required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
- CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
- CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
-- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
- "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
- "mout_mclk_cdrex" entries
-- devfreq-events : phandles for PPMU devices connected to this DMC.
-- vdd-supply : phandle for voltage regulator which is connected.
-- reg : registers of two CDREX controllers.
-- operating-points-v2 : phandle for OPPs described in v2 definition.
-- device-handle : phandle of the connected DRAM memory device. For more
- information please refer to documentation file:
- Documentation/devicetree/bindings/ddr/lpddr3.txt
-- devfreq-events : phandles of the PPMU events used by the controller.
-- samsung,syscon-clk : phandle of the clock register set used by the controller,
- these registers are used for enabling a 'pause' feature and are not
- exposed by clock framework but they must be used in a safe way.
- The register offsets are in the driver code and specyfic for this SoC
- type.
-
-Optional properties for DMC device for Exynos5422:
-- interrupt-parent : The parent interrupt controller.
-- interrupts : Contains the IRQ line numbers for the DMC internal performance
- event counters in DREX0 and DREX1 channels. Align with specification of the
- interrupt line(s) in the interrupt-parent controller.
-- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
- same as in the 'interrupts' list above.
-
-Example:
-
- ppmu_dmc0_0: ppmu@10d00000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x10d00000 0x2000>;
- clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
- clock-names = "ppmu";
- events {
- ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
- event-name = "ppmu-event3-dmc0_0";
- };
- };
- };
-
- dmc: memory-controller@10c20000 {
- compatible = "samsung,exynos5422-dmc";
- reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
- clocks = <&clock CLK_FOUT_SPLL>,
- <&clock CLK_MOUT_SCLK_SPLL>,
- <&clock CLK_FF_DOUT_SPLL2>,
- <&clock CLK_FOUT_BPLL>,
- <&clock CLK_MOUT_BPLL>,
- <&clock CLK_SCLK_BPLL>,
- <&clock CLK_MOUT_MX_MSPLL_CCORE>,
- <&clock CLK_MOUT_MCLK_CDREX>;
- clock-names = "fout_spll",
- "mout_sclk_spll",
- "ff_dout_spll2",
- "fout_bpll",
- "mout_bpll",
- "sclk_bpll",
- "mout_mx_mspll_ccore",
- "mout_mclk_cdrex";
- operating-points-v2 = <&dmc_opp_table>;
- devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
- <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
- device-handle = <&samsung_K3QF2F20DB>;
- vdd-supply = <&buck1_reg>;
- samsung,syscon-clk = <&clock>;
- interrupt-parent = <&combiner>;
- interrupts = <16 0>, <16 1>;
- interrupt-names = "drex_0", "drex_1";
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
new file mode 100644
index 000000000000..6f4fd5814bf4
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: |
+ Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
+ Controller device
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Lukasz Luba <lukasz.luba@arm.com>
+
+description: |
+ The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
+ DRAM memory chips are connected. The driver is to monitor the controller in
+ runtime and switch frequency and voltage. To monitor the usage of the
+ controller in runtime, the driver uses the PPMU (Platform Performance
+ Monitoring Unit), which is able to measure the current load of the memory.
+ When 'userspace' governor is used for the driver, an application is able to
+ switch the DMC and memory frequency.
+
+properties:
+ compatible:
+ items:
+ - const: samsung,exynos5422-dmc
+
+ clock-names:
+ items:
+ - const: fout_spll
+ - const: mout_sclk_spll
+ - const: ff_dout_spll2
+ - const: fout_bpll
+ - const: mout_bpll
+ - const: sclk_bpll
+ - const: mout_mx_mspll_ccore
+ - const: mout_mclk_cdrex
+
+ clocks:
+ minItems: 8
+ maxItems: 8
+
+ devfreq-events:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ minItems: 1
+ maxItems: 16
+ description: phandles of the PPMU events used by the controller.
+
+ device-handle:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ phandle of the connected DRAM memory device. For more information please
+ refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
+
+ operating-points-v2: true
+
+ interrupts:
+ items:
+ - description: DMC internal performance event counters in DREX0
+ - description: DMC internal performance event counters in DREX1
+
+ interrupt-names:
+ items:
+ - const: drex_0
+ - const: drex_1
+
+ reg:
+ items:
+ - description: registers of DREX0
+ - description: registers of DREX1
+
+ samsung,syscon-clk:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Phandle of the clock register set used by the controller, these registers
+ are used for enabling a 'pause' feature and are not exposed by clock
+ framework but they must be used in a safe way. The register offsets are
+ in the driver code and specyfic for this SoC type.
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - clock-names
+ - clocks
+ - devfreq-events
+ - device-handle
+ - reg
+ - samsung,syscon-clk
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5420.h>
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ operating-points-v2 = <&dmc_opp_table>;
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ vdd-supply = <&buck1_reg>;
+ samsung,syscon-clk = <&clock>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index ebdb07a49b02..eb4ada858826 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5570,7 +5570,7 @@ M: Lukasz Luba <lukasz.luba@arm.com>
L: linux-pm@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
+F: Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
F: drivers/memory/samsung/exynos5422-dmc.c
DME1737 HARDWARE MONITOR DRIVER
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 3/4] dt-bindings: memory: convert Samsung Exynos DMC to dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-08-24 13:02 ` Rob Herring
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 13:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lukasz Luba, MyungJoo Ham, Rob Herring, linux-pm, Kyungmin Park,
linux-samsung-soc, linux-kernel, devicetree, Chanwoo Choi,
linux-arm-kernel
On Fri, 20 Aug 2021 17:03:52 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5422 SoC frequency and voltage scaling for
> Dynamic Memory Controller to DT schema format using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Acked-by: Lukasz Luba <lukasz.luba@arm.com>
>
> ---
>
> Changes since v1:
> 1. Corrent PPMU event node name (remove underscore).
> 2. Add Ack.
> ---
> .../memory-controllers/exynos5422-dmc.txt | 84 -----------
> .../samsung,exynos5422-dmc.yaml | 137 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 138 insertions(+), 85 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: memory: convert Samsung Exynos DMC to dtschema
@ 2021-08-24 13:02 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 13:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lukasz Luba, MyungJoo Ham, Rob Herring, linux-pm, Kyungmin Park,
linux-samsung-soc, linux-kernel, devicetree, Chanwoo Choi,
linux-arm-kernel
On Fri, 20 Aug 2021 17:03:52 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5422 SoC frequency and voltage scaling for
> Dynamic Memory Controller to DT schema format using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Acked-by: Lukasz Luba <lukasz.luba@arm.com>
>
> ---
>
> Changes since v1:
> 1. Corrent PPMU event node name (remove underscore).
> 2. Add Ack.
> ---
> .../memory-controllers/exynos5422-dmc.txt | 84 -----------
> .../samsung,exynos5422-dmc.yaml | 137 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 138 insertions(+), 85 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Use hyphen instead of underscore and align the PPMU event node name with
dtschema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Changes since v1:
1. New patch
---
arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e23e8ffb093f..10ccd5cb69fd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -302,7 +302,7 @@ ppmu_dmc0_0: ppmu@10d00000 {
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+ ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
event-name = "ppmu-event3-dmc0_0";
};
};
@@ -314,7 +314,7 @@ ppmu_dmc0_1: ppmu@10d10000 {
clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+ ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
event-name = "ppmu-event3-dmc0_1";
};
};
@@ -326,7 +326,7 @@ ppmu_dmc1_0: ppmu@10d60000 {
clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+ ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
event-name = "ppmu-event3-dmc1_0";
};
};
@@ -338,7 +338,7 @@ ppmu_dmc1_1: ppmu@10d70000 {
clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+ ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
event-name = "ppmu-event3-dmc1_1";
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
@ 2021-08-20 15:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-08-20 15:03 UTC (permalink / raw)
To: Chanwoo Choi, MyungJoo Ham, Kyungmin Park, Rob Herring,
Krzysztof Kozlowski, Lukasz Luba, linux-pm, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Use hyphen instead of underscore and align the PPMU event node name with
dtschema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Changes since v1:
1. New patch
---
arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e23e8ffb093f..10ccd5cb69fd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -302,7 +302,7 @@ ppmu_dmc0_0: ppmu@10d00000 {
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+ ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
event-name = "ppmu-event3-dmc0_0";
};
};
@@ -314,7 +314,7 @@ ppmu_dmc0_1: ppmu@10d10000 {
clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+ ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
event-name = "ppmu-event3-dmc0_1";
};
};
@@ -326,7 +326,7 @@ ppmu_dmc1_0: ppmu@10d60000 {
clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+ ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
event-name = "ppmu-event3-dmc1_0";
};
};
@@ -338,7 +338,7 @@ ppmu_dmc1_1: ppmu@10d70000 {
clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
clock-names = "ppmu";
events {
- ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+ ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
event-name = "ppmu-event3-dmc1_1";
};
};
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: (subset) [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-09-15 7:50 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-09-15 7:50 UTC (permalink / raw)
To: Kyungmin Park, linux-samsung-soc, MyungJoo Ham, linux-kernel,
Chanwoo Choi, linux-pm, Lukasz Luba, devicetree,
Krzysztof Kozlowski, linux-arm-kernel, Rob Herring
On Fri, 20 Aug 2021 17:03:53 +0200, Krzysztof Kozlowski wrote:
> Use hyphen instead of underscore and align the PPMU event node name with
> dtschema.
>
>
Applied, thanks!
[4/4] ARM: dts: exynos: align PPMU event node names with dtschema
commit: fb9b199e562d66af90f61d70eb737fa5e4deac2c
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: (subset) [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
@ 2021-09-15 7:50 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-09-15 7:50 UTC (permalink / raw)
To: Kyungmin Park, linux-samsung-soc, MyungJoo Ham, linux-kernel,
Chanwoo Choi, linux-pm, Lukasz Luba, devicetree,
Krzysztof Kozlowski, linux-arm-kernel, Rob Herring
On Fri, 20 Aug 2021 17:03:53 +0200, Krzysztof Kozlowski wrote:
> Use hyphen instead of underscore and align the PPMU event node name with
> dtschema.
>
>
Applied, thanks!
[4/4] ARM: dts: exynos: align PPMU event node names with dtschema
commit: fb9b199e562d66af90f61d70eb737fa5e4deac2c
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: (subset) [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
2021-09-15 7:50 ` Krzysztof Kozlowski
@ 2021-09-16 11:15 ` Marek Szyprowski
-1 siblings, 0 replies; 20+ messages in thread
From: Marek Szyprowski @ 2021-09-16 11:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kyungmin Park, linux-samsung-soc,
MyungJoo Ham, linux-kernel, Chanwoo Choi, linux-pm, Lukasz Luba,
devicetree, linux-arm-kernel, Rob Herring
Hi Krzysztof,
On 15.09.2021 09:50, Krzysztof Kozlowski wrote:
> On Fri, 20 Aug 2021 17:03:53 +0200, Krzysztof Kozlowski wrote:
>> Use hyphen instead of underscore and align the PPMU event node name with
>> dtschema.
>>
>>
> Applied, thanks!
>
> [4/4] ARM: dts: exynos: align PPMU event node names with dtschema
> commit: fb9b199e562d66af90f61d70eb737fa5e4deac2c
>
This breaks probing of Exynos event counters, which are needed by the
Exynos DMC driver on Odroid XU3/XU4/HC1 boards. Just check the today's
linux-next. I had no time to analyze which part of the code depends on
the node names though...
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: (subset) [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
@ 2021-09-16 11:15 ` Marek Szyprowski
0 siblings, 0 replies; 20+ messages in thread
From: Marek Szyprowski @ 2021-09-16 11:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kyungmin Park, linux-samsung-soc,
MyungJoo Ham, linux-kernel, Chanwoo Choi, linux-pm, Lukasz Luba,
devicetree, linux-arm-kernel, Rob Herring
Hi Krzysztof,
On 15.09.2021 09:50, Krzysztof Kozlowski wrote:
> On Fri, 20 Aug 2021 17:03:53 +0200, Krzysztof Kozlowski wrote:
>> Use hyphen instead of underscore and align the PPMU event node name with
>> dtschema.
>>
>>
> Applied, thanks!
>
> [4/4] ARM: dts: exynos: align PPMU event node names with dtschema
> commit: fb9b199e562d66af90f61d70eb737fa5e4deac2c
>
This breaks probing of Exynos event counters, which are needed by the
Exynos DMC driver on Odroid XU3/XU4/HC1 boards. Just check the today's
linux-next. I had no time to analyze which part of the code depends on
the node names though...
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: (subset) [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
2021-09-16 11:15 ` Marek Szyprowski
@ 2021-09-16 11:16 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-09-16 11:16 UTC (permalink / raw)
To: Marek Szyprowski, Kyungmin Park, linux-samsung-soc, MyungJoo Ham,
linux-kernel, Chanwoo Choi, linux-pm, Lukasz Luba, devicetree,
linux-arm-kernel, Rob Herring
On 16/09/2021 13:15, Marek Szyprowski wrote:
> Hi Krzysztof,
>
> On 15.09.2021 09:50, Krzysztof Kozlowski wrote:
>> On Fri, 20 Aug 2021 17:03:53 +0200, Krzysztof Kozlowski wrote:
>>> Use hyphen instead of underscore and align the PPMU event node name with
>>> dtschema.
>>>
>>>
>> Applied, thanks!
>>
>> [4/4] ARM: dts: exynos: align PPMU event node names with dtschema
>> commit: fb9b199e562d66af90f61d70eb737fa5e4deac2c
>>
> This breaks probing of Exynos event counters, which are needed by the
> Exynos DMC driver on Odroid XU3/XU4/HC1 boards. Just check the today's
> linux-next. I had no time to analyze which part of the code depends on
> the node names though...
Thanks for the report. I'll drop the patch from my queue and check later
the driver.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: (subset) [PATCH v2 4/4] ARM: dts: exynos: align PPMU event node names with dtschema
@ 2021-09-16 11:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2021-09-16 11:16 UTC (permalink / raw)
To: Marek Szyprowski, Kyungmin Park, linux-samsung-soc, MyungJoo Ham,
linux-kernel, Chanwoo Choi, linux-pm, Lukasz Luba, devicetree,
linux-arm-kernel, Rob Herring
On 16/09/2021 13:15, Marek Szyprowski wrote:
> Hi Krzysztof,
>
> On 15.09.2021 09:50, Krzysztof Kozlowski wrote:
>> On Fri, 20 Aug 2021 17:03:53 +0200, Krzysztof Kozlowski wrote:
>>> Use hyphen instead of underscore and align the PPMU event node name with
>>> dtschema.
>>>
>>>
>> Applied, thanks!
>>
>> [4/4] ARM: dts: exynos: align PPMU event node names with dtschema
>> commit: fb9b199e562d66af90f61d70eb737fa5e4deac2c
>>
> This breaks probing of Exynos event counters, which are needed by the
> Exynos DMC driver on Odroid XU3/XU4/HC1 boards. Just check the today's
> linux-next. I had no time to analyze which part of the code depends on
> the node names though...
Thanks for the report. I'll drop the patch from my queue and check later
the driver.
Best regards,
Krzysztof
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: devfreq: event: convert Samsung Exynos NoCP to dtschema
2021-08-20 15:03 ` Krzysztof Kozlowski
@ 2021-08-24 13:01 ` Rob Herring
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 13:01 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-arm-kernel, Rob Herring,
MyungJoo Ham, devicetree, Kyungmin Park, Chanwoo Choi,
Lukasz Luba, linux-pm
On Fri, 20 Aug 2021 17:03:50 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos NoC Probe bindings to DT schema format using
> json-schema.
>
> New bindings contain copied description from previous bindings document,
> therefore the license is set as GPL-2.0-only.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. New patch
> ---
> .../bindings/devfreq/event/exynos-nocp.txt | 26 ----------
> .../devfreq/event/samsung,exynos-nocp.yaml | 48 +++++++++++++++++++
> 2 files changed, 48 insertions(+), 26 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: devfreq: event: convert Samsung Exynos NoCP to dtschema
@ 2021-08-24 13:01 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 13:01 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, linux-samsung-soc, linux-arm-kernel, Rob Herring,
MyungJoo Ham, devicetree, Kyungmin Park, Chanwoo Choi,
Lukasz Luba, linux-pm
On Fri, 20 Aug 2021 17:03:50 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos NoC Probe bindings to DT schema format using
> json-schema.
>
> New bindings contain copied description from previous bindings document,
> therefore the license is set as GPL-2.0-only.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. New patch
> ---
> .../bindings/devfreq/event/exynos-nocp.txt | 26 ----------
> .../devfreq/event/samsung,exynos-nocp.yaml | 48 +++++++++++++++++++
> 2 files changed, 48 insertions(+), 26 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml
>
Applied, thanks!
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^ permalink raw reply [flat|nested] 20+ messages in thread