From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v5 10/14] target/riscv: Add a REQUIRE_32BIT macro
Date: Mon, 23 Aug 2021 20:42:44 +0200 [thread overview]
Message-ID: <20210823184248.2209614-11-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20210823184248.2209614-1-philipp.tomsich@vrull.eu>
With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
(no changes since v3)
Changes in v3:
- Moved the REQUIRE_32BIT macro into a separate commit.
target/riscv/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bdb47905f6..9b726ce9c4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -417,6 +417,12 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_32BIT(ctx) do { \
+ if (!is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_64BIT(ctx) do { \
if (is_32bit(ctx)) { \
return false; \
--
2.25.1
next prev parent reply other threads:[~2021-08-23 18:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 18:42 [PATCH v5 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 02/14] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 04/14] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 06/14] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 07/14] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-08-25 13:39 ` Richard Henderson
2021-08-25 17:01 ` Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 08/14] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-08-23 18:42 ` Philipp Tomsich [this message]
2021-08-23 18:42 ` [PATCH v5 11/14] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 13/14] target/riscv: Remove RVB (replaced by Zb[abcs] Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 14/14] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
2021-08-25 16:56 [PATCH v5 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-25 16:56 ` [PATCH v5 10/14] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
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