From: Richard Henderson <richard.henderson@linaro.org>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, qemu-devel@nongnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v5 07/14] target/riscv: Add instructions of the Zbc-extension
Date: Wed, 25 Aug 2021 06:39:59 -0700 [thread overview]
Message-ID: <7c3e8e3a-62b4-532f-0682-52deb58ec0b9@linaro.org> (raw)
In-Reply-To: <20210823184248.2209614-8-philipp.tomsich@vrull.eu>
On 8/23/21 11:42 AM, Philipp Tomsich wrote:
> +static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
> +{
> + REQUIRE_ZBC(ctx);
> + return gen_arith(ctx, a, gen_helper_clmul);
> +}
> +
> +
> +static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
> +{
> + REQUIRE_ZBC(ctx);
> + return gen_arith(ctx, a, gen_clmulh);
> +}
> +
> +static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
> +{
> + REQUIRE_ZBC(ctx);
> + return gen_arith(ctx, a, gen_helper_clmulr);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index fc22ae82d0..32a067dcd2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -739,6 +739,12 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_gen_add_tl(ret, arg1, arg2);
> }
>
> +static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
> +{
> + gen_helper_clmulr(dst, src1, src2);
> + tcg_gen_shri_tl(dst, dst, 1);
> +}
> +
Put this immediately before its use in trans_rvb.c.inc. I have patches to clean up the
rest of the instances that still remain in translate.c.
With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-08-25 13:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 18:42 [PATCH v5 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 02/14] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 04/14] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 06/14] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 07/14] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-08-25 13:39 ` Richard Henderson [this message]
2021-08-25 17:01 ` Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 08/14] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 10/14] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 11/14] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 13/14] target/riscv: Remove RVB (replaced by Zb[abcs] Philipp Tomsich
2021-08-23 18:42 ` [PATCH v5 14/14] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
2021-08-25 16:56 [PATCH v5 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-25 16:56 ` [PATCH v5 07/14] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
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