From: Sasha Levin <sashal@kernel.org> To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@google.com>, Will Deacon <will@kernel.org>, Sasha Levin <sashal@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.13 26/26] arm64: initialize all of CNTHCTL_EL2 Date: Mon, 23 Aug 2021 20:53:56 -0400 [thread overview] Message-ID: <20210824005356.630888-26-sashal@kernel.org> (raw) In-Reply-To: <20210824005356.630888-1-sashal@kernel.org> From: Mark Rutland <mark.rutland@arm.com> [ Upstream commit bde8fff82e4a4b0f000dbf4d5eadab2079be0b56 ] In __init_el2_timers we initialize CNTHCTL_EL2.{EL1PCEN,EL1PCTEN} with a RMW sequence, leaving all other bits UNKNOWN. In general, we should initialize all bits in a register rather than using an RMW sequence, since most bits are UNKNOWN out of reset, and as new bits are added to the reigster their reset value might not result in expected behaviour. In the case of CNTHCTL_EL2, FEAT_ECV added a number of new control bits in previously RES0 bits, which reset to UNKNOWN values, and may cause issues for EL1 and EL0: * CNTHCTL_EL2.ECV enables the CNTPOFF_EL2 offset (which itself resets to an UNKNOWN value) at EL0 and EL1. Since the offset could reset to distinct values across CPUs, when the control bit resets to 1 this could break timekeeping generally. * CNTHCTL_EL2.{EL1TVT,EL1TVCT} trap EL0 and EL1 accesses to the EL1 virtual timer/counter registers to EL2. When reset to 1, this could cause unexpected traps to EL2. Initializing these bits to zero avoids these problems, and all other bits in CNTHCTL_EL2 other than EL1PCEN and EL1PCTEN can safely be reset to zero. This patch ensures we initialize CNTHCTL_EL2 accordingly, only setting EL1PCEN and EL1PCTEN, and setting all other bits to zero. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Oliver Upton <oupton@google.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Oliver Upton <oupton@google.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210818161535.52786-1-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> --- arch/arm64/include/asm/el2_setup.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 21fa330f498d..b83fb24954b7 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -33,8 +33,7 @@ * EL2. */ .macro __init_el2_timers - mrs x0, cnthctl_el2 - orr x0, x0, #3 // Enable EL1 physical timers + mov x0, #3 // Enable EL1 physical timers msr cnthctl_el2, x0 msr cntvoff_el2, xzr // Clear virtual offset .endm -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org> To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@google.com>, Will Deacon <will@kernel.org>, Sasha Levin <sashal@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.13 26/26] arm64: initialize all of CNTHCTL_EL2 Date: Mon, 23 Aug 2021 20:53:56 -0400 [thread overview] Message-ID: <20210824005356.630888-26-sashal@kernel.org> (raw) In-Reply-To: <20210824005356.630888-1-sashal@kernel.org> From: Mark Rutland <mark.rutland@arm.com> [ Upstream commit bde8fff82e4a4b0f000dbf4d5eadab2079be0b56 ] In __init_el2_timers we initialize CNTHCTL_EL2.{EL1PCEN,EL1PCTEN} with a RMW sequence, leaving all other bits UNKNOWN. In general, we should initialize all bits in a register rather than using an RMW sequence, since most bits are UNKNOWN out of reset, and as new bits are added to the reigster their reset value might not result in expected behaviour. In the case of CNTHCTL_EL2, FEAT_ECV added a number of new control bits in previously RES0 bits, which reset to UNKNOWN values, and may cause issues for EL1 and EL0: * CNTHCTL_EL2.ECV enables the CNTPOFF_EL2 offset (which itself resets to an UNKNOWN value) at EL0 and EL1. Since the offset could reset to distinct values across CPUs, when the control bit resets to 1 this could break timekeeping generally. * CNTHCTL_EL2.{EL1TVT,EL1TVCT} trap EL0 and EL1 accesses to the EL1 virtual timer/counter registers to EL2. When reset to 1, this could cause unexpected traps to EL2. Initializing these bits to zero avoids these problems, and all other bits in CNTHCTL_EL2 other than EL1PCEN and EL1PCTEN can safely be reset to zero. This patch ensures we initialize CNTHCTL_EL2 accordingly, only setting EL1PCEN and EL1PCTEN, and setting all other bits to zero. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Oliver Upton <oupton@google.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Oliver Upton <oupton@google.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210818161535.52786-1-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> --- arch/arm64/include/asm/el2_setup.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 21fa330f498d..b83fb24954b7 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -33,8 +33,7 @@ * EL2. */ .macro __init_el2_timers - mrs x0, cnthctl_el2 - orr x0, x0, #3 // Enable EL1 physical timers + mov x0, #3 // Enable EL1 physical timers msr cnthctl_el2, x0 msr cntvoff_el2, xzr // Clear virtual offset .endm -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-24 0:56 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-24 0:53 [PATCH AUTOSEL 5.13 01/26] iwlwifi: pnvm: accept multiple HW-type TLVs Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 02/26] iwlwifi: add new SoF with JF devices Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 03/26] iwlwifi: add new so-jf devices Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 04/26] opp: remove WARN when no valid OPPs remain Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 05/26] cpufreq: blocklist Qualcomm sm8150 in cpufreq-dt-platdev Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 06/26] virtio: Improve vq->broken access to avoid any compiler optimization Sasha Levin 2021-08-24 0:53 ` Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 07/26] virtio_pci: Support surprise removal of virtio pci device Sasha Levin 2021-08-24 0:53 ` Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 08/26] virtio_vdpa: reject invalid vq indices Sasha Levin 2021-08-24 0:53 ` Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 09/26] vringh: Use wiov->used to check for read/write desc order Sasha Levin 2021-08-24 0:53 ` Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 10/26] tools/virtio: fix build Sasha Levin 2021-08-24 0:53 ` Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 11/26] platform/x86: asus-nb-wmi: Allow configuring SW_TABLET_MODE method with a module option Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 12/26] platform/x86: asus-nb-wmi: Add tablet_mode_sw=lid-flip quirk for the TP200s Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 13/26] qed: qed ll2 race condition fixes Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 14/26] qed: Fix null-pointer dereference in qed_rdma_create_qp() Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 15/26] Revert "drm/amd/pm: fix workload mismatch on vega10" Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 16/26] drm/amd/pm: change the workload type for some cards Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 17/26] blk-mq: don't grab rq's refcount in blk_mq_check_expired() Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 18/26] drm: Copy drm_wait_vblank to user before returning Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 19/26] platform/x86: gigabyte-wmi: add support for X570 GAMING X Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 20/26] drm/nouveau: recognise GA107 Sasha Levin 2021-08-24 0:53 ` [Nouveau] " Sasha Levin 2021-08-24 17:08 ` Lyude Paul 2021-08-24 17:08 ` Lyude Paul 2021-08-24 17:08 ` Lyude Paul 2021-08-30 12:17 ` Sasha Levin 2021-08-30 12:17 ` [Nouveau] " Sasha Levin 2021-08-30 17:08 ` Lyude Paul 2021-08-30 17:08 ` Lyude Paul 2021-08-30 17:08 ` [Nouveau] " Lyude Paul 2021-08-30 17:09 ` Lyude Paul 2021-08-30 17:09 ` Lyude Paul 2021-08-30 17:09 ` [Nouveau] " Lyude Paul 2021-08-30 21:55 ` Sasha Levin 2021-08-30 21:55 ` [Nouveau] " Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 21/26] drm/nouveau/disp: power down unused DP links during init Sasha Levin 2021-08-24 0:53 ` [Nouveau] " Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 22/26] drm/nouveau/kms/nv50: workaround EFI GOP window channel format differences Sasha Levin 2021-08-24 0:53 ` [Nouveau] " Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 23/26] drm/nouveau: block a bunch of classes from userspace Sasha Levin 2021-08-24 0:53 ` [Nouveau] " Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 24/26] platform/x86: gigabyte-wmi: add support for B450M S2H V2 Sasha Levin 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 25/26] net/rds: dma_map_sg is entitled to merge entries Sasha Levin 2021-08-24 0:53 ` Sasha Levin [this message] 2021-08-24 0:53 ` [PATCH AUTOSEL 5.13 26/26] arm64: initialize all of CNTHCTL_EL2 Sasha Levin
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