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From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support
Date: Mon, 30 Aug 2021 09:47:24 +0530	[thread overview]
Message-ID: <20210830041729.237252-7-anup.patel@wdc.com> (raw)
In-Reply-To: <20210830041729.237252-1-anup.patel@wdc.com>

The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means
we have to create a IPI interrupt domain to use CLINT IPI functionality
hence requiring a "interrupt-controller" and "#interrupt-cells" DT
property in CLINT DT nodes.

Impact of this CLINT DT bindings change only affects Linux RISC-V
NoMMU kernel and has no effect of existing M-mode runtime firmwares
(i.e. OpenSBI).

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../bindings/timer/sifive,clint.yaml          | 20 ++++++++++++++-----
 arch/riscv/boot/dts/canaan/k210.dtsi          |  2 ++
 .../boot/dts/microchip/microchip-mpfs.dtsi    |  2 ++
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index a35952f48742..9c8ef9f4094f 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -43,6 +43,12 @@ properties:
 
   interrupts-extended:
     minItems: 1
+    maxItems: 4095
+
+  "#interrupt-cells":
+    const: 0
+
+  interrupt-controller: true
 
 additionalProperties: false
 
@@ -50,15 +56,19 @@ required:
   - compatible
   - reg
   - interrupts-extended
+  - interrupt-controller
+  - "#interrupt-cells"
 
 examples:
   - |
     timer@2000000 {
       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
-      interrupts-extended = <&cpu1intc 3 &cpu1intc 7
-                             &cpu2intc 3 &cpu2intc 7
-                             &cpu3intc 3 &cpu3intc 7
-                             &cpu4intc 3 &cpu4intc 7>;
-       reg = <0x2000000 0x10000>;
+      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
+                            <&cpu2intc 3>, <&cpu2intc 7>,
+                            <&cpu3intc 3>, <&cpu3intc 7>,
+                            <&cpu4intc 3>, <&cpu4intc 7>;
+      reg = <0x2000000 0x10000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
     };
 ...
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5e8ca8142482..67dcda1efadb 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -105,6 +105,8 @@ clint0: timer@2000000 {
 			reg = <0x2000000 0xC000>;
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 					      &cpu1_intc 3 &cpu1_intc 7>;
+			#interrupt-cells = <0>;
+			interrupt-controller;
 		};
 
 		plic0: interrupt-controller@c000000 {
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b9819570a7d1..67fb41439f20 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7
 						&cpu2_intc 3 &cpu2_intc 7
 						&cpu3_intc 3 &cpu3_intc 7
 						&cpu4_intc 3 &cpu4_intc 7>;
+			#interrupt-cells = <0>;
+			interrupt-controller;
 		};
 
 		plic: interrupt-controller@c000000 {
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support
Date: Mon, 30 Aug 2021 09:47:24 +0530	[thread overview]
Message-ID: <20210830041729.237252-7-anup.patel@wdc.com> (raw)
In-Reply-To: <20210830041729.237252-1-anup.patel@wdc.com>

The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means
we have to create a IPI interrupt domain to use CLINT IPI functionality
hence requiring a "interrupt-controller" and "#interrupt-cells" DT
property in CLINT DT nodes.

Impact of this CLINT DT bindings change only affects Linux RISC-V
NoMMU kernel and has no effect of existing M-mode runtime firmwares
(i.e. OpenSBI).

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../bindings/timer/sifive,clint.yaml          | 20 ++++++++++++++-----
 arch/riscv/boot/dts/canaan/k210.dtsi          |  2 ++
 .../boot/dts/microchip/microchip-mpfs.dtsi    |  2 ++
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index a35952f48742..9c8ef9f4094f 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -43,6 +43,12 @@ properties:
 
   interrupts-extended:
     minItems: 1
+    maxItems: 4095
+
+  "#interrupt-cells":
+    const: 0
+
+  interrupt-controller: true
 
 additionalProperties: false
 
@@ -50,15 +56,19 @@ required:
   - compatible
   - reg
   - interrupts-extended
+  - interrupt-controller
+  - "#interrupt-cells"
 
 examples:
   - |
     timer@2000000 {
       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
-      interrupts-extended = <&cpu1intc 3 &cpu1intc 7
-                             &cpu2intc 3 &cpu2intc 7
-                             &cpu3intc 3 &cpu3intc 7
-                             &cpu4intc 3 &cpu4intc 7>;
-       reg = <0x2000000 0x10000>;
+      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
+                            <&cpu2intc 3>, <&cpu2intc 7>,
+                            <&cpu3intc 3>, <&cpu3intc 7>,
+                            <&cpu4intc 3>, <&cpu4intc 7>;
+      reg = <0x2000000 0x10000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
     };
 ...
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5e8ca8142482..67dcda1efadb 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -105,6 +105,8 @@ clint0: timer@2000000 {
 			reg = <0x2000000 0xC000>;
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 					      &cpu1_intc 3 &cpu1_intc 7>;
+			#interrupt-cells = <0>;
+			interrupt-controller;
 		};
 
 		plic0: interrupt-controller@c000000 {
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b9819570a7d1..67fb41439f20 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7
 						&cpu2_intc 3 &cpu2_intc 7
 						&cpu3_intc 3 &cpu3_intc 7
 						&cpu4_intc 3 &cpu4_intc 7>;
+			#interrupt-cells = <0>;
+			interrupt-controller;
 		};
 
 		plic: interrupt-controller@c000000 {
-- 
2.25.1


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  parent reply	other threads:[~2021-08-30  4:18 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-30  4:17 [RFC PATCH v3 00/11] Linux RISC-V ACLINT Support Anup Patel
2021-08-30  4:17 ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 01/11] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 02/11] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 03/11] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 04/11] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 05/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-09-01  1:24   ` Rob Herring
2021-09-01  1:24     ` Rob Herring
2021-09-01 11:56     ` Anup Patel
2021-09-01 11:56       ` Anup Patel
2021-09-02  0:33       ` Rob Herring
2021-09-02  0:33         ` Rob Herring
2021-09-03 10:40         ` Anup Patel
2021-09-03 10:40           ` Anup Patel
2021-09-07 13:48           ` Rob Herring
2021-09-07 13:48             ` Rob Herring
2021-08-30  4:17 ` Anup Patel [this message]
2021-08-30  4:17   ` [RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support Anup Patel
2021-09-01  1:29   ` Rob Herring
2021-09-01  1:29     ` Rob Herring
2021-09-01 12:00     ` Anup Patel
2021-09-01 12:00       ` Anup Patel
2021-09-02  0:18       ` Rob Herring
2021-09-02  0:18         ` Rob Herring
2021-09-02  5:37         ` Anup Patel
2021-09-02  5:37           ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 07/11] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 08/11] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 09/11] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-09-01  1:31   ` Rob Herring
2021-09-01  1:31     ` Rob Herring
2021-08-30  4:17 ` [RFC PATCH v3 10/11] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-08-30  4:17   ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 11/11] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
2021-08-30  4:17   ` Anup Patel

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