From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> To: intel-gfx@lists.freedesktop.org, Lionel G Landwerlin <lionel.g.landwerlin@intel.com>, Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: dri-devel@lists.freedesktop.org, daniel.vetter@ffwll.ch, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, jason@jlekstrand.net Subject: [PATCH 2/8] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Date: Mon, 30 Aug 2021 12:38:45 -0700 [thread overview] Message-ID: <20210830193851.15607-3-umesh.nerlige.ramappa@intel.com> (raw) In-Reply-To: <20210830193851.15607-1-umesh.nerlige.ramappa@intel.com> From: Chris Wilson <chris.p.wilson@intel.com> Switch the search and grow code of the _wa_add to use _wa_index and _wa_list_grow. Signed-off-by: Chris Wilson <chris.p.wilson@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 124 +++++++++++--------- 1 file changed, 71 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2a8cc0e2d1b1..6928f250cafe 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -60,20 +60,19 @@ static void wa_init_start(struct i915_wa_list *wal, const char *name, const char #define WA_LIST_CHUNK (1 << 4) -static void wa_init_finish(struct i915_wa_list *wal) +static void wa_trim(struct i915_wa_list *wal, gfp_t gfp) { + struct i915_wa *list; + /* Trim unused entries. */ - if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { - struct i915_wa *list = kmemdup(wal->list, - wal->count * sizeof(*list), - GFP_KERNEL); - - if (list) { - kfree(wal->list); - wal->list = list; - } - } + list = krealloc(wal->list, wal->count * sizeof(*list), gfp); + if (list) + wal->list = list; +} +static void wa_init_finish(struct i915_wa_list *wal) +{ + wa_trim(wal, GFP_KERNEL); if (!wal->count) return; @@ -81,57 +80,60 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } -static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) +static int wa_index(struct i915_wa_list *wal, i915_reg_t reg) { - unsigned int addr = i915_mmio_reg_offset(wa->reg); - unsigned int start = 0, end = wal->count; - const unsigned int grow = WA_LIST_CHUNK; - struct i915_wa *wa_; + unsigned int addr = i915_mmio_reg_offset(reg); + int start = 0, end = wal->count; - GEM_BUG_ON(!is_power_of_2(grow)); + /* addr and wal->list[].reg, both include the R/W flags */ + while (start < end) { + unsigned int mid = start + (end - start) / 2; - if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ - struct i915_wa *list; + if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) + start = mid + 1; + else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) + end = mid; + else + return mid; + } - list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), - GFP_KERNEL); - if (!list) { - DRM_ERROR("No space for workaround init!\n"); - return; - } + return -ENOENT; +} - if (wal->list) { - memcpy(list, wal->list, sizeof(*wa) * wal->count); - kfree(wal->list); - } +static int wa_list_grow(struct i915_wa_list *wal, size_t count, gfp_t gfp) +{ + struct i915_wa *list; - wal->list = list; - } + list = krealloc(wal->list, count * sizeof(*list), gfp); + if (!list) + return -ENOMEM; - while (start < end) { - unsigned int mid = start + (end - start) / 2; + wal->list = list; + return 0; +} - if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { - start = mid + 1; - } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { - end = mid; - } else { - wa_ = &wal->list[mid]; - - if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { - DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), - wa_->clr, wa_->set); - - wa_->set &= ~wa->clr; - } - - wal->wa_count++; - wa_->set |= wa->set; - wa_->clr |= wa->clr; - wa_->read |= wa->read; - return; +static void __wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) +{ + struct i915_wa *wa_; + int index; + + index = wa_index(wal, wa->reg); + if (index >= 0) { + wa_ = &wal->list[index]; + + if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { + DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", + i915_mmio_reg_offset(wa_->reg), + wa_->clr, wa_->set); + + wa_->set &= ~wa->clr; } + + wal->wa_count++; + wa_->set |= wa->set; + wa_->clr |= wa->clr; + wa_->read |= wa->read; + return; } wal->wa_count++; @@ -149,6 +151,22 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) } } +static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) +{ + const unsigned int grow = WA_LIST_CHUNK; + + GEM_BUG_ON(!is_power_of_2(grow)); + + if (IS_ALIGNED(wal->count, grow) && /* Either uninitialized or full. */ + wa_list_grow(wal, ALIGN(wal->count + 1, grow), GFP_KERNEL)) { + DRM_ERROR("Unable to store w/a for reg %04x\n", + i915_mmio_reg_offset(wa->reg)); + return; + } + + __wa_add(wal, wa); +} + static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set, u32 read_mask, bool masked_reg) { -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> To: intel-gfx@lists.freedesktop.org, Lionel G Landwerlin <lionel.g.landwerlin@intel.com>, Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: dri-devel@lists.freedesktop.org, daniel.vetter@ffwll.ch, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, jason@jlekstrand.net Subject: [Intel-gfx] [PATCH 2/8] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Date: Mon, 30 Aug 2021 12:38:45 -0700 [thread overview] Message-ID: <20210830193851.15607-3-umesh.nerlige.ramappa@intel.com> (raw) In-Reply-To: <20210830193851.15607-1-umesh.nerlige.ramappa@intel.com> From: Chris Wilson <chris.p.wilson@intel.com> Switch the search and grow code of the _wa_add to use _wa_index and _wa_list_grow. Signed-off-by: Chris Wilson <chris.p.wilson@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 124 +++++++++++--------- 1 file changed, 71 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2a8cc0e2d1b1..6928f250cafe 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -60,20 +60,19 @@ static void wa_init_start(struct i915_wa_list *wal, const char *name, const char #define WA_LIST_CHUNK (1 << 4) -static void wa_init_finish(struct i915_wa_list *wal) +static void wa_trim(struct i915_wa_list *wal, gfp_t gfp) { + struct i915_wa *list; + /* Trim unused entries. */ - if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { - struct i915_wa *list = kmemdup(wal->list, - wal->count * sizeof(*list), - GFP_KERNEL); - - if (list) { - kfree(wal->list); - wal->list = list; - } - } + list = krealloc(wal->list, wal->count * sizeof(*list), gfp); + if (list) + wal->list = list; +} +static void wa_init_finish(struct i915_wa_list *wal) +{ + wa_trim(wal, GFP_KERNEL); if (!wal->count) return; @@ -81,57 +80,60 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } -static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) +static int wa_index(struct i915_wa_list *wal, i915_reg_t reg) { - unsigned int addr = i915_mmio_reg_offset(wa->reg); - unsigned int start = 0, end = wal->count; - const unsigned int grow = WA_LIST_CHUNK; - struct i915_wa *wa_; + unsigned int addr = i915_mmio_reg_offset(reg); + int start = 0, end = wal->count; - GEM_BUG_ON(!is_power_of_2(grow)); + /* addr and wal->list[].reg, both include the R/W flags */ + while (start < end) { + unsigned int mid = start + (end - start) / 2; - if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ - struct i915_wa *list; + if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) + start = mid + 1; + else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) + end = mid; + else + return mid; + } - list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), - GFP_KERNEL); - if (!list) { - DRM_ERROR("No space for workaround init!\n"); - return; - } + return -ENOENT; +} - if (wal->list) { - memcpy(list, wal->list, sizeof(*wa) * wal->count); - kfree(wal->list); - } +static int wa_list_grow(struct i915_wa_list *wal, size_t count, gfp_t gfp) +{ + struct i915_wa *list; - wal->list = list; - } + list = krealloc(wal->list, count * sizeof(*list), gfp); + if (!list) + return -ENOMEM; - while (start < end) { - unsigned int mid = start + (end - start) / 2; + wal->list = list; + return 0; +} - if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { - start = mid + 1; - } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { - end = mid; - } else { - wa_ = &wal->list[mid]; - - if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { - DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), - wa_->clr, wa_->set); - - wa_->set &= ~wa->clr; - } - - wal->wa_count++; - wa_->set |= wa->set; - wa_->clr |= wa->clr; - wa_->read |= wa->read; - return; +static void __wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) +{ + struct i915_wa *wa_; + int index; + + index = wa_index(wal, wa->reg); + if (index >= 0) { + wa_ = &wal->list[index]; + + if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { + DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", + i915_mmio_reg_offset(wa_->reg), + wa_->clr, wa_->set); + + wa_->set &= ~wa->clr; } + + wal->wa_count++; + wa_->set |= wa->set; + wa_->clr |= wa->clr; + wa_->read |= wa->read; + return; } wal->wa_count++; @@ -149,6 +151,22 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) } } +static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) +{ + const unsigned int grow = WA_LIST_CHUNK; + + GEM_BUG_ON(!is_power_of_2(grow)); + + if (IS_ALIGNED(wal->count, grow) && /* Either uninitialized or full. */ + wa_list_grow(wal, ALIGN(wal->count + 1, grow), GFP_KERNEL)) { + DRM_ERROR("Unable to store w/a for reg %04x\n", + i915_mmio_reg_offset(wa->reg)); + return; + } + + __wa_add(wal, wa); +} + static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set, u32 read_mask, bool masked_reg) { -- 2.20.1
next prev parent reply other threads:[~2021-08-30 19:39 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-30 19:38 [PATCH 0/8] Enable triggered perf query for Xe_HP Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [PATCH 1/8] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa [this message] 2021-08-30 19:38 ` [Intel-gfx] [PATCH 2/8] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Umesh Nerlige Ramappa 2021-08-30 19:38 ` [PATCH 3/8] drm/i915/gt: Check for conflicting RING_NONPRIV Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-31 3:39 ` kernel test robot 2021-08-31 3:39 ` kernel test robot 2021-08-30 19:38 ` [PATCH 4/8] drm/i915/gt: Enable dynamic adjustment of RING_NONPRIV Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] [PATCH 5/8] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] [PATCH 6/8] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa 2021-08-30 19:38 ` [PATCH 7/8] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 19:38 ` [Intel-gfx] [PATCH 8/8] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa 2021-08-30 19:38 ` Umesh Nerlige Ramappa 2021-08-31 12:55 ` Daniel Vetter 2021-08-31 12:55 ` [Intel-gfx] " Daniel Vetter 2021-08-31 20:35 ` Umesh Nerlige Ramappa 2021-08-31 20:35 ` [Intel-gfx] " Umesh Nerlige Ramappa 2021-08-30 22:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable triggered perf query for Xe_HP (rev2) Patchwork -- strict thread matches above, loose matches on Subject: below -- 2021-08-03 20:13 [PATCH 0/8] Enable triggered perf query for Xe_HP Umesh Nerlige Ramappa 2021-08-03 20:13 ` [PATCH 2/8] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Umesh Nerlige Ramappa
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