* [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX
2021-08-31 8:29 [PATCH v6 0/3] Add support for Fujitsu A64FX processor Shuuichirou Ishii
@ 2021-08-31 8:29 ` Shuuichirou Ishii
2021-08-31 10:20 ` Andrew Jones
2021-08-31 8:29 ` [PATCH v6 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Shuuichirou Ishii
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Shuuichirou Ishii @ 2021-08-31 8:29 UTC (permalink / raw)
To: peter.maydell, drjones, qemu-arm; +Cc: qemu-devel, ishii.shuuichir
Add a definition for the Fujitsu A64FX processor.
The A64FX processor does not implement the AArch32 Execution state,
so there are no associated AArch32 Identification registers.
For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths.
The Identification registers value are defined based on the FX700,
and have been tested and confirmed.
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
---
target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 2f0cbddab5..15245a60a8 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -841,10 +841,58 @@ static void aarch64_max_initfn(Object *obj)
cpu_max_set_sve_max_vq, NULL, NULL);
}
+static void aarch64_a64fx_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,a64fx";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x461f0010;
+ cpu->revidr = 0x00000000;
+ cpu->ctr = 0x86668006;
+ cpu->reset_sctlr = 0x30000180;
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+ cpu->id_aa64afr0 = 0x0000000000000000;
+ cpu->id_aa64afr1 = 0x0000000000000000;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+ cpu->clidr = 0x0000000080000023;
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
+ cpu->dcz_blocksize = 6; /* 256 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+
+ /* Suppport of A64FX's vector length are 128,256 and 512bit only */
+ aarch64_add_sve_properties(obj);
+ bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ);
+ set_bit(0, cpu->sve_vq_supported); /* 128bit */
+ set_bit(1, cpu->sve_vq_supported); /* 256bit */
+ set_bit(3, cpu->sve_vq_supported); /* 512bit */
+
+ /* TODO: Add A64FX specific HPC extension registers */
+}
+
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
+ { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
};
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX
2021-08-31 8:29 ` [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX Shuuichirou Ishii
@ 2021-08-31 10:20 ` Andrew Jones
2021-09-01 6:31 ` ishii.shuuichir
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Jones @ 2021-08-31 10:20 UTC (permalink / raw)
To: Shuuichirou Ishii; +Cc: peter.maydell, qemu-arm, qemu-devel
On Tue, Aug 31, 2021 at 05:29:38PM +0900, Shuuichirou Ishii wrote:
> Add a definition for the Fujitsu A64FX processor.
>
> The A64FX processor does not implement the AArch32 Execution state,
> so there are no associated AArch32 Identification registers.
>
> For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths.
>
> The Identification registers value are defined based on the FX700,
> and have been tested and confirmed.
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
> target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
I already gave my r-b on the last posting, but here it is again
Reviewed-by: Andrew Jones <drjones@redhat.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX
2021-08-31 10:20 ` Andrew Jones
@ 2021-09-01 6:31 ` ishii.shuuichir
0 siblings, 0 replies; 7+ messages in thread
From: ishii.shuuichir @ 2021-09-01 6:31 UTC (permalink / raw)
To: 'Andrew Jones'
Cc: peter.maydell, qemu-arm, qemu-devel, ishii.shuuichir
> I already gave my r-b on the last posting, but here it is again
>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
Sorry, We overlooked that.
Thank you:)
Best regards,
> -----Original Message-----
> From: Andrew Jones <drjones@redhat.com>
> Sent: Tuesday, August 31, 2021 7:20 PM
> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> Cc: peter.maydell@linaro.org; qemu-arm@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX
>
> On Tue, Aug 31, 2021 at 05:29:38PM +0900, Shuuichirou Ishii wrote:
> > Add a definition for the Fujitsu A64FX processor.
> >
> > The A64FX processor does not implement the AArch32 Execution state, so
> > there are no associated AArch32 Identification registers.
> >
> > For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths.
> >
> > The Identification registers value are defined based on the FX700, and
> > have been tested and confirmed.
> >
> > Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> > ---
> > target/arm/cpu64.c | 48
> > ++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 48 insertions(+)
> >
>
> I already gave my r-b on the last posting, but here it is again
>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v6 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine
2021-08-31 8:29 [PATCH v6 0/3] Add support for Fujitsu A64FX processor Shuuichirou Ishii
2021-08-31 8:29 ` [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX Shuuichirou Ishii
@ 2021-08-31 8:29 ` Shuuichirou Ishii
2021-08-31 8:29 ` [PATCH v6 3/3] tests/arm-cpu-features: Add A64FX processor related Shuuichirou Ishii
2021-09-01 8:23 ` [PATCH v6 0/3] Add support for Fujitsu A64FX processor Peter Maydell
3 siblings, 0 replies; 7+ messages in thread
From: Shuuichirou Ishii @ 2021-08-31 8:29 UTC (permalink / raw)
To: peter.maydell, drjones, qemu-arm; +Cc: qemu-devel, ishii.shuuichir
Add -cpu a64fx to use A64FX processor when -machine virt option is specified.
In addition, add a64fx to the Supported guest CPU types in the virt.rst document.
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 59acf0eeaf..850787495b 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -55,6 +55,7 @@ Supported guest CPU types:
- ``cortex-a53`` (64-bit)
- ``cortex-a57`` (64-bit)
- ``cortex-a72`` (64-bit)
+- ``a64fx`` (64-bit)
- ``host`` (with KVM only)
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 86c8a4ca3d..3fa4295a78 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -200,6 +200,7 @@ static const char *valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
+ ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("host"),
ARM_CPU_TYPE_NAME("max"),
};
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v6 3/3] tests/arm-cpu-features: Add A64FX processor related
2021-08-31 8:29 [PATCH v6 0/3] Add support for Fujitsu A64FX processor Shuuichirou Ishii
2021-08-31 8:29 ` [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX Shuuichirou Ishii
2021-08-31 8:29 ` [PATCH v6 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Shuuichirou Ishii
@ 2021-08-31 8:29 ` Shuuichirou Ishii
2021-09-01 8:23 ` [PATCH v6 0/3] Add support for Fujitsu A64FX processor Peter Maydell
3 siblings, 0 replies; 7+ messages in thread
From: Shuuichirou Ishii @ 2021-08-31 8:29 UTC (permalink / raw)
To: peter.maydell, drjones, qemu-arm; +Cc: qemu-devel, ishii.shuuichir
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
tests/qtest/arm-cpu-features.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 8252b85bb8..90a87f0ea9 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -473,6 +473,19 @@ static void test_query_cpu_model_expansion(const void *data)
assert_has_feature_enabled(qts, "cortex-a57", "pmu");
assert_has_feature_enabled(qts, "cortex-a57", "aarch64");
+ assert_has_feature_enabled(qts, "a64fx", "pmu");
+ assert_has_feature_enabled(qts, "a64fx", "aarch64");
+ /*
+ * A64FX does not support any other vector lengths besides those
+ * that are enabled by default(128bit, 256bits, 512bit).
+ */
+ assert_has_feature_enabled(qts, "a64fx", "sve");
+ assert_sve_vls(qts, "a64fx", 0xb, NULL);
+ assert_error(qts, "a64fx", "cannot enable sve384",
+ "{ 'sve384': true }");
+ assert_error(qts, "a64fx", "cannot enable sve640",
+ "{ 'sve640': true }");
+
sve_tests_default(qts, "max");
pauth_tests_default(qts, "max");
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v6 0/3] Add support for Fujitsu A64FX processor
2021-08-31 8:29 [PATCH v6 0/3] Add support for Fujitsu A64FX processor Shuuichirou Ishii
` (2 preceding siblings ...)
2021-08-31 8:29 ` [PATCH v6 3/3] tests/arm-cpu-features: Add A64FX processor related Shuuichirou Ishii
@ 2021-09-01 8:23 ` Peter Maydell
3 siblings, 0 replies; 7+ messages in thread
From: Peter Maydell @ 2021-09-01 8:23 UTC (permalink / raw)
To: Shuuichirou Ishii; +Cc: Andrew Jones, qemu-arm, QEMU Developers
On Tue, 31 Aug 2021 at 09:29, Shuuichirou Ishii
<ishii.shuuichir@fujitsu.com> wrote:
>
> This is the v6 patch series.
>
> v6:
> For patch 1[1/3], added the commit messages that the Identification registers
> value are defined based on FX700, and has been tested and confirmed.
Applied to target-arm.next. Thanks!
-- PMM
^ permalink raw reply [flat|nested] 7+ messages in thread