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From: Maxime Ripard <maxime@cerno.tech>
To: devicetree@vger.kernel.org, "Rob Herring" <robh+dt@kernel.org>,
	"Frank Rowand" <frowand.list@gmail.com>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Maxime Ripard" <maxime@cerno.tech>,
	"Jernej Škrabec" <jernej.skrabec@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-sunxi@googlegroups.com,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: [PATCH v2 06/52] dt-bindings: arm: Convert ARM CCI-400 binding to a schema
Date: Wed,  1 Sep 2021 11:18:06 +0200	[thread overview]
Message-ID: <20210901091852.479202-7-maxime@cerno.tech> (raw)
In-Reply-To: <20210901091852.479202-1-maxime@cerno.tech>

The ARM CCI-400 Interconnect is supported by Linux thanks to its device
tree binding.

Now that we have the DT validation in place, let's convert the device
tree bindings for that driver over to a YAML schema.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

---

Changes from v1:
  - Reduced the max number of interrupts
  - Comented the pl330 compatible to avoid a warning
  - Added cci-control-port to the cpus schemas
---
 .../devicetree/bindings/arm/arm,cci-400.yaml  | 216 +++++++++++++++++
 .../bindings/arm/cci-control-port.yaml        |  38 +++
 Documentation/devicetree/bindings/arm/cci.txt | 224 ------------------
 .../devicetree/bindings/arm/cpus.yaml         |   2 +
 4 files changed, 256 insertions(+), 224 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,cci-400.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/cci-control-port.yaml
 delete mode 100644 Documentation/devicetree/bindings/arm/cci.txt

diff --git a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
new file mode 100644
index 000000000000..4682f991a5c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM CCI Cache Coherent Interconnect Device Tree Binding
+
+maintainers:
+  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+
+description: >
+  ARM multi-cluster systems maintain intra-cluster coherency through a cache
+  coherent interconnect (CCI) that is capable of monitoring bus transactions
+  and manage coherency, TLB invalidations and memory barriers.
+
+  It allows snooping and distributed virtual memory message broadcast across
+  clusters, through memory mapped interface, with a global control register
+  space and multiple sets of interface control registers, one per slave
+  interface.
+
+properties:
+  $nodename:
+    pattern: "^cci(@[0-9a-f]+)?$"
+
+  compatible:
+    enum:
+      - arm,cci-400
+      - arm,cci-500
+      - arm,cci-550
+
+  reg:
+    maxItems: 1
+    description: >
+      Specifies base physical address of CCI control registers common to all
+      interfaces.
+
+  "#address-cells": true
+  "#size-cells": true
+  ranges: true
+
+patternProperties:
+  "^slave-if@[0-9a-f]+$":
+    type: object
+
+    properties:
+      compatible:
+        const: arm,cci-400-ctrl-if
+
+      interface-type:
+        enum:
+          - ace
+          - ace-lite
+
+      reg:
+        maxItems: 1
+
+    required:
+      - compatible
+      - interface-type
+      - reg
+
+    additionalProperties: false
+
+  "^pmu@[0-9a-f]+$":
+    type: object
+
+    properties:
+      compatible:
+        oneOf:
+          - const: arm,cci-400-pmu,r0
+          - const: arm,cci-400-pmu,r1
+          - const: arm,cci-400-pmu
+            deprecated: true
+            description: >
+              Permitted only where OS has secure access to CCI registers
+          - const: arm,cci-500-pmu,r0
+          - const: arm,cci-550-pmu,r0
+
+      interrupts:
+        minItems: 1
+        maxItems: 8
+        description: >
+          List of counter overflow interrupts, one per counter. The interrupts
+          must be specified starting with the cycle counter overflow interrupt,
+          followed by counter0 overflow interrupt, counter1 overflow
+          interrupt,...  ,counterN overflow interrupt.
+
+          The CCI PMU has an interrupt signal for each counter. The number of
+          interrupts must be equal to the number of counters.
+
+      reg:
+        maxItems: 1
+
+    required:
+      - compatible
+      - interrupts
+      - reg
+
+    additionalProperties: false
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - ranges
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+      / {
+          #address-cells = <2>;
+          #size-cells = <2>;
+
+          compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
+          model = "V2P-CA15_CA7";
+          arm,hbi = <0x249>;
+          interrupt-parent = <&gic>;
+
+          /*
+           * This CCI node corresponds to a CCI component whose control
+           * registers sits at address 0x000000002c090000.
+           *
+           * CCI slave interface @0x000000002c091000 is connected to dma
+           * controller dma0.
+           *
+           * CCI slave interface @0x000000002c094000 is connected to CPUs
+           * {CPU0, CPU1};
+           *
+           * CCI slave interface @0x000000002c095000 is connected to CPUs
+           * {CPU2, CPU3};
+           */
+
+          cpus {
+              #size-cells = <0>;
+              #address-cells = <1>;
+
+              CPU0: cpu@0 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a15";
+                  cci-control-port = <&cci_control1>;
+                  reg = <0x0>;
+              };
+
+              CPU1: cpu@1 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a15";
+                  cci-control-port = <&cci_control1>;
+                  reg = <0x1>;
+              };
+
+              CPU2: cpu@100 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a7";
+                  cci-control-port = <&cci_control2>;
+                  reg = <0x100>;
+              };
+
+              CPU3: cpu@101 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a7";
+                  cci-control-port = <&cci_control2>;
+                  reg = <0x101>;
+              };
+          };
+
+          dma0: dma@3000000 {
+              /* compatible = "arm,pl330", "arm,primecell"; */
+              cci-control-port = <&cci_control0>;
+              reg = <0x0 0x3000000 0x0 0x1000>;
+              interrupts = <10>;
+              #dma-cells = <1>;
+              #dma-channels = <8>;
+              #dma-requests = <32>;
+          };
+
+          cci@2c090000 {
+              compatible = "arm,cci-400";
+              #address-cells = <1>;
+              #size-cells = <1>;
+              reg = <0x0 0x2c090000 0 0x1000>;
+              ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+              cci_control0: slave-if@1000 {
+                  compatible = "arm,cci-400-ctrl-if";
+                  interface-type = "ace-lite";
+                  reg = <0x1000 0x1000>;
+              };
+
+              cci_control1: slave-if@4000 {
+                  compatible = "arm,cci-400-ctrl-if";
+                  interface-type = "ace";
+                  reg = <0x4000 0x1000>;
+              };
+
+              cci_control2: slave-if@5000 {
+                  compatible = "arm,cci-400-ctrl-if";
+                  interface-type = "ace";
+                  reg = <0x5000 0x1000>;
+              };
+
+              pmu@9000 {
+                  compatible = "arm,cci-400-pmu";
+                  reg = <0x9000 0x5000>;
+                  interrupts = <0 101 4>,
+                    <0 102 4>,
+                    <0 103 4>,
+                    <0 104 4>,
+                    <0 105 4>;
+              };
+          };
+      };
+
+...
diff --git a/Documentation/devicetree/bindings/arm/cci-control-port.yaml b/Documentation/devicetree/bindings/arm/cci-control-port.yaml
new file mode 100644
index 000000000000..c9114866213f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci-control-port.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CCI Interconnect Bus Masters binding
+
+maintainers:
+  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+
+description: |
+  Masters in the device tree connected to a CCI port (inclusive of CPUs
+  and their cpu nodes).
+
+select: true
+
+properties:
+  cci-control-port:
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+additionalProperties: true
+
+examples:
+  - |
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        cpu@0 {
+            compatible = "arm,cortex-a15";
+            device_type = "cpu";
+            cci-control-port = <&cci_control1>;
+            reg = <0>;
+        };
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
deleted file mode 100644
index 9600761f2d5b..000000000000
--- a/Documentation/devicetree/bindings/arm/cci.txt
+++ /dev/null
@@ -1,224 +0,0 @@
-=======================================================
-ARM CCI cache coherent interconnect binding description
-=======================================================
-
-ARM multi-cluster systems maintain intra-cluster coherency through a
-cache coherent interconnect (CCI) that is capable of monitoring bus
-transactions and manage coherency, TLB invalidations and memory barriers.
-
-It allows snooping and distributed virtual memory message broadcast across
-clusters, through memory mapped interface, with a global control register
-space and multiple sets of interface control registers, one per slave
-interface.
-
-* CCI interconnect node
-
-	Description: Describes a CCI cache coherent Interconnect component
-
-	Node name must be "cci".
-	Node's parent must be the root node /, and the address space visible
-	through the CCI interconnect is the same as the one seen from the
-	root node (ie from CPUs perspective as per DT standard).
-	Every CCI node has to define the following properties:
-
-	- compatible
-		Usage: required
-		Value type: <string>
-		Definition: must contain one of the following:
-			    "arm,cci-400"
-			    "arm,cci-500"
-			    "arm,cci-550"
-
-	- reg
-		Usage: required
-		Value type: Integer cells. A register entry, expressed as a pair
-			    of cells, containing base and size.
-		Definition: A standard property. Specifies base physical
-			    address of CCI control registers common to all
-			    interfaces.
-
-	- ranges:
-		Usage: required
-		Value type: Integer cells. An array of range entries, expressed
-			    as a tuple of cells, containing child address,
-			    parent address and the size of the region in the
-			    child address space.
-		Definition: A standard property. Follow rules in the Devicetree
-			    Specification for hierarchical bus addressing. CCI
-			    interfaces addresses refer to the parent node
-			    addressing scheme to declare their register bases.
-
-	CCI interconnect node can define the following child nodes:
-
-	- CCI control interface nodes
-
-		Node name must be "slave-if".
-		Parent node must be CCI interconnect node.
-
-		A CCI control interface node must contain the following
-		properties:
-
-		- compatible
-			Usage: required
-			Value type: <string>
-			Definition: must be set to
-				    "arm,cci-400-ctrl-if"
-
-		- interface-type:
-			Usage: required
-			Value type: <string>
-			Definition: must be set to one of {"ace", "ace-lite"}
-				    depending on the interface type the node
-				    represents.
-
-		- reg:
-			Usage: required
-			Value type: Integer cells. A register entry, expressed
-				    as a pair of cells, containing base and
-				    size.
-			Definition: the base address and size of the
-				    corresponding interface programming
-				    registers.
-
-	- CCI PMU node
-
-		Parent node must be CCI interconnect node.
-
-		A CCI pmu node must contain the following properties:
-
-		- compatible
-			Usage: required
-			Value type: <string>
-			Definition: Must contain one of:
-				 "arm,cci-400-pmu,r0"
-				 "arm,cci-400-pmu,r1"
-				 "arm,cci-400-pmu"  - DEPRECATED, permitted only where OS has
-						      secure access to CCI registers
-				 "arm,cci-500-pmu,r0"
-				 "arm,cci-550-pmu,r0"
-		- reg:
-			Usage: required
-			Value type: Integer cells. A register entry, expressed
-				    as a pair of cells, containing base and
-				    size.
-			Definition: the base address and size of the
-				    corresponding interface programming
-				    registers.
-
-		- interrupts:
-			Usage: required
-			Value type: Integer cells. Array of interrupt specifier
-				    entries, as defined in
-				    ../interrupt-controller/interrupts.txt.
-			Definition: list of counter overflow interrupts, one per
-				    counter. The interrupts must be specified
-				    starting with the cycle counter overflow
-				    interrupt, followed by counter0 overflow
-				    interrupt, counter1 overflow interrupt,...
-				    ,counterN overflow interrupt.
-
-				    The CCI PMU has an interrupt signal for each
-				    counter. The number of interrupts must be
-				    equal to the number of counters.
-
-* CCI interconnect bus masters
-
-	Description: masters in the device tree connected to a CCI port
-		     (inclusive of CPUs and their cpu nodes).
-
-	A CCI interconnect bus master node must contain the following
-	properties:
-
-	- cci-control-port:
-		Usage: required
-		Value type: <phandle>
-		Definition: a phandle containing the CCI control interface node
-			    the master is connected to.
-
-Example:
-
-	cpus {
-		#size-cells = <0>;
-		#address-cells = <1>;
-
-		CPU0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			cci-control-port = <&cci_control1>;
-			reg = <0x0>;
-		};
-
-		CPU1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			cci-control-port = <&cci_control1>;
-			reg = <0x1>;
-		};
-
-		CPU2: cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			cci-control-port = <&cci_control2>;
-			reg = <0x100>;
-		};
-
-		CPU3: cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			cci-control-port = <&cci_control2>;
-			reg = <0x101>;
-		};
-
-	};
-
-	dma0: dma@3000000 {
-		compatible = "arm,pl330", "arm,primecell";
-		cci-control-port = <&cci_control0>;
-		reg = <0x0 0x3000000 0x0 0x1000>;
-		interrupts = <10>;
-		#dma-cells = <1>;
-		#dma-channels = <8>;
-		#dma-requests = <32>;
-	};
-
-	cci@2c090000 {
-		compatible = "arm,cci-400";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x0 0x2c090000 0 0x1000>;
-		ranges = <0x0 0x0 0x2c090000 0x10000>;
-
-		cci_control0: slave-if@1000 {
-			compatible = "arm,cci-400-ctrl-if";
-			interface-type = "ace-lite";
-			reg = <0x1000 0x1000>;
-		};
-
-		cci_control1: slave-if@4000 {
-			compatible = "arm,cci-400-ctrl-if";
-			interface-type = "ace";
-			reg = <0x4000 0x1000>;
-		};
-
-		cci_control2: slave-if@5000 {
-			compatible = "arm,cci-400-ctrl-if";
-			interface-type = "ace";
-			reg = <0x5000 0x1000>;
-		};
-
-		pmu@9000 {
-			 compatible = "arm,cci-400-pmu";
-			 reg = <0x9000 0x5000>;
-			 interrupts = <0 101 4>,
-				      <0 102 4>,
-				      <0 103 4>,
-				      <0 104 4>,
-				      <0 105 4>;
-		};
-	};
-
-This CCI node corresponds to a CCI component whose control registers sits
-at address 0x000000002c090000.
-CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
-CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
-CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 9a2432a88074..35b552ce8803 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -240,6 +240,8 @@ properties:
       DMIPS/MHz, relative to highest capacity-dmips-mhz
       in the system.
 
+  cci-control-port: true
+
   dynamic-power-coefficient:
     $ref: '/schemas/types.yaml#/definitions/uint32'
     description:
-- 
2.31.1


WARNING: multiple messages have this Message-ID
From: Maxime Ripard <maxime@cerno.tech>
To: devicetree@vger.kernel.org, "Rob Herring" <robh+dt@kernel.org>,
	"Frank Rowand" <frowand.list@gmail.com>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Maxime Ripard" <maxime@cerno.tech>,
	"Jernej Škrabec" <jernej.skrabec@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-sunxi@googlegroups.com,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: [PATCH v2 06/52] dt-bindings: arm: Convert ARM CCI-400 binding to a schema
Date: Wed,  1 Sep 2021 11:18:06 +0200	[thread overview]
Message-ID: <20210901091852.479202-7-maxime@cerno.tech> (raw)
In-Reply-To: <20210901091852.479202-1-maxime@cerno.tech>

The ARM CCI-400 Interconnect is supported by Linux thanks to its device
tree binding.

Now that we have the DT validation in place, let's convert the device
tree bindings for that driver over to a YAML schema.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

---

Changes from v1:
  - Reduced the max number of interrupts
  - Comented the pl330 compatible to avoid a warning
  - Added cci-control-port to the cpus schemas
---
 .../devicetree/bindings/arm/arm,cci-400.yaml  | 216 +++++++++++++++++
 .../bindings/arm/cci-control-port.yaml        |  38 +++
 Documentation/devicetree/bindings/arm/cci.txt | 224 ------------------
 .../devicetree/bindings/arm/cpus.yaml         |   2 +
 4 files changed, 256 insertions(+), 224 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,cci-400.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/cci-control-port.yaml
 delete mode 100644 Documentation/devicetree/bindings/arm/cci.txt

diff --git a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
new file mode 100644
index 000000000000..4682f991a5c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM CCI Cache Coherent Interconnect Device Tree Binding
+
+maintainers:
+  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+
+description: >
+  ARM multi-cluster systems maintain intra-cluster coherency through a cache
+  coherent interconnect (CCI) that is capable of monitoring bus transactions
+  and manage coherency, TLB invalidations and memory barriers.
+
+  It allows snooping and distributed virtual memory message broadcast across
+  clusters, through memory mapped interface, with a global control register
+  space and multiple sets of interface control registers, one per slave
+  interface.
+
+properties:
+  $nodename:
+    pattern: "^cci(@[0-9a-f]+)?$"
+
+  compatible:
+    enum:
+      - arm,cci-400
+      - arm,cci-500
+      - arm,cci-550
+
+  reg:
+    maxItems: 1
+    description: >
+      Specifies base physical address of CCI control registers common to all
+      interfaces.
+
+  "#address-cells": true
+  "#size-cells": true
+  ranges: true
+
+patternProperties:
+  "^slave-if@[0-9a-f]+$":
+    type: object
+
+    properties:
+      compatible:
+        const: arm,cci-400-ctrl-if
+
+      interface-type:
+        enum:
+          - ace
+          - ace-lite
+
+      reg:
+        maxItems: 1
+
+    required:
+      - compatible
+      - interface-type
+      - reg
+
+    additionalProperties: false
+
+  "^pmu@[0-9a-f]+$":
+    type: object
+
+    properties:
+      compatible:
+        oneOf:
+          - const: arm,cci-400-pmu,r0
+          - const: arm,cci-400-pmu,r1
+          - const: arm,cci-400-pmu
+            deprecated: true
+            description: >
+              Permitted only where OS has secure access to CCI registers
+          - const: arm,cci-500-pmu,r0
+          - const: arm,cci-550-pmu,r0
+
+      interrupts:
+        minItems: 1
+        maxItems: 8
+        description: >
+          List of counter overflow interrupts, one per counter. The interrupts
+          must be specified starting with the cycle counter overflow interrupt,
+          followed by counter0 overflow interrupt, counter1 overflow
+          interrupt,...  ,counterN overflow interrupt.
+
+          The CCI PMU has an interrupt signal for each counter. The number of
+          interrupts must be equal to the number of counters.
+
+      reg:
+        maxItems: 1
+
+    required:
+      - compatible
+      - interrupts
+      - reg
+
+    additionalProperties: false
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - ranges
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+      / {
+          #address-cells = <2>;
+          #size-cells = <2>;
+
+          compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
+          model = "V2P-CA15_CA7";
+          arm,hbi = <0x249>;
+          interrupt-parent = <&gic>;
+
+          /*
+           * This CCI node corresponds to a CCI component whose control
+           * registers sits at address 0x000000002c090000.
+           *
+           * CCI slave interface @0x000000002c091000 is connected to dma
+           * controller dma0.
+           *
+           * CCI slave interface @0x000000002c094000 is connected to CPUs
+           * {CPU0, CPU1};
+           *
+           * CCI slave interface @0x000000002c095000 is connected to CPUs
+           * {CPU2, CPU3};
+           */
+
+          cpus {
+              #size-cells = <0>;
+              #address-cells = <1>;
+
+              CPU0: cpu@0 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a15";
+                  cci-control-port = <&cci_control1>;
+                  reg = <0x0>;
+              };
+
+              CPU1: cpu@1 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a15";
+                  cci-control-port = <&cci_control1>;
+                  reg = <0x1>;
+              };
+
+              CPU2: cpu@100 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a7";
+                  cci-control-port = <&cci_control2>;
+                  reg = <0x100>;
+              };
+
+              CPU3: cpu@101 {
+                  device_type = "cpu";
+                  compatible = "arm,cortex-a7";
+                  cci-control-port = <&cci_control2>;
+                  reg = <0x101>;
+              };
+          };
+
+          dma0: dma@3000000 {
+              /* compatible = "arm,pl330", "arm,primecell"; */
+              cci-control-port = <&cci_control0>;
+              reg = <0x0 0x3000000 0x0 0x1000>;
+              interrupts = <10>;
+              #dma-cells = <1>;
+              #dma-channels = <8>;
+              #dma-requests = <32>;
+          };
+
+          cci@2c090000 {
+              compatible = "arm,cci-400";
+              #address-cells = <1>;
+              #size-cells = <1>;
+              reg = <0x0 0x2c090000 0 0x1000>;
+              ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+              cci_control0: slave-if@1000 {
+                  compatible = "arm,cci-400-ctrl-if";
+                  interface-type = "ace-lite";
+                  reg = <0x1000 0x1000>;
+              };
+
+              cci_control1: slave-if@4000 {
+                  compatible = "arm,cci-400-ctrl-if";
+                  interface-type = "ace";
+                  reg = <0x4000 0x1000>;
+              };
+
+              cci_control2: slave-if@5000 {
+                  compatible = "arm,cci-400-ctrl-if";
+                  interface-type = "ace";
+                  reg = <0x5000 0x1000>;
+              };
+
+              pmu@9000 {
+                  compatible = "arm,cci-400-pmu";
+                  reg = <0x9000 0x5000>;
+                  interrupts = <0 101 4>,
+                    <0 102 4>,
+                    <0 103 4>,
+                    <0 104 4>,
+                    <0 105 4>;
+              };
+          };
+      };
+
+...
diff --git a/Documentation/devicetree/bindings/arm/cci-control-port.yaml b/Documentation/devicetree/bindings/arm/cci-control-port.yaml
new file mode 100644
index 000000000000..c9114866213f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci-control-port.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CCI Interconnect Bus Masters binding
+
+maintainers:
+  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+
+description: |
+  Masters in the device tree connected to a CCI port (inclusive of CPUs
+  and their cpu nodes).
+
+select: true
+
+properties:
+  cci-control-port:
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+additionalProperties: true
+
+examples:
+  - |
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        cpu@0 {
+            compatible = "arm,cortex-a15";
+            device_type = "cpu";
+            cci-control-port = <&cci_control1>;
+            reg = <0>;
+        };
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
deleted file mode 100644
index 9600761f2d5b..000000000000
--- a/Documentation/devicetree/bindings/arm/cci.txt
+++ /dev/null
@@ -1,224 +0,0 @@
-=======================================================
-ARM CCI cache coherent interconnect binding description
-=======================================================
-
-ARM multi-cluster systems maintain intra-cluster coherency through a
-cache coherent interconnect (CCI) that is capable of monitoring bus
-transactions and manage coherency, TLB invalidations and memory barriers.
-
-It allows snooping and distributed virtual memory message broadcast across
-clusters, through memory mapped interface, with a global control register
-space and multiple sets of interface control registers, one per slave
-interface.
-
-* CCI interconnect node
-
-	Description: Describes a CCI cache coherent Interconnect component
-
-	Node name must be "cci".
-	Node's parent must be the root node /, and the address space visible
-	through the CCI interconnect is the same as the one seen from the
-	root node (ie from CPUs perspective as per DT standard).
-	Every CCI node has to define the following properties:
-
-	- compatible
-		Usage: required
-		Value type: <string>
-		Definition: must contain one of the following:
-			    "arm,cci-400"
-			    "arm,cci-500"
-			    "arm,cci-550"
-
-	- reg
-		Usage: required
-		Value type: Integer cells. A register entry, expressed as a pair
-			    of cells, containing base and size.
-		Definition: A standard property. Specifies base physical
-			    address of CCI control registers common to all
-			    interfaces.
-
-	- ranges:
-		Usage: required
-		Value type: Integer cells. An array of range entries, expressed
-			    as a tuple of cells, containing child address,
-			    parent address and the size of the region in the
-			    child address space.
-		Definition: A standard property. Follow rules in the Devicetree
-			    Specification for hierarchical bus addressing. CCI
-			    interfaces addresses refer to the parent node
-			    addressing scheme to declare their register bases.
-
-	CCI interconnect node can define the following child nodes:
-
-	- CCI control interface nodes
-
-		Node name must be "slave-if".
-		Parent node must be CCI interconnect node.
-
-		A CCI control interface node must contain the following
-		properties:
-
-		- compatible
-			Usage: required
-			Value type: <string>
-			Definition: must be set to
-				    "arm,cci-400-ctrl-if"
-
-		- interface-type:
-			Usage: required
-			Value type: <string>
-			Definition: must be set to one of {"ace", "ace-lite"}
-				    depending on the interface type the node
-				    represents.
-
-		- reg:
-			Usage: required
-			Value type: Integer cells. A register entry, expressed
-				    as a pair of cells, containing base and
-				    size.
-			Definition: the base address and size of the
-				    corresponding interface programming
-				    registers.
-
-	- CCI PMU node
-
-		Parent node must be CCI interconnect node.
-
-		A CCI pmu node must contain the following properties:
-
-		- compatible
-			Usage: required
-			Value type: <string>
-			Definition: Must contain one of:
-				 "arm,cci-400-pmu,r0"
-				 "arm,cci-400-pmu,r1"
-				 "arm,cci-400-pmu"  - DEPRECATED, permitted only where OS has
-						      secure access to CCI registers
-				 "arm,cci-500-pmu,r0"
-				 "arm,cci-550-pmu,r0"
-		- reg:
-			Usage: required
-			Value type: Integer cells. A register entry, expressed
-				    as a pair of cells, containing base and
-				    size.
-			Definition: the base address and size of the
-				    corresponding interface programming
-				    registers.
-
-		- interrupts:
-			Usage: required
-			Value type: Integer cells. Array of interrupt specifier
-				    entries, as defined in
-				    ../interrupt-controller/interrupts.txt.
-			Definition: list of counter overflow interrupts, one per
-				    counter. The interrupts must be specified
-				    starting with the cycle counter overflow
-				    interrupt, followed by counter0 overflow
-				    interrupt, counter1 overflow interrupt,...
-				    ,counterN overflow interrupt.
-
-				    The CCI PMU has an interrupt signal for each
-				    counter. The number of interrupts must be
-				    equal to the number of counters.
-
-* CCI interconnect bus masters
-
-	Description: masters in the device tree connected to a CCI port
-		     (inclusive of CPUs and their cpu nodes).
-
-	A CCI interconnect bus master node must contain the following
-	properties:
-
-	- cci-control-port:
-		Usage: required
-		Value type: <phandle>
-		Definition: a phandle containing the CCI control interface node
-			    the master is connected to.
-
-Example:
-
-	cpus {
-		#size-cells = <0>;
-		#address-cells = <1>;
-
-		CPU0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			cci-control-port = <&cci_control1>;
-			reg = <0x0>;
-		};
-
-		CPU1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			cci-control-port = <&cci_control1>;
-			reg = <0x1>;
-		};
-
-		CPU2: cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			cci-control-port = <&cci_control2>;
-			reg = <0x100>;
-		};
-
-		CPU3: cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			cci-control-port = <&cci_control2>;
-			reg = <0x101>;
-		};
-
-	};
-
-	dma0: dma@3000000 {
-		compatible = "arm,pl330", "arm,primecell";
-		cci-control-port = <&cci_control0>;
-		reg = <0x0 0x3000000 0x0 0x1000>;
-		interrupts = <10>;
-		#dma-cells = <1>;
-		#dma-channels = <8>;
-		#dma-requests = <32>;
-	};
-
-	cci@2c090000 {
-		compatible = "arm,cci-400";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x0 0x2c090000 0 0x1000>;
-		ranges = <0x0 0x0 0x2c090000 0x10000>;
-
-		cci_control0: slave-if@1000 {
-			compatible = "arm,cci-400-ctrl-if";
-			interface-type = "ace-lite";
-			reg = <0x1000 0x1000>;
-		};
-
-		cci_control1: slave-if@4000 {
-			compatible = "arm,cci-400-ctrl-if";
-			interface-type = "ace";
-			reg = <0x4000 0x1000>;
-		};
-
-		cci_control2: slave-if@5000 {
-			compatible = "arm,cci-400-ctrl-if";
-			interface-type = "ace";
-			reg = <0x5000 0x1000>;
-		};
-
-		pmu@9000 {
-			 compatible = "arm,cci-400-pmu";
-			 reg = <0x9000 0x5000>;
-			 interrupts = <0 101 4>,
-				      <0 102 4>,
-				      <0 103 4>,
-				      <0 104 4>,
-				      <0 105 4>;
-		};
-	};
-
-This CCI node corresponds to a CCI component whose control registers sits
-at address 0x000000002c090000.
-CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
-CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
-CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 9a2432a88074..35b552ce8803 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -240,6 +240,8 @@ properties:
       DMIPS/MHz, relative to highest capacity-dmips-mhz
       in the system.
 
+  cci-control-port: true
+
   dynamic-power-coefficient:
     $ref: '/schemas/types.yaml#/definitions/uint32'
     description:
-- 
2.31.1


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  parent reply	other threads:[~2021-09-01  9:19 UTC|newest]

Thread overview: 259+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01  9:18 [PATCH v2 00/52] ARM: dts: Last round of DT schema fixes Maxime Ripard
2021-09-01  9:18 ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 01/52] ASoC: dt-bindings: Add WM8978 Binding Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01 10:11   ` Charles Keepax
2021-09-01 10:11     ` Charles Keepax
2021-09-01 10:11     ` Charles Keepax
2021-09-01 14:39   ` Mark Brown
2021-09-01 14:39     ` Mark Brown
2021-09-01 14:39     ` Mark Brown
2021-09-03 10:37     ` Maxime Ripard
2021-09-03 10:37       ` Maxime Ripard
2021-09-03 10:37       ` Maxime Ripard
2021-09-03 11:36       ` Mark Brown
2021-09-03 11:36         ` Mark Brown
2021-09-03 11:36         ` Mark Brown
2021-09-01  9:18 ` [PATCH v2 02/52] ASoC: dt-bindings: Convert Bluetooth SCO Link binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 17:52   ` Rob Herring
2021-09-03 17:52     ` Rob Herring
2021-09-03 17:52     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 03/52] ASoC: dt-bindings: Convert SPDIF Transmitter " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 04/52] ASoC: dt-bindings: Convert Simple Amplifier " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 05/52] dt-bindings: Convert Reserved Memory " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01 12:10   ` Tom Rini
2021-09-01 12:10     ` Tom Rini
2021-09-03 18:08   ` Rob Herring
2021-09-03 18:08     ` Rob Herring
2021-09-01  9:18 ` Maxime Ripard [this message]
2021-09-01  9:18   ` [PATCH v2 06/52] dt-bindings: arm: Convert ARM CCI-400 " Maxime Ripard
2021-09-03 18:12   ` Rob Herring
2021-09-03 18:12     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 07/52] dt-bindings: bluetooth: broadcom: Fix clocks check Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-16 22:53   ` Linus Walleij
2021-09-16 22:53     ` Linus Walleij
2021-09-01  9:18 ` [PATCH v2 08/52] dt-bindings: bluetooth: realtek: Add missing max-speed Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 09/52] dt-bindings: clocks: Fix typo in the H6 compatible Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 20:50   ` Jernej Škrabec
2021-09-05 20:50     ` Jernej Škrabec
2021-09-06 13:34     ` Maxime Ripard
2021-09-06 13:34       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 10/52] dt-bindings: display: Move idk-1110wr to panel-lvds Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 18:30   ` Rob Herring
2021-09-03 18:30     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 11/52] dt-bindings: display: Move idk-2121wr " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 12/52] dt-bindings: display: Move ee101ia-01d " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 13/52] dt-bindings: display: aa104xd12: Remove unused vcc-supply Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 18:30   ` Rob Herring
2021-09-03 18:30     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 14/52] dt-bindings: display: aa104xd12: Fix data-mapping Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 18:31   ` Rob Herring
2021-09-03 18:31     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 15/52] dt-bindings: display: Move aa104xd12 to panel-lvds Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 16/52] dt-bindings: display: aa121td01: Remove unused vcc-supply Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 18:31   ` Rob Herring
2021-09-03 18:31     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 17/52] dt-bindings: display: aa121td01: Fix data-mapping Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 18:31   ` Rob Herring
2021-09-03 18:31     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 18/52] dt-bindings: display: Move aa121td01 to panel-lvds Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 19/52] dt-bindings: display: Move gktw70sdae4se " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 20/52] dt-bindings: display: panel-lvds: Document missing panel compatibles Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 21/52] dt-bindings: gnss: Convert UBlox Neo-6M binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:27   ` Rob Herring
2021-09-03 19:27     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 22/52] dt-bindings: gpio: Convert X-Powers AXP209 GPIO " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:32   ` Rob Herring
2021-09-03 19:32     ` Rob Herring
2021-09-19  7:56   ` Bartosz Golaszewski
2021-09-19  7:56     ` Bartosz Golaszewski
2021-09-01  9:18 ` [PATCH v2 23/52] dt-bindings: hwmon: Add IIO HWMON binding Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:33   ` Rob Herring
2021-09-03 19:33     ` Rob Herring
2021-09-04 15:03   ` Guenter Roeck
2021-09-04 15:03     ` Guenter Roeck
2021-09-01  9:18 ` [PATCH v2 24/52] dt-bindings: input: Convert Silead GSL1680 binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:35   ` Rob Herring
2021-09-03 19:35     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 25/52] dt-bindings: interconnect: sunxi: Add R40 MBUS compatible Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 20:53   ` Jernej Škrabec
2021-09-05 20:53     ` Jernej Škrabec
2021-10-15  8:08   ` (subset) " Maxime Ripard
2021-10-15  8:08     ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 26/52] dt-bindings: media: ti,cal: Fix example Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:36   ` Rob Herring
2021-09-03 19:36     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 27/52] dt-bindings: media: Convert OV5640 binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:39   ` Rob Herring
2021-09-03 19:39     ` Rob Herring
2021-10-14 13:48   ` Geert Uytterhoeven
2021-10-14 13:48     ` Geert Uytterhoeven
2021-09-01  9:18 ` [PATCH v2 28/52] dt-bindings: mfd: Convert X-Powers AC100 " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:40   ` Rob Herring
2021-09-03 19:40     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 29/52] dt-bindings: mfd: Convert X-Powers AXP " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:44   ` Rob Herring
2021-09-03 19:44     ` Rob Herring
2021-09-06  9:02     ` Lee Jones
2021-09-06  9:02       ` Lee Jones
2021-09-14  7:12       ` Maxime Ripard
2021-09-14  7:12         ` Maxime Ripard
2021-09-14 12:57         ` Rob Herring
2021-09-14 12:57           ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 30/52] dt-bindings: mmc: Convert MMC Card " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:45   ` Rob Herring
2021-09-03 19:45     ` Rob Herring
2021-09-06 17:10   ` Ulf Hansson
2021-09-06 17:10     ` Ulf Hansson
2021-09-01  9:18 ` [PATCH v2 31/52] dt-bindings: net: dwmac: Fix typo in the R40 compatible Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 20:56   ` Jernej Škrabec
2021-09-05 20:56     ` Jernej Škrabec
2021-09-01  9:18 ` [PATCH v2 32/52] dt-bindings: net: wireless: Convert ESP ESP8089 binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 33/52] dt-bindings: regulator: Convert SY8106A " Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 34/52] dt-bindings: sunxi: Add CPU Configuration Controller Binding Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:00   ` Jernej Škrabec
2021-09-05 21:00     ` Jernej Škrabec
2021-09-06 13:35     ` Maxime Ripard
2021-09-06 13:35       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 35/52] dt-bindings: sunxi: Add Allwinner A80 PRCM Binding Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:01   ` Jernej Škrabec
2021-09-05 21:01     ` Jernej Škrabec
2021-09-06 13:36     ` Maxime Ripard
2021-09-06 13:36       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 36/52] dt-bindings: usb: Convert SMSC USB3503 binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:47   ` Rob Herring
2021-09-03 19:47     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 37/52] dt-bindings: usb: dwc3: Fix usb-phy check Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-01 12:36   ` Felipe Balbi
2021-09-01 12:36     ` Felipe Balbi
2021-09-03 19:49     ` Rob Herring
2021-09-03 19:49       ` Rob Herring
2021-09-03 19:50   ` Rob Herring
2021-09-03 19:50     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 38/52] dt-bindings: w1: Convert 1-Wire GPIO binding to a schema Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-03 19:50   ` Rob Herring
2021-09-03 19:50     ` Rob Herring
2021-09-01  9:18 ` [PATCH v2 39/52] ARM: dts: sunxi: Rename power-supply names Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:02   ` Jernej Škrabec
2021-09-05 21:02     ` Jernej Škrabec
2021-09-06 13:36     ` Maxime Ripard
2021-09-06 13:36       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 40/52] ARM: dts: sunxi: Rename gpio pinctrl names Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:03   ` Jernej Škrabec
2021-09-05 21:03     ` Jernej Škrabec
2021-09-06 13:37     ` Maxime Ripard
2021-09-06 13:37       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 41/52] ARM: dts: sunxi: Fix OPP arrays Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:04   ` Jernej Škrabec
2021-09-05 21:04     ` Jernej Škrabec
2021-09-06 13:37     ` Maxime Ripard
2021-09-06 13:37       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 42/52] ARM: dts: sunxi: Fix OPPs node name Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:05   ` Jernej Škrabec
2021-09-05 21:05     ` Jernej Škrabec
2021-09-06 13:38     ` Maxime Ripard
2021-09-06 13:38       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 43/52] ARM: dts: sunxi: Fix the SPI NOR node names Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:06   ` Jernej Škrabec
2021-09-05 21:06     ` Jernej Škrabec
2021-09-06 13:38     ` Maxime Ripard
2021-09-06 13:38       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 44/52] ARM: dts: v3s: Remove useless DMA properties Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:08   ` Jernej Škrabec
2021-09-05 21:08     ` Jernej Škrabec
2021-09-01  9:18 ` [PATCH v2 45/52] ARM: dts: tbs711: Fix touchscreen compatible Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:11   ` Jernej Škrabec
2021-09-05 21:11     ` Jernej Škrabec
2021-09-06 13:38     ` Maxime Ripard
2021-09-06 13:38       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 46/52] ARM: dts: cubieboard4: Remove the dumb-vga-dac compatible Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:12   ` Jernej Škrabec
2021-09-05 21:12     ` Jernej Škrabec
2021-09-06 13:39     ` Maxime Ripard
2021-09-06 13:39       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 47/52] arm64: dts: allwinner: h5: Fix GPU thermal zone node name Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:12   ` Jernej Škrabec
2021-09-05 21:12     ` Jernej Škrabec
2021-09-06 13:39     ` Maxime Ripard
2021-09-06 13:39       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 48/52] arm64: dts: allwinner: h6: Fix de3 parent clocks ordering Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:13   ` Jernej Škrabec
2021-09-05 21:13     ` Jernej Škrabec
2021-09-06 13:40     ` Maxime Ripard
2021-09-06 13:40       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 49/52] arm64: dts: allwinner: a100: Fix thermal zone node name Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:13   ` Jernej Škrabec
2021-09-05 21:13     ` Jernej Škrabec
2021-09-06 13:40     ` Maxime Ripard
2021-09-06 13:40       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 50/52] arm64: dts: allwinner: pinetab: Change regulator node name to avoid warning Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:14   ` Jernej Škrabec
2021-09-05 21:14     ` Jernej Škrabec
2021-09-06 13:41     ` Maxime Ripard
2021-09-06 13:41       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 51/52] arm64: dts: allwinner: teres-i: Add missing reg Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:14   ` Jernej Škrabec
2021-09-05 21:14     ` Jernej Škrabec
2021-09-06 13:41     ` Maxime Ripard
2021-09-06 13:41       ` Maxime Ripard
2021-09-01  9:18 ` [PATCH v2 52/52] arm64: dts: allwinner: teres-i: Remove wakekup-source from the PMIC Maxime Ripard
2021-09-01  9:18   ` Maxime Ripard
2021-09-05 21:24   ` Jernej Škrabec
2021-09-05 21:24     ` Jernej Škrabec
2021-09-06 13:41     ` Maxime Ripard
2021-09-06 13:41       ` Maxime Ripard
2021-09-13 10:53 ` (subset) [PATCH v2 00/52] ARM: dts: Last round of DT schema fixes Mark Brown
2021-09-13 10:53   ` Mark Brown

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