From: Igor Mammedov <imammedo@redhat.com>
To: Shashi Mallela <shashi.mallela@linaro.org>
Cc: peter.maydell@linaro.org, mst@redhat.com, rad@semihalf.com,
qemu-devel@nongnu.org, eric.auger@redhat.com,
qemu-arm@nongnu.org, leif@nuviainc.com
Subject: Re: [PATCH v7 10/10] tests/data/acpi/virt: Update IORT files for ITS
Date: Wed, 1 Sep 2021 10:03:24 +0200 [thread overview]
Message-ID: <20210901100324.3ce458f6@redhat.com> (raw)
In-Reply-To: <20210805223002.144855-11-shashi.mallela@linaro.org>
not directly related to the patch but while I was testing IORT testcase
(https://github.com/imammedo/qemu acpi-tests)
after rebase to 6.1, I get test failure due to change in MADT table vs
expected blobs made in 6.0 time and it does look like ABI change
(what is bad, it also happens to virt-6.0 machine type).
Can ARM folks check if we didn't break something?
acpi-test: Warning! APIC mismatch. Actual [asl:/tmp/asl-1TCW80.dsl, aml:/tmp/aml-OUIW80], Expected [asl:/tmp/asl-O8DW80.dsl, aml:tests/data/acpi/virt/APIC].
--- /tmp/asl-O8DW80.dsl 2021-09-01 03:49:02.311023292 -0400
+++ /tmp/asl-1TCW80.dsl 2021-09-01 03:49:02.311023292 -0400
@@ -1,78 +1,82 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/APIC, Wed Sep 1 03:49:02 2021
+ * Disassembly of /tmp/aml-OUIW80, Wed Sep 1 03:49:02 2021
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
-[004h 0004 4] Table Length : 000000A8
+[004h 0004 4] Table Length : 000000B4
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : 50
+[009h 0009 1] Checksum : CA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : 00000000
[028h 0040 4] Flags (decoded below) : 00000000
PC-AT Compatibility : 0
[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor]
[02Dh 0045 1] Length : 18
[02Eh 0046 2] Reserved : 0000
[030h 0048 4] Local GIC Hardware ID : 00000000
[034h 0052 8] Base Address : 0000000008000000
[03Ch 0060 4] Interrupt Base : 00000000
-[040h 0064 1] Version : 02
+[040h 0064 1] Version : 03
[041h 0065 3] Reserved : 000000
[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller]
[045h 0069 1] Length : 4C
[046h 0070 2] Reserved : 0000
[048h 0072 4] CPU Interface Number : 00000000
[04Ch 0076 4] Processor UID : 00000000
[050h 0080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[054h 0084 4] Parking Protocol Version : 00000000
[058h 0088 4] Performance Interrupt : 00000017
[05Ch 0092 8] Parked Address : 0000000000000000
-[064h 0100 8] Base Address : 0000000008010000
-[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000
-[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000
+[064h 0100 8] Base Address : 0000000000000000
+[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000
+[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000
[07Ch 0124 4] Virtual GIC Interrupt : 00000000
[080h 0128 8] Redistributor Base Address : 0000000000000000
[088h 0136 8] ARM MPIDR : 0000000000000000
/**** ACPI subtable terminates early - may be older version (dump table) */
-[090h 0144 1] Subtable Type : 0D [Generic MSI Frame]
-[091h 0145 1] Length : 18
+[090h 0144 1] Subtable Type : 0E [Generic Interrupt Redistributor]
+[091h 0145 1] Length : 10
[092h 0146 2] Reserved : 0000
-[094h 0148 4] MSI Frame ID : 00000000
-[098h 0152 8] Base Address : 0000000008020000
-[0A0h 0160 4] Flags (decoded below) : 00000001
- Select SPI : 1
-[0A4h 0164 2] SPI Count : 0040
-[0A6h 0166 2] SPI Base : 0050
+[094h 0148 8] Base Address : 00000000080A0000
+[09Ch 0156 4] Length : 00F60000
-Raw Table Data: Length 168 (0xA8)
+[0A0h 0160 1] Subtable Type : 0F [Generic Interrupt Translator]
+[0A1h 0161 1] Length : 14
+[0A2h 0162 2] Reserved : 0000
+[0A4h 0164 4] Translation ID : 00000000
+[0A8h 0168 8] Base Address : 0000000008080000
+[0B0h 0176 4] Reserved : 00000000
next prev parent reply other threads:[~2021-09-01 8:06 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 22:29 [PATCH v7 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-08-05 22:29 ` [PATCH v7 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-08-10 7:35 ` Neil Armstrong
2021-08-05 22:29 ` [PATCH v7 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-08-10 7:35 ` Neil Armstrong
2021-08-05 22:29 ` [PATCH v7 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela
2021-08-10 7:35 ` Neil Armstrong
2021-08-05 22:29 ` [PATCH v7 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-08-06 8:58 ` Neil Armstrong
2021-08-06 13:06 ` shashi.mallela
2021-08-05 22:29 ` [PATCH v7 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-08-10 7:35 ` Neil Armstrong
2021-08-05 22:29 ` [PATCH v7 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-08-10 7:35 ` Neil Armstrong
2021-08-05 22:29 ` [PATCH v7 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
2021-08-05 22:30 ` [PATCH v7 08/10] tests/data/acpi/virt: Add IORT files for ITS Shashi Mallela
2021-08-06 11:10 ` Igor Mammedov
2021-08-05 22:30 ` [PATCH v7 09/10] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-08-06 11:09 ` Igor Mammedov
2021-08-12 16:54 ` shashi.mallela
2021-08-05 22:30 ` [PATCH v7 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela
2021-08-06 11:11 ` Igor Mammedov
2021-09-01 8:03 ` Igor Mammedov [this message]
2021-09-01 8:06 ` Peter Maydell
2021-09-01 9:02 ` Igor Mammedov
2021-09-01 9:45 ` Peter Maydell
2021-09-01 10:04 ` Igor Mammedov
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