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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/51] arm: Move system PPB container handling to armv7m
Date: Wed,  1 Sep 2021 11:36:31 +0100	[thread overview]
Message-ID: <20210901103653.13435-30-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org>

Instead of having the NVIC device provide a single sysbus memory
region covering the whole of the "System PPB" space, which implements
the default behaviour for unimplemented ranges and provides the NS
alias window to the sysregs as well as the main sysreg MR, move this
handling to the container armv7m device.  The NVIC now provides a
single memory region which just implements the system registers.
This consolidates all the handling of "map various devices in the
PPB" into the armv7m container where it belongs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-4-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h       |   4 +
 include/hw/intc/armv7m_nvic.h |   3 -
 hw/arm/armv7m.c               | 100 ++++++++++++++++++++++-
 hw/intc/armv7m_nvic.c         | 145 +---------------------------------
 4 files changed, 107 insertions(+), 145 deletions(-)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index 360c35c5fb2..fe8b248a6c6 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -77,6 +77,10 @@ struct ARMv7MState {
      * NS systick device if appropriate.
      */
     MemoryRegion systick_ns_mem;
+    /* Ditto, for the sysregs region provided by the NVIC */
+    MemoryRegion sysreg_ns_mem;
+    /* MR providing default PPB behaviour */
+    MemoryRegion defaultmem;
 
     /* Properties */
     char *cpu_type;
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 6a6a99090c7..0180c7b0ca1 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -80,9 +80,6 @@ struct NVICState {
     int vectpending_prio; /* group prio of the exeception in vectpending */
 
     MemoryRegion sysregmem;
-    MemoryRegion sysreg_ns_mem;
-    MemoryRegion container;
-    MemoryRegion defaultmem;
 
     uint32_t num_irq;
     qemu_irq excpout;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 364ac069702..899159f70b1 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -18,6 +18,7 @@
 #include "sysemu/reset.h"
 #include "qemu/error-report.h"
 #include "qemu/module.h"
+#include "qemu/log.h"
 #include "target/arm/idau.h"
 
 /* Bitbanded IO.  Each word corresponds to a single bit.  */
@@ -203,6 +204,43 @@ static const MemoryRegionOps v7m_systick_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
+/*
+ * Unassigned portions of the PPB space are RAZ/WI for privileged
+ * accesses, and fault for non-privileged accesses.
+ */
+static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
+                                    uint64_t *data, unsigned size,
+                                    MemTxAttrs attrs)
+{
+    qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
+                  (uint32_t)addr);
+    if (attrs.user) {
+        return MEMTX_ERROR;
+    }
+    *data = 0;
+    return MEMTX_OK;
+}
+
+static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
+                                     uint64_t value, unsigned size,
+                                     MemTxAttrs attrs)
+{
+    qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
+                  (uint32_t)addr);
+    if (attrs.user) {
+        return MEMTX_ERROR;
+    }
+    return MEMTX_OK;
+}
+
+static const MemoryRegionOps ppb_default_ops = {
+    .read_with_attrs = ppb_default_read,
+    .write_with_attrs = ppb_default_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 8,
+};
+
 static void armv7m_instance_init(Object *obj)
 {
     ARMv7MState *s = ARMV7M(obj);
@@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
     qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
     qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
 
+    /*
+     * We map various devices into the container MR at their architected
+     * addresses. In particular, we map everything corresponding to the
+     * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff
+     * and includes the NVIC, the System Control Space (system registers),
+     * the systick timer, and for CPUs with the Security extension an NS
+     * banked version of all of these.
+     *
+     * The default behaviour for unimplemented registers/ranges
+     * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
+     * is to RAZ/WI for privileged access and BusFault for non-privileged
+     * access.
+     *
+     * The NVIC and System Control Space (SCS) starts at 0xe000e000
+     * and looks like this:
+     *  0x004 - ICTR
+     *  0x010 - 0xff - systick
+     *  0x100..0x7ec - NVIC
+     *  0x7f0..0xcff - Reserved
+     *  0xd00..0xd3c - SCS registers
+     *  0xd40..0xeff - Reserved or Not implemented
+     *  0xf00 - STIR
+     *
+     * Some registers within this space are banked between security states.
+     * In v8M there is a second range 0xe002e000..0xe002efff which is the
+     * NonSecure alias SCS; secure accesses to this behave like NS accesses
+     * to the main SCS range, and non-secure accesses (including when
+     * the security extension is not implemented) are RAZ/WI.
+     * Note that both the main SCS range and the alias range are defined
+     * to be exempt from memory attribution (R_BLJT) and so the memory
+     * transaction attribute always matches the current CPU security
+     * state (attrs.secure == env->v7m.secure). In the v7m_sysreg_ns_ops
+     * wrappers we change attrs.secure to indicate the NS access; so
+     * generally code determining which banked register to use should
+     * use attrs.secure; code determining actual behaviour of the system
+     * should use env->v7m.secure.
+     *
+     * Within the PPB space, some MRs overlap, and the priority
+     * of overlapping regions is:
+     *  - default region (for RAZ/WI and BusFault) : -1
+     *  - system register regions (provided by the NVIC) : 0
+     *  - systick : 1
+     * This is because the systick device is a small block of registers
+     * in the middle of the other system control registers.
+     */
+
+    memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
+                          "nvic-default", 0x100000);
+    memory_region_add_subregion_overlap(&s->container, 0xe0000000,
+                                        &s->defaultmem, -1);
+
     /* Wire the NVIC up to the CPU */
     sbd = SYS_BUS_DEVICE(&s->nvic);
     sysbus_connect_irq(sbd, 0,
                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 
-    memory_region_add_subregion(&s->container, 0xe0000000,
+    memory_region_add_subregion(&s->container, 0xe000e000,
                                 sysbus_mmio_get_region(sbd, 0));
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
+        /* Create the NS alias region for the NVIC sysregs */
+        memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
+                              &v7m_sysreg_ns_ops,
+                              sysbus_mmio_get_region(sbd, 0),
+                              "nvic_sysregs_ns", 0x1000);
+        memory_region_add_subregion(&s->container, 0xe002e000,
+                                    &s->sysreg_ns_mem);
+    }
 
     /* Create and map the systick devices */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 2b3e79a3da9..13df002ce4d 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2470,90 +2470,6 @@ static const MemoryRegionOps nvic_sysreg_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
-                                        uint64_t value, unsigned size,
-                                        MemTxAttrs attrs)
-{
-    MemoryRegion *mr = opaque;
-
-    if (attrs.secure) {
-        /* S accesses to the alias act like NS accesses to the real region */
-        attrs.secure = 0;
-        return memory_region_dispatch_write(mr, addr, value,
-                                            size_memop(size) | MO_TE, attrs);
-    } else {
-        /* NS attrs are RAZ/WI for privileged, and BusFault for user */
-        if (attrs.user) {
-            return MEMTX_ERROR;
-        }
-        return MEMTX_OK;
-    }
-}
-
-static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
-                                       uint64_t *data, unsigned size,
-                                       MemTxAttrs attrs)
-{
-    MemoryRegion *mr = opaque;
-
-    if (attrs.secure) {
-        /* S accesses to the alias act like NS accesses to the real region */
-        attrs.secure = 0;
-        return memory_region_dispatch_read(mr, addr, data,
-                                           size_memop(size) | MO_TE, attrs);
-    } else {
-        /* NS attrs are RAZ/WI for privileged, and BusFault for user */
-        if (attrs.user) {
-            return MEMTX_ERROR;
-        }
-        *data = 0;
-        return MEMTX_OK;
-    }
-}
-
-static const MemoryRegionOps nvic_sysreg_ns_ops = {
-    .read_with_attrs = nvic_sysreg_ns_read,
-    .write_with_attrs = nvic_sysreg_ns_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-/*
- * Unassigned portions of the PPB space are RAZ/WI for privileged
- * accesses, and fault for non-privileged accesses.
- */
-static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
-                                    uint64_t *data, unsigned size,
-                                    MemTxAttrs attrs)
-{
-    qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
-                  (uint32_t)addr);
-    if (attrs.user) {
-        return MEMTX_ERROR;
-    }
-    *data = 0;
-    return MEMTX_OK;
-}
-
-static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
-                                     uint64_t value, unsigned size,
-                                     MemTxAttrs attrs)
-{
-    qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
-                  (uint32_t)addr);
-    if (attrs.user) {
-        return MEMTX_ERROR;
-    }
-    return MEMTX_OK;
-}
-
-static const MemoryRegionOps ppb_default_ops = {
-    .read_with_attrs = ppb_default_read,
-    .write_with_attrs = ppb_default_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid.min_access_size = 1,
-    .valid.max_access_size = 8,
-};
-
 static int nvic_post_load(void *opaque, int version_id)
 {
     NVICState *s = opaque;
@@ -2770,66 +2686,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
     s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
 
     /*
-     * This device provides a single sysbus memory region which
-     * represents the whole of the "System PPB" space. This is the
-     * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
-     * the System Control Space (system registers), the systick timer,
-     * and for CPUs with the Security extension an NS banked version
-     * of all of these.
-     *
-     * The default behaviour for unimplemented registers/ranges
-     * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
-     * is to RAZ/WI for privileged access and BusFault for non-privileged
-     * access.
-     *
-     * The NVIC and System Control Space (SCS) starts at 0xe000e000
-     * and looks like this:
-     *  0x004 - ICTR
-     *  0x010 - 0xff - systick
-     *  0x100..0x7ec - NVIC
-     *  0x7f0..0xcff - Reserved
-     *  0xd00..0xd3c - SCS registers
-     *  0xd40..0xeff - Reserved or Not implemented
-     *  0xf00 - STIR
-     *
-     * Some registers within this space are banked between security states.
-     * In v8M there is a second range 0xe002e000..0xe002efff which is the
-     * NonSecure alias SCS; secure accesses to this behave like NS accesses
-     * to the main SCS range, and non-secure accesses (including when
-     * the security extension is not implemented) are RAZ/WI.
-     * Note that both the main SCS range and the alias range are defined
-     * to be exempt from memory attribution (R_BLJT) and so the memory
-     * transaction attribute always matches the current CPU security
-     * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
-     * wrappers we change attrs.secure to indicate the NS access; so
-     * generally code determining which banked register to use should
-     * use attrs.secure; code determining actual behaviour of the system
-     * should use env->v7m.secure.
-     *
-     * The container covers the whole PPB space. Within it the priority
-     * of overlapping regions is:
-     *  - default region (for RAZ/WI and BusFault) : -1
-     *  - system register regions : 0
-     *  - systick : 1
-     * This is because the systick device is a small block of registers
-     * in the middle of the other system control registers.
+     * This device provides a single memory region which covers the
+     * sysreg/NVIC registers from 0xE000E000 .. 0xE000EFFF, with the
+     * exception of the systick timer registers 0xE000E010 .. 0xE000E0FF.
      */
-    memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
-    memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
-                          "nvic-default", 0x100000);
-    memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
     memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
                           "nvic_sysregs", 0x1000);
-    memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
-
-    if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
-        memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
-                              &nvic_sysreg_ns_ops, &s->sysregmem,
-                              "nvic_sysregs_ns", 0x1000);
-        memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
-    }
-
-    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysregmem);
 }
 
 static void armv7m_nvic_instance_init(Object *obj)
-- 
2.20.1



  parent reply	other threads:[~2021-09-01 10:49 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01 10:36 [PULL 00/51] target-arm queue Peter Maydell
2021-09-01 10:36 ` [PULL 01/51] tests: Remove uses of deprecated raspi2/raspi3 machine names Peter Maydell
2021-09-01 10:36 ` [PULL 02/51] hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases Peter Maydell
2021-09-01 10:36 ` [PULL 03/51] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix Peter Maydell
2021-09-01 10:36 ` [PULL 04/51] hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans Peter Maydell
2021-09-01 10:36 ` [PULL 05/51] hw: Add compat machines for 6.2 Peter Maydell
2021-09-01 10:36 ` [PULL 06/51] target/arm: Implement MVE VADD (floating-point) Peter Maydell
2021-09-01 10:36 ` [PULL 07/51] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM Peter Maydell
2021-09-01 10:36 ` [PULL 08/51] target/arm: Implement MVE VCADD Peter Maydell
2021-09-01 10:36 ` [PULL 09/51] target/arm: Implement MVE VFMA and VFMS Peter Maydell
2021-09-01 10:36 ` [PULL 10/51] target/arm: Implement MVE VCMUL and VCMLA Peter Maydell
2021-09-01 10:36 ` [PULL 11/51] target/arm: Implement MVE VMAXNMA and VMINNMA Peter Maydell
2021-09-01 10:36 ` [PULL 12/51] target/arm: Implement MVE scalar fp insns Peter Maydell
2021-09-01 10:36 ` [PULL 13/51] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS Peter Maydell
2021-09-01 10:36 ` [PULL 14/51] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode Peter Maydell
2021-09-01 10:36 ` [PULL 15/51] target/arm: Implement MVE FP max/min across vector Peter Maydell
2021-09-01 10:36 ` [PULL 16/51] target/arm: Implement MVE fp vector comparisons Peter Maydell
2021-09-01 10:36 ` [PULL 17/51] target/arm: Implement MVE fp scalar comparisons Peter Maydell
2021-09-01 10:36 ` [PULL 18/51] target/arm: Implement MVE VCVT between floating and fixed point Peter Maydell
2021-09-01 10:36 ` [PULL 19/51] target/arm: Implement MVE VCVT between fp and integer Peter Maydell
2021-09-01 10:36 ` [PULL 20/51] target/arm: Implement MVE VCVT with specified rounding mode Peter Maydell
2021-09-01 10:36 ` [PULL 21/51] target/arm: Implement MVE VCVT between single and half precision Peter Maydell
2021-09-01 10:36 ` [PULL 22/51] target/arm: Implement MVE VRINT insns Peter Maydell
2021-09-01 10:36 ` [PULL 23/51] target/arm: Enable MVE in Cortex-M55 Peter Maydell
2021-09-01 10:36 ` [PULL 24/51] target-arm: Add support for Fujitsu A64FX Peter Maydell
2021-09-01 10:36 ` [PULL 25/51] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Peter Maydell
2021-09-01 10:36 ` [PULL 26/51] tests/arm-cpu-features: Add A64FX processor related tests Peter Maydell
2021-09-01 10:36 ` [PULL 27/51] arm: Move M-profile RAS register block into its own device Peter Maydell
2021-09-01 10:36 ` [PULL 28/51] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
2021-09-01 10:36 ` Peter Maydell [this message]
2021-09-01 10:36 ` [PULL 30/51] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
2021-09-01 10:36 ` [PULL 31/51] hw/timer/armv7m_systick: Add input clocks Peter Maydell
2021-09-01 10:36 ` [PULL 32/51] hw/arm/armv7m: Create " Peter Maydell
2021-09-01 10:36 ` [PULL 33/51] armsse: Wire up systick cpuclk clock Peter Maydell
2021-09-01 10:36 ` [PULL 34/51] hw/arm/mps2.c: Connect up armv7m clocks Peter Maydell
2021-09-01 10:36 ` [PULL 35/51] clock: Provide builtin multiplier/divider Peter Maydell
2021-09-01 10:36 ` [PULL 36/51] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
2021-09-01 10:36 ` [PULL 37/51] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
2021-09-01 10:36 ` [PULL 38/51] hw/arm/stm32f205: " Peter Maydell
2021-09-01 10:36 ` [PULL 39/51] hw/arm/stm32f405: " Peter Maydell
2021-09-01 10:36 ` [PULL 40/51] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
2021-09-01 10:36 ` [PULL 41/51] hw/arm/nrf51: Wire up sysclk Peter Maydell
2021-09-01 10:36 ` [PULL 42/51] hw/arm/stellaris: split stellaris_sys_init() Peter Maydell
2021-09-01 10:36 ` [PULL 43/51] hw/arm/stellaris: Wire sysclk up to armv7m Peter Maydell
2021-09-01 10:36 ` [PULL 44/51] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Peter Maydell
2021-09-01 10:36 ` [PULL 45/51] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Peter Maydell
2021-09-01 10:36 ` [PULL 46/51] hw/arm/msf2-soc: Wire up refclk Peter Maydell
2021-09-01 10:36 ` [PULL 47/51] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Peter Maydell
2021-09-01 10:36 ` [PULL 48/51] hw/arm/stellaris: Fix code style issues in GPTM code Peter Maydell
2021-09-01 10:36 ` [PULL 49/51] hw/arm/stellaris: Split stellaris-gptm into its own file Peter Maydell
2021-09-01 10:36 ` [PULL 50/51] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Peter Maydell
2021-09-01 10:36 ` [PULL 51/51] arm: Remove system_clock_scale global Peter Maydell
2021-09-02  7:48 ` [PULL 00/51] target-arm queue Peter Maydell

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